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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT2.c
98 /// @brief INTERN_DVBT2 DVBT2
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT2_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 //#include "BinInfo.h"
114 #include "drvDMD_VD_MBX.h"
115 #include "drvDMD_INTERN_DVBT2.h"
116 #include "halDMD_INTERN_DVBT2.h"
117 #include "halDMD_INTERN_common.h"
118
119 extern void *memcpy(void *destination, const void *source, size_t num);
120
121 #define TEST_EMBEDED_DEMOD 0
122 //U8 load_data_variable=1;
123 //-----------------------------------------------------------------------
124 #define BIN_ID_INTERN_DVBT2_DEMOD BIN_ID_INTERN_DVBT
125
126 #define TDE_REG_BASE 0x2400
127 #define DIV_REG_BASE 0x2500
128 #define TR_REG_BASE 0x2600
129 #define FTN_REG_BASE 0x2700
130 #define FTNEXT_REG_BASE 0x2800
131
132
133
134 #if 0//ENABLE_SCAN_ONELINE_MSG
135 #define DBG_INTERN_DVBT2_ONELINE(x) x
136 #else
137 #define DBG_INTERN_DVBT2_ONELINE(x) // x
138 #endif
139
140 #ifdef MS_DEBUG
141 #define DBG_INTERN_DVBT2(x) x
142 #define DBG_GET_SIGNAL(x) x
143 #define DBG_INTERN_DVBT2_TIME(x) x
144 #define DBG_INTERN_DVBT2_LOCK(x) x
145 #else
146 #define DBG_INTERN_DVBT2(x) //x
147 #define DBG_GET_SIGNAL(x) //x
148 #define DBG_INTERN_DVBT2_TIME(x) // x
149 #define DBG_INTERN_DVBT2_LOCK(x) //x
150 #endif
151 #define DBG_DUMP_LOAD_DSP_TIME 0
152
153 #define INTERN_DVBT2_TS_SERIAL_INVERSION 0
154 #define INTERN_DVBT2_TS_PARALLEL_INVERSION 1
155 #define INTERN_DVBT2_DTV_DRIVING_LEVEL 1
156 #define INTERN_DVBT2_INTERNAL_DEBUG 1
157
158 #define SIGNAL_LEVEL_OFFSET 0.00
159 #define TAKEOVERPOINT -59.0
160 #define TAKEOVERRANGE 0.5
161 #define LOG10_OFFSET -0.21
162 #define INTERN_DVBT2_USE_SAR_3_ENABLE 0
163 #define INTERN_DVBT2_GET_TIME msAPI_Timer_GetTime0()
164
165
166 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
167 #define TUNER_VPP 2
168 #define IF_AGC_VPP 2
169 #else
170 #define TUNER_VPP 1
171 #define IF_AGC_VPP 2
172 #endif
173
174 #if (TUNER_VPP == 1)
175 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
176 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
177 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
178 #endif
179
180 /*BEG INTERN_DVBT2_DSPREG_TABLE*/
181 #define DVBT2_FS 24000
182
183 // BW: 0->1.7M, 1->5M, 2->6M, 3->7M, 4->8M, 5->10M
184 #define T2_BW_VAL 0x04
185 // FC: FC = FS = 5000 = 0x1388 (5.0MHz IF)
186 #define T2_FC_L_VAL 0x88 // 5.0M
187 #define T2_FC_H_VAL 0x13
188 #define T2_TS_SERIAL_VAL 0x00
189 #define T2_TS_CLK_RATE_VAL 0x06
190 #define T2_TS_OUT_INV_VAL 0x00
191 #define T2_TS_DATA_SWAP_VAL 0x00
192 #define T2_IF_AGC_INV_PWM_EN_VAL 0x00
193 #define T2_LITE_VAL 0x00
194 #define T2_AGC_REF_VAL 0x40
195
196 //#define DVBT2_BER_TH_HY 0.1
197
198 /*END INTERN_DVBT2_DSPREG_TABLE*/
199 //-----------------------------------------------------------------------
200 /****************************************************************
201 *Local Variables *
202 ****************************************************************/
203 static MS_BOOL bFECLock=0;
204 static MS_BOOL bP1Lock = 0;
205 static MS_U32 u32ChkScanTimeStart = 0;
206 static MS_U32 u32FecFirstLockTime=0;
207 static MS_U32 u32FecLastLockTime=0;
208 //static float fLDPCBerFiltered=-1;
209 //static float fBerFilteredDVBT2 = -1.0;
210
211 //Global Variables
212 //S_CMDPKTREG gsCmdPacket;
213 //U8 gCalIdacCh0, gCalIdacCh1;
214 extern MS_U32 u32DMD_DVBT2_DRAM_START_ADDR;
215 extern MS_U32 u32DMD_DVBT2_EQ_START_ADDR;
216 extern MS_U32 u32DMD_DVBT2_TDI_START_ADDR;
217 extern MS_U32 u32DMD_DVBT2_DJB_START_ADDR;
218 extern MS_U32 u32DMD_DVBT2_FW_START_ADDR;
219
220 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
221 MS_U8 INTERN_DVBT2_table[] = {
222 #include "fwDMD_INTERN_DVBT2.dat"
223 };
224
225 #endif
226 /*
227 static DMD_T2_SSI_DBM_NORDIGP1 dvbt2_ssi_dbm_nordigp1[] =
228 {
229 {_T2_QPSK, _T2_CR1Y2, -95.7},
230 {_T2_QPSK, _T2_CR3Y5, -94.4},
231 {_T2_QPSK, _T2_CR2Y3, -93.6},
232 {_T2_QPSK, _T2_CR3Y4, -92.6},
233 {_T2_QPSK, _T2_CR4Y5, -92.0},
234 {_T2_QPSK, _T2_CR5Y6, -91.5},
235
236 {_T2_16QAM, _T2_CR1Y2, -90.8},
237 {_T2_16QAM, _T2_CR3Y5, -89.1},
238 {_T2_16QAM, _T2_CR2Y3, -87.9},
239 {_T2_16QAM, _T2_CR3Y4, -86.7},
240 {_T2_16QAM, _T2_CR4Y5, -85.8},
241 {_T2_16QAM, _T2_CR5Y6, -85.2},
242
243 {_T2_64QAM, _T2_CR1Y2, -86.9},
244 {_T2_64QAM, _T2_CR3Y5, -84.6},
245 {_T2_64QAM, _T2_CR2Y3, -83.2},
246 {_T2_64QAM, _T2_CR3Y4, -81.4},
247 {_T2_64QAM, _T2_CR4Y5, -80.3},
248 {_T2_64QAM, _T2_CR5Y6, -79.7},
249
250 {_T2_256QAM, _T2_CR1Y2, -83.5},
251 {_T2_256QAM, _T2_CR3Y5, -80.4},
252 {_T2_256QAM, _T2_CR2Y3, -78.6},
253 {_T2_256QAM, _T2_CR3Y4, -76.0},
254 {_T2_256QAM, _T2_CR4Y5, -74.4},
255 {_T2_256QAM, _T2_CR5Y6, -73.3},
256 {_T2_QAM_UNKNOWN, _T2_CR_UNKNOWN, 0.0}
257 };
258 */
259
260 /*
261 static float dvbt2_ssi_dbm_nordigp1[][6] =
262 {
263 { -95.7, -94.4, -93.6, -92.6, -92.0, -91.5},
264 { -90.8, -89.1, -87.9, -86.7, -85.8, -85.2},
265 { -86.9, -84.6, -83.2, -81.4, -80.3, -79.7},
266 { -83.5, -80.4, -78.6, -76.0, -74.4, -73.3},
267 };
268
269 // cr, 3/5(1), 2/3(2), 3/4 (3)
270 float fT2_SSI_formula[][12]=
271 {
272 {1.0/5, 97.0, 3.0/2, 82.0, 16.0/5, 50.0, 29.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/5
273 {2.0/3, 95.0, 9.0/5, 77.0, 17.0/5, 43.0, 14.0/5.0, 15.0, 13.0/15, 2.0, 2.0/5, 0.0}, // CR2/3
274 {1.0/2, 93.0, 19.0/10, 74.0, 31.0/10, 43.0, 22.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/4
275 };
276 */
277
278 //static void INTERN_DVBT2_SignalQualityReset(void);
279 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void);
280
281 #if 0
282 static void INTERN_DVBT2_SignalQualityReset(void)
283 {
284 u32FecFirstLockTime=0;
285 fLDPCBerFiltered=-1;
286 }
287 #endif
288
INTERN_DVBT2_DSPReg_Init(const MS_U8 * u8DVBT2_DSPReg,MS_U8 u8Size)289 MS_BOOL INTERN_DVBT2_DSPReg_Init(const MS_U8 *u8DVBT2_DSPReg, MS_U8 u8Size)
290 {
291 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
292 MS_BOOL status = TRUE;
293 MS_U16 u16DspAddr = 0;
294
295 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_DSPReg_Init\n"));
296
297 //for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
298 // status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
299 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_BW, T2_BW_VAL) != TRUE)
300 {
301 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
302 }
303 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_L, T2_FC_L_VAL) != TRUE)
304 {
305 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
306 }
307 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_FC_H, T2_FC_H_VAL) != TRUE)
308 {
309 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
310 }
311 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_SERIAL, T2_TS_SERIAL_VAL) != TRUE)
312 {
313 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
314 }
315 //if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_CLK_RATE, T2_TS_CLK_RATE_VAL) != TRUE)
316 //{
317 // printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
318 //}
319 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_OUT_INV, T2_TS_OUT_INV_VAL) != TRUE)
320 {
321 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
322 }
323 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_TS_DATA_SWAP, T2_TS_DATA_SWAP_VAL) != TRUE)
324 {
325 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
326 }
327 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_IF_AGC_INV_PWM_EN, T2_IF_AGC_INV_PWM_EN_VAL) != TRUE)
328 {
329 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
330 }
331 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_LITE, T2_LITE_VAL) != TRUE)
332 {
333 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
334 }
335
336 if(MDrv_SYS_DMD_VD_MBX_WriteDSPReg((MS_U32)E_DMD_T2_AGC_REF, T2_AGC_REF_VAL) != TRUE) //brown:0x40->agc_ref
337 {
338 printf("INTERN_DVBT2_DSPReg_Init NG\n"); return FALSE;
339 }
340
341 if (u8DVBT2_DSPReg != NULL)
342 {
343 /*temp solution until new dsp table applied.*/
344 // if (INTERN_DVBT2_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
345 if (u8DVBT2_DSPReg[0] >= 1)
346 {
347 u8DVBT2_DSPReg+=2;
348 for (idx = 0; idx<u8Size; idx++)
349 {
350 u16DspAddr = *u8DVBT2_DSPReg;
351 u8DVBT2_DSPReg++;
352 u16DspAddr = (u16DspAddr) + ((*u8DVBT2_DSPReg)<<8);
353 u8DVBT2_DSPReg++;
354 u8Mask = *u8DVBT2_DSPReg;
355 u8DVBT2_DSPReg++;
356 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
357 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT2_DSPReg) & (u8Mask));
358 u8DVBT2_DSPReg++;
359 DBG_INTERN_DVBT2(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
360 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
361 }
362 }
363 else
364 {
365 printf("FATAL: parameter version incorrect\n");
366 }
367 }
368
369 return status;
370 }
371
372 /***********************************************************************************
373 Subject: SoftStop
374 Function: INTERN_DVBT2_SoftStop
375 Parmeter:
376 Return: MS_BOOL
377 Remark:
378 ************************************************************************************/
379
INTERN_DVBT2_SoftStop(void)380 MS_BOOL INTERN_DVBT2_SoftStop ( void )
381 {
382 MS_U16 u8WaitCnt=0;
383 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
384 {
385 printf(">> MB Busy!\n");
386 return FALSE;
387 }
388
389 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
390
391 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
392 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
393
394 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
395 {
396 if (u8WaitCnt++ >= 0xFFF)
397 {
398 printf(">> DVBT2 SoftStop Fail!\n");
399 return FALSE;
400 }
401 }
402
403 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
404 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
405 return TRUE;
406 }
407
INTERN_DVBT2_SoftReset(void)408 MS_BOOL INTERN_DVBT2_SoftReset ( void )
409 {
410 MS_BOOL bRet=TRUE;
411 //MS_U8 u8Data, fdp_fifo_done, djb_fifo_done, tdi_fifo_done;
412 MS_U8 u8Data = 0, fdp_fifo_done = 0, tdi_fifo_done = 0;
413 MS_U8 u8_timeout = 0;
414
415 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_SoftReset\n"));
416
417 //stop FSM_EN
418 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x00); // FSM_EN
419
420 MsOS_DelayTask(5);
421
422 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
423 DBG_INTERN_DVBT2(printf("@@@TOP_RESET:0x%x\n", u8Data));
424 // MIU hold function
425 if((u8Data & 0x20) == 0x00)
426 {
427 // mask miu service with fdp, djb, tdi
428 //fdp 0x17 [12] reg_fdp_fifo_stop=1'b1
429 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
430 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+(0x17*2)+1, (u8Data|0x10));
431 // [8] reg_fdp_load, fdp register dynamic change protection, 1->load register
432 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2FDP_REG_BASE+0xff, 0x10);
433 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x17*2)+1, &u8Data);
434 //printf("@@@@@@ DVBT2 [reg_fdp_fifo_stop]=0x%x\n", u8Data);
435 //djb 0x65 [0] reg_stop_mu_request
436 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
437 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE+(0x65*2), (u8Data|0x01));
438 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2), &u8Data);
439 //printf("@@@@@@ DVBT2 [reg_stop_mu_request]=0x%x\n", u8Data);
440 //snr 0x23 [8] reg_tdi_miu_off
441 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
442 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(T2SNR_REG_BASE+(0x23*2)+1, (u8Data|0x01));
443 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
444 //printf("@@@@@@ DVBT2 [reg_tdi_miu_off]=0x%x\n", u8Data);
445 // ---------------------------------------------
446 // Wait MIU mask or timeout!
447 // DVBT2_TIMER_INT[ 7:0] : indicator of the selected Timer's max count(15:8) (r)
448 // DVBT2_TIMER_INT[11:8] : timer3~timer0 interrupt (r)
449 // ---------------------------------------------
450 //fdp 0x18 [2] reg_fdp_fifo_req_done
451 //djb 0x65 [8] reg_miu_req_terminate_done
452 //tdi 0x23 [9] reg_tdi_miu_off_done
453 do
454 {
455 // Wait MIU mask done or timeout!
456 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+(0x18*2), &u8Data);
457 fdp_fifo_done = u8Data & 0x04;
458 //bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE+(0x65*2)+1, &u8Data);
459 //djb_fifo_done = u8Data & 0x01;
460 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(T2SNR_REG_BASE+(0x23*2)+1, &u8Data);
461 tdi_fifo_done = u8Data & 0x02;
462
463 u8_timeout++;
464 }
465 //while(((fdp_fifo_done != 0x04)||(djb_fifo_done != 0x01)||(tdi_fifo_done != 0x02))
466 while(((fdp_fifo_done != 0x04)||(tdi_fifo_done != 0x02))
467 && u8_timeout != 0x7f);
468
469 //printf(">> DVBT2 fdp_fifo_done=%d, djb_fifo_done=%d, tdi_fifo_done=%d \n", fdp_fifo_done, djb_fifo_done, tdi_fifo_done);
470 printf(">> DVBT2 [fdp_fifo_done]=%d, [tdi_fifo_done]=%d \n", fdp_fifo_done, tdi_fifo_done);
471
472 MsOS_DelayTask(2);
473
474 if(u8_timeout == 0x7f)
475 {
476 printf(">> DVBT2 MIU hold function Fail!\n");
477 //return FALSE;
478 }
479 else
480 {
481 printf(">> DVBT2 MIU hold function done!!\n");
482 }
483 }
484 else
485 printf(">> No need DVBT2 MIU hold function!!\n");
486
487 // demod_top reset
488 bRet = MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0x02, &u8Data);
489 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data|0x20));
490
491 MsOS_DelayTask(1);
492
493 bRet = MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0x02, (u8Data&(~0x20)));
494
495 DBG_INTERN_DVBT2(printf("@INTERN_DVBT2_SoftReset done!!\n"));
496
497 return bRet;
498 }
499
500
501 /***********************************************************************************
502 Subject: Reset
503 Function: INTERN_DVBT2_Reset
504 Parmeter:
505 Return: MS_BOOL
506 Remark:
507 ************************************************************************************/
508 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT2_Reset(void)509 MS_BOOL INTERN_DVBT2_Reset ( void )
510 {
511 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_reset\n"));
512
513 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Reset, t = %ld\n",MsOS_GetSystemTime()));
514
515 INTERN_DVBT2_SoftStop();
516
517
518 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
519 MsOS_DelayTask(5);
520 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
521
522 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
523 MsOS_DelayTask(5);
524
525 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
526 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
527
528 bFECLock = FALSE;
529 bP1Lock = FALSE;
530 u32ChkScanTimeStart = MsOS_GetSystemTime();
531 return TRUE;
532 }
533
534 /***********************************************************************************
535 Subject: Exit
536 Function: INTERN_DVBT2_Exit
537 Parmeter:
538 Return: MS_BOOL
539 Remark:
540 ************************************************************************************/
INTERN_DVBT2_Exit(void)541 MS_BOOL INTERN_DVBT2_Exit ( void )
542 {
543 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_Exit\n"));
544
545
546
547 //diable clk gen
548 //HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
549 //HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
550 /*
551 HAL_DMD_RIU_WriteByte(0x10330a, 0x01); // reg_ckg_atsc_adcd_sync@0x05[3:0] : ADCCLK
552 HAL_DMD_RIU_WriteByte(0x10330b, 0x00);
553
554 HAL_DMD_RIU_WriteByte(0x10330c, 0x01); // reg_ckg_dvbtc_inner1x@0x06[3:0] : MPLLDIV10/4=21.5MHz
555 HAL_DMD_RIU_WriteByte(0x10330d, 0x01); // reg_ckg_dvbtc_inner2x@0x06[11:8]: MPLLDIV10/2=43.2MHz
556
557 HAL_DMD_RIU_WriteByte(0x10330e, 0x01); // reg_ckg_dvbtc_inner4x@0x07[3:0] : MPLLDIV10=86.4MHz
558 HAL_DMD_RIU_WriteByte(0x10330f, 0x00);
559
560 HAL_DMD_RIU_WriteByte(0x103310, 0x01); // reg_ckg_dvbtc_outer1x@0x08[3:0] : MPLLDIV10/2=43.2MHz
561 HAL_DMD_RIU_WriteByte(0x103311, 0x01); // reg_ckg_dvbtc_outer2x@0x08[11:8]: MPLLDIV10=86.4MHz
562
563 HAL_DMD_RIU_WriteByte(0x103312, 0x01); // dvbt_t:0x0000, dvb_c: 0x0004
564 HAL_DMD_RIU_WriteByte(0x103313, 0x00);
565
566 HAL_DMD_RIU_WriteByte(0x103314, 0x01); // reg_ckg_dvbtc_adc@0x0a[3:0] : ADC_CLK
567 HAL_DMD_RIU_WriteByte(0x103315, 0x01); // reg_ckg_dvbtc_innc@0x0a[11:8]
568
569 HAL_DMD_RIU_WriteByte(0x103316, 0x01); // reg_ckg_dvbtc_eq8x@0x0b[3:0] : MPLLDIV3/2=144MHz
570 HAL_DMD_RIU_WriteByte(0x103317, 0x01); // reg_ckg_dvbtc_eq@0x0b[11:8] : MPLLDIV3/16=18MHz
571
572 HAL_DMD_RIU_WriteByte(0x103318, 0x11); // reg_ckg_dvbtc_sram0~3@0x0c[13:0]
573 HAL_DMD_RIU_WriteByte(0x103319, 0x11);
574
575 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
576 HAL_DMD_RIU_WriteByte(0x103309, 0x05); // reg_ckg_dvbtc_ts@0x04
577
578 HAL_DMD_RIU_WriteByte(0x101E3E, 0x00); // DVBT = BIT1 clear
579 */
580 return INTERN_DVBT2_SoftStop();
581 }
582 /*
583 MS_BOOL INTERN_DVBT2_Load2Sdram(MS_U8 *u8_ptr, MS_U16 data_length)
584 {
585
586 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Load2Sdram, len=0x%x, \n",data_length));
587 MS_U8 addrhi, addrlo;
588 int i, j, k, old_i=0;
589 int sdram_start_addr = 0;//1024 >> 2; //StrToInt(ed_sdram_start->Text)>>2; // 4KB alignment
590
591 //I2C_CH_Exit(); // exit CH4
592 //I2C_CH5_Reset(); // switch to CH5
593 //MDrv_DMD_I2C_Channel_Change(5);
594 //--------------------------------------------------------------------------
595 // Set xData map for DRAM
596 //--------------------------------------------------------------------------
597
598 //banknum = 0x1d; //dmdmcu51_xdmiu
599
600 //set xData map upper and low bound for 64k DRAM window
601 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x2020);
602 if(SLAVE_I2CWrite16(banknum,0x63,0x2020)==false)
603 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
604
605 //set xData map offset for 64k DRAM window
606 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x64, 0x0000);
607 if(SLAVE_I2CWrite16(banknum,0x64,0x0000)==false)
608 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
609
610 //set xData map upper and low bound for 4k DRAM window
611 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x65, 0x2420);
612 if(SLAVE_I2CWrite16(banknum,0x65,0x2420)==false)
613 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
614
615 //set xData map offset for 4k DRAM window
616 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, sdram_start_addr);
617 if(SLAVE_I2CWrite16(banknum,0x66,sdram_start_addr)==false)
618 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
619
620 //I2C_CH_Exit(); // exit CH5
621 //EnterDebugMode(1); // switch to CH1
622
623 //enable xData map for DRAM
624 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x63, 0x0007);
625 if(SLAVE_I2CWrite16(banknum,0x62,0x0007)==false)
626 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
627
628
629 for ( i = 0, j = SDRAM_BASE, k = sdram_start_addr + 0x01; i < size;)
630 {
631 if (j == SDRAM_BASE + 0x1000)
632 {
633 //I2C_CH_Exit(); // exit CH1
634 //I2C_CH5_Reset(); // switch to CH5
635 //set xData map offset for 4k DRAM window
636 MDrv_SYS_DMD_VD_MBX_Write2Reg(XDMIU_REG_BASE, 0x66, k++);
637 if(SLAVE_I2CWrite16(banknum,0x66,k++)==false)
638 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
639 j = SDRAM_BASE;
640
641 //I2C_CH_Exit(); // exit CH5
642 //EnterDebugMode(1); // switch to CH1
643
644 }
645
646 addrhi = (j >> 8) & 0xff;
647 addrlo = j & 0xff;
648
649 if (i+EZUSB_Write_Buffer<size)
650 {
651 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,EZUSB_Write_Buffer)==FALSE)
652 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
653
654 j=j+EZUSB_Write_Buffer;
655 i=i+EZUSB_Write_Buffer;
656 }
657 else
658 {
659 if(I2C_WriteBytes(addrhi,addrlo,in_buf+i,size-i)==FALSE)
660 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
661
662 i=size;
663 }
664
665 if ((i-old_i)>=2048)
666 {
667 ShowMCUDL_Progress(0,3*i,size);
668 old_i=i;
669 }
670 }//end for
671
672
673 FWDLRichEdit->Lines->Add(">SDRAM Down Load OK!");
674
675 I2C_CH_Exit(); // exit CH1
676 I2C_CH5_Reset(); // switch to CH5
677
678 //--------------------------------------------------------------------------
679 // Release xData map for SDRAM
680 //--------------------------------------------------------------------------
681
682 if(SLAVE_I2CWrite16(banknum,0x62,0x0000)==false)
683 { MessageBox(NULL,"Fail to write register!!","write register",MB_OK|MB_ICONERROR); return FALSE; }
684
685 }
686 */
687 /***********************************************************************************
688 Subject: Load DSP code to chip
689 Function: INTERN_DVBT2_LoadDSPCode
690 Parmeter:
691 Return: MS_BOOL
692 Remark:
693 ************************************************************************************/
INTERN_DVBT2_LoadDSPCode(void)694 static MS_BOOL INTERN_DVBT2_LoadDSPCode(void)
695 {
696 MS_U8 u8data = 0x00;
697 MS_U16 i;
698 MS_U16 fail_cnt=0;
699 //MS_U16 u16AddressOffset;
700 MS_U32 u32VA_DramCodeAddr;
701
702 #if (DBG_DUMP_LOAD_DSP_TIME==1)
703 MS_U32 u32Time;
704 #endif
705
706
707 #ifndef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
708 BININFO BinInfo;
709 MS_BOOL bResult;
710 MS_U32 u32GEAddr;
711 MS_U8 Data;
712 MS_S8 op;
713 MS_U32 srcaddr;
714 MS_U32 len;
715 MS_U32 SizeBy4K;
716 MS_U16 u16Counter=0;
717 MS_U8 *pU8Data;
718 #endif
719
720 #if 0
721 if(HAL_DMD_RIU_ReadByte(0x101E3E))
722 {
723 printf("Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
724 return FALSE;
725 }
726 #endif
727
728 // MDrv_Sys_DisableWatchDog();
729
730
731 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
732 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
733 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
734 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
735 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
736 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
737
738 //// Load code thru VDMCU_IF ////
739 DBG_INTERN_DVBT2(printf(">Load Code...\n"));
740 //#ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
741 //for ( i = 0; i < sizeof(INTERN_DVBT2_table); i++)
742 //{
743 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
744 //}
745 if (sizeof(INTERN_DVBT2_table) < 0x8000)
746 {
747 printf("----->Bin file Size is not match...\n");
748 }
749 else
750 {
751 // load half code to SRAM
752 for ( i = 0; i < 0x8000; i++)
753 {
754 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT2_table[i]); // write data to VD MCU 51 code sram
755 }
756 DBG_INTERN_DVBT2(printf(">Load SRAM code done...\n"));
757
758
759 if((u32DMD_DVBT2_FW_START_ADDR & 0x8000) != 0x8000)
760 {
761 printf(">DVB-T2 DRAM Start address is not correct!!\n");
762 }
763 else
764 {
765 // load another half code to SDRAM
766 // VA = MsOS_PA2KSEG1(PA); //NonCache
767 DBG_INTERN_DVBT2(printf(">>> DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
768 u32VA_DramCodeAddr = MsOS_PA2KSEG1(u32DMD_DVBT2_FW_START_ADDR);
769 memcpy((void*)(MS_VIRT)u32VA_DramCodeAddr, &INTERN_DVBT2_table[0x8000], sizeof(INTERN_DVBT2_table) - 0x8000);
770
771 DBG_INTERN_DVBT2(printf(">Load DRAM code done...\n"));
772 }
773 }
774
775 //#endif
776
777 //// Content verification ////
778 DBG_INTERN_DVBT2(printf(">Verify Code...\n"));
779
780 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
781 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
782
783 #ifdef INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY
784 for ( i = 0; i < 0x8000; i++)
785 {
786 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
787 if (u8data != INTERN_DVBT2_table[i])
788 {
789 printf(">fail add = 0x%x\n", i);
790 printf(">code = 0x%x\n", INTERN_DVBT2_table[i]);
791 printf(">data = 0x%x\n", u8data);
792
793 if (fail_cnt++ > 10)
794 {
795 printf(">DVB-T2 DSP SRAM Loadcode fail!\n");
796 return false;
797 }
798 }
799 }
800 #else
801 for (i=0;i<=SizeBy4K;i++)
802 {
803 if(i==SizeBy4K)
804 len=BinInfo.B_Len%0x1000;
805 else
806 len=0x1000;
807
808 srcaddr = u32GEAddr+(0x1000*i);
809 //printf("\t i = %08LX\n", i);
810 //printf("\t len = %08LX\n", len);
811 op = 1;
812 u16Counter = 0 ;
813 //printf("\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
814 while(len--)
815 {
816 u16Counter ++ ;
817 //printf("file: %s, line: %d\n", __FILE__, __LINE__);
818 //pU8Data = (U8 *)(srcaddr|0x80000000);
819 #if OBA2
820 pU8Data = (U8 *)(srcaddr);
821 #else
822 pU8Data = (U8 *)(srcaddr|0x80000000);
823 #endif
824 Data = *pU8Data;
825
826 #if 0
827 if(u16Counter < 0x100)
828 printf("0x%bx,", Data);
829 #endif
830 u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
831 if (u8data != Data)
832 {
833 printf(">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
834 printf(">code = 0x%x\n", Data);
835 printf(">data = 0x%x\n", u8data);
836
837 if (fail_cnt++ > 10)
838 {
839 printf(">DVB-T DSP Loadcode fail!");
840 return false;
841 }
842 }
843
844 srcaddr += op;
845 }
846 // printf("\n\n\n");
847 }
848 #endif
849
850 // add T2 DRAM bufer start address into fixed location
851 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
852 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
853
854 // write Start address to VD MCU 51 code sram
855 // //0x30~0x33
856 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR);
857 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 8));
858 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 16));
859 // HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DRAM_START_ADDR >> 24));
860 //0x30~0x33
861 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_EQ_START_ADDR);
862 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 8));
863 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 16));
864 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_EQ_START_ADDR >> 24));
865 //0x34~0x37
866 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_TDI_START_ADDR);
867 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 8));
868 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 16));
869 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_TDI_START_ADDR >> 24));
870 //0x38~0x3b
871 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_DJB_START_ADDR);
872 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 8));
873 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 16));
874 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_DJB_START_ADDR >> 24));
875 //0x3c~0x3f
876 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBT2_FW_START_ADDR);
877 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 8));
878 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 16));
879 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBT2_FW_START_ADDR >> 24));
880
881 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR));
882 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR));
883 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR));
884 DBG_INTERN_DVBT2(printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR));
885
886 #if 0
887 // DEBUG
888 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte
889 // HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
890
891 // for ( i = 0; i < 16; i++)
892 // {
893 // u8data = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
894 // printf(">add = 0x%x\t", i);
895 // printf(">data = 0x%x\n", u8data);
896 // }
897
898 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_EQ_START_ADDR=0x%lx \n", u32DMD_DVBT2_EQ_START_ADDR);
899 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_TDI_START_ADDR=0x%lx \n", u32DMD_DVBT2_TDI_START_ADDR);
900 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_DJB_START_ADDR=0x%lx \n", u32DMD_DVBT2_DJB_START_ADDR);
901 printf(">>> [INTERN_DVBT2_LoadDSPCode]DVBT2_FW_START_ADDR=0x%lx \n", u32DMD_DVBT2_FW_START_ADDR);
902 #endif
903
904 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
905 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
906 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
907 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
908
909 DBG_INTERN_DVBT2(printf(">DSP Loadcode done."));
910 //while(load_data_variable);
911
912 return TRUE;
913 }
914
915 /***********************************************************************************
916 Subject: DVB-T CLKGEN initialized function
917 Function: INTERN_DVBT2_Power_On_Initialization
918 Parmeter:
919 Return: MS_BOOL
920 Remark:
921 ************************************************************************************/
INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)922 void INTERN_DVBT2_InitClkgen(MS_BOOL bRFAGCTristateEnable)
923 {
924 MS_U8 temp_val;
925 MS_U16 u16_temp_val;
926
927 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_InitClkgen\n"));
928
929 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
930 //HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
931 // ----------------------------------------------
932 // start demod CLKGEN setting
933 // ----------------------------------------------
934 // *** Set register at CLKGEN1
935 // enable DMD MCU clock "bit[0] set 0"
936 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
937 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
938 // CLK_DMDMCU clock setting
939 // [0] disable clock
940 // [1] invert clock
941 // [4:2]
942 // 000:170 MHz(MPLL_DIV_BUf)
943 // 001:160MHz
944 // 010:144MHz
945 // 011:123MHz
946 // 100:108MHz
947 // 101:mem_clcok
948 // 110:mem_clock div 2
949 // 111:select XTAL
950 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
951 // HAL_DMD_RIU_WriteByte(0x10331e,0x1c); // 24MHz
952 HAL_DMD_RIU_WriteByte(0x10331e,0x10); // 108MHz
953
954 // set parallet ts clock
955 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
956 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
957 //HAL_DMD_RIU_WriteByte(0x103301,0x07);//0615
958 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
959 temp_val|=0x05;
960 // temp_val|=0x07;
961 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
962
963 HAL_DMD_RIU_WriteByte(0x103300,0x10);
964
965 // enable DVBTC ts clock
966 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
967 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
968 HAL_DMD_RIU_WriteByte(0x103309,0x00);
969 HAL_DMD_RIU_WriteByte(0x103308,0x00);
970
971 // enable dvbc adc clock
972 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
973 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
974 HAL_DMD_RIU_WriteByte(0x103315,0x00);
975 HAL_DMD_RIU_WriteByte(0x103314,0x00);
976
977 // ----------------------------------------------
978 // start demod_0 CLKGEN setting
979 // ----------------------------------------------
980
981 // enable clk_atsc_adcd_sync
982 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
983 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
984 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
985 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
986
987 //reg_ckg_dvbt_inner
988 HAL_DMD_RIU_WriteByte(0x111f21,0x11);
989 HAL_DMD_RIU_WriteByte(0x111f20,0x10);
990
991 //reg_ckg_dvbt_outer
992 HAL_DMD_RIU_WriteByte(0x111f23,0x01);
993 HAL_DMD_RIU_WriteByte(0x111f22,0x11);
994
995 //reg_ckg_acifir
996 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
997
998 //reg_ckg_dvbtm_sram_t1o2x_t22x
999 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
1000 HAL_DMD_RIU_WriteByte(0x111f28,0x00);
1001
1002 //reg_ckg_dvbtm_sram_adc_t22x
1003 HAL_DMD_RIU_WriteByte(0x111f2d,0x00);
1004 HAL_DMD_RIU_WriteByte(0x111f2c,0x01);
1005
1006 //reg_ckg_dvbtm_sram_t12x_t24x
1007 HAL_DMD_RIU_WriteByte(0x111f2f,0x00);
1008 HAL_DMD_RIU_WriteByte(0x111f2e,0x00);
1009
1010 //reg_ckg_dvbtm_ts_in
1011 HAL_DMD_RIU_WriteByte(0x111f31,0x04);
1012 HAL_DMD_RIU_WriteByte(0x111f30,0x00);
1013
1014 HAL_DMD_RIU_WriteByte(0x111f33,0x3c);
1015 HAL_DMD_RIU_WriteByte(0x111f32,0x00);
1016
1017 HAL_DMD_RIU_WriteByte(0x111f35,0x00);
1018 HAL_DMD_RIU_WriteByte(0x111f34,0x00);
1019
1020 HAL_DMD_RIU_WriteByte(0x111f37,0x00);
1021 HAL_DMD_RIU_WriteByte(0x111f36,0x00);
1022
1023 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
1024 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
1025
1026 HAL_DMD_RIU_WriteByte(0x111f3d,0x00);
1027 HAL_DMD_RIU_WriteByte(0x111f3c,0x00);
1028
1029 HAL_DMD_RIU_WriteByte(0x111f43,0x00);
1030 HAL_DMD_RIU_WriteByte(0x111f42,0x00);
1031
1032 HAL_DMD_RIU_WriteByte(0x111f45,0x00);
1033 HAL_DMD_RIU_WriteByte(0x111f44,0x00);
1034
1035 HAL_DMD_RIU_WriteByte(0x111fe1,0x00);
1036 HAL_DMD_RIU_WriteByte(0x111fe0,0x00);
1037
1038 HAL_DMD_RIU_WriteByte(0x111fe3,0x00);
1039 HAL_DMD_RIU_WriteByte(0x111fe2,0x00);
1040
1041 HAL_DMD_RIU_WriteByte(0x111fe5,0x00);
1042 HAL_DMD_RIU_WriteByte(0x111fe4,0x00);
1043
1044 HAL_DMD_RIU_WriteByte(0x111fe7,0x00);
1045 HAL_DMD_RIU_WriteByte(0x111fe6,0x00);
1046
1047 HAL_DMD_RIU_WriteByte(0x111fe9,0x00);
1048 HAL_DMD_RIU_WriteByte(0x111fe8,0x00);
1049
1050 HAL_DMD_RIU_WriteByte(0x111feb,0xc8);
1051 HAL_DMD_RIU_WriteByte(0x111fea,0x00);
1052
1053 HAL_DMD_RIU_WriteByte(0x111fed,0x00);
1054 HAL_DMD_RIU_WriteByte(0x111fec,0x0c);
1055
1056 HAL_DMD_RIU_WriteByte(0x111fef,0x00);
1057 HAL_DMD_RIU_WriteByte(0x111fee,0x00);
1058
1059 // Maserati special
1060 HAL_DMD_RIU_WriteByte(0x152971,0x10);
1061 HAL_DMD_RIU_WriteByte(0x152970,0x01);
1062
1063 HAL_DMD_RIU_WriteByte(0x111ff0,0x00);
1064
1065 // Mulan special
1066 // TEQ CLK for DVBT2
1067 // HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1068
1069 // SRAM share
1070 HAL_DMD_RIU_WriteByte(0x111f75,0x00);
1071 HAL_DMD_RIU_WriteByte(0x111f74,0x00);
1072
1073 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
1074 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
1075
1076 HAL_DMD_RIU_WriteByte(0x111f79,0x00);
1077 HAL_DMD_RIU_WriteByte(0x111f78,0x00);
1078
1079 HAL_DMD_RIU_WriteByte(0x111f7b,0x00);
1080 HAL_DMD_RIU_WriteByte(0x111f7a,0x00);
1081
1082 HAL_DMD_RIU_WriteByte(0x111f7d,0x00);
1083 HAL_DMD_RIU_WriteByte(0x111f7c,0x00);
1084
1085 HAL_DMD_RIU_WriteByte(0x111f7f,0x00);
1086 HAL_DMD_RIU_WriteByte(0x111f7e,0x00);
1087
1088 // 32+4K xdata sram
1089 HAL_DMD_RIU_WriteByte(0x1117e0,0x23);
1090 HAL_DMD_RIU_WriteByte(0x1117e1,0x21);
1091 HAL_DMD_RIU_WriteByte(0x1117e4,0x01);
1092 HAL_DMD_RIU_WriteByte(0x1117e6,0x11);
1093
1094 // SRAM allocation
1095 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1096 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1097
1098 HAL_DMD_RIU_WriteByte(0x111705,0x00);
1099 HAL_DMD_RIU_WriteByte(0x111704,0x00);
1100
1101 HAL_DMD_RIU_WriteByte(0x111703,0x00);
1102 HAL_DMD_RIU_WriteByte(0x111702,0x00);
1103
1104 HAL_DMD_RIU_WriteByte(0x111707,0x7f);
1105 HAL_DMD_RIU_WriteByte(0x111706,0xff);
1106
1107 // SDRAM address offset
1108 u16_temp_val = (MS_U16)(u32DMD_DVBT2_FW_START_ADDR>>16);
1109 HAL_DMD_RIU_WriteByte(0x11171b,(MS_U8)(u16_temp_val>>8));
1110 HAL_DMD_RIU_WriteByte(0x11171a,(MS_U8)u16_temp_val);
1111
1112 // DRAM allocation
1113 HAL_DMD_RIU_WriteByte(0x111709,0x00);
1114 HAL_DMD_RIU_WriteByte(0x111708,0x00);
1115
1116 HAL_DMD_RIU_WriteByte(0x11170d,0x80);
1117 HAL_DMD_RIU_WriteByte(0x11170c,0x00);
1118
1119 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
1120 HAL_DMD_RIU_WriteByte(0x11170a,0x00);
1121
1122 HAL_DMD_RIU_WriteByte(0x11170f,0xff);
1123 HAL_DMD_RIU_WriteByte(0x11170e,0xff);
1124
1125 // DRAM EN
1126 HAL_DMD_RIU_WriteByte(0x111718,0x04);
1127
1128 // [0]switch dram address mode:
1129 // 0: address from dmdmcu51 bank (old mode)
1130 // 1: address from dmdmcu51_top bank (new mode)
1131 HAL_DMD_RIU_WriteByte(0x11171c,0x01);
1132
1133 // ----------------------------------------------
1134 // start demod CLKGEN setting
1135 // ----------------------------------------------
1136 // select DMD MCU
1137 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1138 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0300);
1139 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1140
1141 // stream2miu_en, activate rst_wadr
1142 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0012);
1143 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1144 // stream2miu_en, turn off rst_wadr
1145 // `RIU_W((`RIUBASE_TSP0 >>1) + `REG16_HW_CONFIG8, 2'b11, 16'h0102);
1146
1147 }
1148
1149 /***********************************************************************************
1150 Subject: Power on initialized function
1151 Function: INTERN_DVBT2_Power_On_Initialization
1152 Parmeter:
1153 Return: MS_BOOL
1154 Remark:
1155 ************************************************************************************/
1156
INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT2_DSPRegInitExt,MS_U8 u8DMD_DVBT2_DSPRegInitSize)1157 MS_BOOL INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT2_DSPRegInitExt, MS_U8 u8DMD_DVBT2_DSPRegInitSize)
1158 {
1159 MS_U16 status = true;
1160
1161 // MS_U8 temp_val;
1162 //MS_U8 cData = 0;
1163 //U8 cal_done;
1164 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_Power_On_Initialization\n"));
1165
1166 #if defined(PWS_ENABLE)
1167 Mapi_PWS_Stop_VDMCU();
1168 #endif
1169 // No definition for Mulan
1170 #if 0
1171 // Global demod reset. To fix DVBS -> DVBT2 or DVBS blind scan -> DVBT2 unlock issue.
1172 temp_val=HAL_DMD_RIU_ReadByte(0x101e3a);
1173 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val|0x02);
1174
1175 MsOS_DelayTask(1);
1176
1177 HAL_DMD_RIU_WriteByte(0x101e3a,temp_val&(~0x02));
1178 #endif
1179
1180 INTERN_DVBT2_InitClkgen(bRFAGCTristateEnable);
1181 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1182 //// Firmware download //////////
1183 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Load DSP...\n"));
1184 //MsOS_DelayTask(100);
1185
1186 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1187 {
1188 if (INTERN_DVBT2_LoadDSPCode() == FALSE)
1189 {
1190 printf("DVB-T2 Load DSP Code Fail\n");
1191 return FALSE;
1192 }
1193 else
1194 {
1195 DBG_INTERN_DVBT2(printf("DVB-T2 Load DSP Code OK\n"));
1196 }
1197 }
1198
1199
1200 //// MCU Reset //////////
1201 DBG_INTERN_DVBT2(printf("INTERN_DVBT2 Reset...\n"));
1202 if (INTERN_DVBT2_Reset() == FALSE)
1203 {
1204 DBG_INTERN_DVBT2(printf("Fail\n"));
1205 return FALSE;
1206 }
1207 else
1208 {
1209 DBG_INTERN_DVBT2(printf("OK\n"));
1210 }
1211
1212 // SRAM setting, DVB-T use it.
1213 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1214 //MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1215 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1216
1217 status &= INTERN_DVBT2_DSPReg_Init(u8DMD_DVBT2_DSPRegInitExt, u8DMD_DVBT2_DSPRegInitSize);
1218 return status;
1219 }
1220
1221 /************************************************************************************************
1222 Subject: Driving control
1223 Function: INTERN_DVBT2_Driving_Control
1224 Parmeter: bInversionEnable : TRUE For High
1225 Return: void
1226 Remark:
1227 *************************************************************************************************/
INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)1228 void INTERN_DVBT2_Driving_Control(MS_BOOL bEnable)
1229 {
1230 MS_U8 u8Temp;
1231
1232 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1233
1234 if (bEnable)
1235 {
1236 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1237 }
1238 else
1239 {
1240 u8Temp = u8Temp & (~0x01);
1241 }
1242
1243 DBG_INTERN_DVBT2(printf("---> INTERN_DVBT2_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1244 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1245 }
1246 /************************************************************************************************
1247 Subject: Clk Inversion control
1248 Function: INTERN_DVBT2_Clk_Inversion_Control
1249 Parmeter: bInversionEnable : TRUE For Inversion Action
1250 Return: void
1251 Remark:
1252 *************************************************************************************************/
INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)1253 void INTERN_DVBT2_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1254 {
1255 MS_U8 u8Temp;
1256
1257 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1258
1259 if (bInversionEnable)
1260 {
1261 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1262 }
1263 else
1264 {
1265 u8Temp = u8Temp & (~0x02);
1266 }
1267
1268 DBG_INTERN_DVBT2(printf("---> Inversion(Bit9) = 0x%x \n",u8Temp));
1269 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1270 }
1271 /************************************************************************************************
1272 Subject: Transport stream serial/parallel control
1273 Function: INTERN_DVBT2_Serial_Control
1274 Parmeter: bEnable : TRUE For serial
1275 Return: MS_BOOL :
1276 Remark:
1277 *************************************************************************************************/
INTERN_DVBT2_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1278 MS_BOOL INTERN_DVBT2_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1279 {
1280 MS_U8 status = true;
1281 MS_U8 temp_val;
1282 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_ts... u8TSClk=%d\n",u8TSClk));
1283
1284 if (u8TSClk == 0xFF) u8TSClk=0x13;
1285 if (bEnable) //Serial mode for TS pad
1286 {
1287 // serial
1288 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1289 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1290
1291 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1292 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1293 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1294
1295 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1296 temp_val|=0x04;
1297 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1298 #else
1299 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1300 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1301 temp_val|=0x07;
1302 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1303 #endif
1304 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1305 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1306 }
1307 else
1308 {
1309 //parallel
1310 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1311 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1312
1313 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1314 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1315 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1316 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1317 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1318 temp_val|=0x05;
1319 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1320 #else
1321 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1322 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1323 temp_val|=0x07;
1324 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1325 #endif
1326
1327 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1328 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1329 }
1330
1331 //DBG_INTERN_DVBT2(printf("---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1332
1333 INTERN_DVBT2_Driving_Control(INTERN_DVBT2_DTV_DRIVING_LEVEL);
1334 return status;
1335 }
1336
1337 /************************************************************************************************
1338 Subject: TS1 output control
1339 Function: INTERN_DVBT2_PAD_TS1_Enable
1340 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1341 Return: void
1342 Remark:
1343 *************************************************************************************************/
INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)1344 void INTERN_DVBT2_PAD_TS1_Enable(MS_BOOL flag)
1345 {
1346 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_TS1_Enable... \n"));
1347
1348 if(flag) // PAD_TS1 Enable TS CLK PAD
1349 {
1350 //printf("=== TS1_Enable ===\n");
1351 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1352 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1353 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1354 }
1355 else // PAD_TS1 Disable TS CLK PAD
1356 {
1357 //printf("=== TS1_Disable ===\n");
1358 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1359 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1360 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1361 }
1362 }
1363
1364 /************************************************************************************************
1365 Subject: channel change config
1366 Function: INTERN_DVBT2_Config
1367 Parmeter: BW: bandwidth
1368 Return: MS_BOOL :
1369 Remark:
1370 *************************************************************************************************/
INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U8 u8PlpID)1371 MS_BOOL INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U8 u8PlpID)
1372 {
1373 MS_U8 bandwidth;
1374 MS_U8 status = true;
1375 //MS_U8 temp_val;
1376 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_config %d %d %d %ld %d\n", BW, bSerialTS, u8TSClk, u32IFFreq, u8PlpID));
1377 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_Config, t = %ld\n",MsOS_GetSystemTime()));
1378
1379 if (u8TSClk == 0xFF) u8TSClk=0x13;
1380 switch(BW)
1381 {
1382 case E_DMD_T2_RF_BAND_5MHz:
1383 bandwidth = 1;
1384 break;
1385 case E_DMD_T2_RF_BAND_6MHz:
1386 bandwidth = 2;
1387 break;
1388 case E_DMD_T2_RF_BAND_7MHz:
1389 bandwidth = 3;
1390 break;
1391 case E_DMD_T2_RF_BAND_10MHz:
1392 bandwidth = 5;
1393 break;
1394 case E_DMD_T2_RF_BAND_1p7MHz:
1395 bandwidth = 0;
1396 break;
1397 case E_DMD_T2_RF_BAND_8MHz:
1398 default:
1399 bandwidth = 4;
1400 break;
1401 }
1402
1403 status &= INTERN_DVBT2_Reset();
1404
1405 // BW mode
1406 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_BW, BW);
1407 // TS mode
1408 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_T2_TS_SERIAL, bSerialTS? 0x01:0x00);
1409 // FC
1410 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_L, u32IFFreq&0xff);
1411 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_FC_H, (u32IFFreq>>8)&0xff);
1412 // PLP_ID
1413 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
1414
1415 /*
1416 if(bSerialTS)
1417 {
1418 // serial
1419 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1420 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1421
1422 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
1423 #if(INTERN_DVBT2_TS_SERIAL_INVERSION == 0)
1424 // HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1425 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1426 temp_val|=0x04;
1427 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1428 #else
1429 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1430 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1431 temp_val|=0x07;
1432 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1433 #endif
1434 }
1435 else
1436 {
1437 //parallel
1438 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
1439 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1440
1441 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1442 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1443 #if(INTERN_DVBT2_TS_PARALLEL_INVERSION == 0)
1444 // HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1445 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1446 temp_val|=0x05;
1447 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1448 #else
1449 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1450 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1451 temp_val|=0x07;
1452 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1453 #endif
1454 }
1455 */
1456 return status;
1457 }
1458 /************************************************************************************************
1459 Subject: enable hw to lock channel
1460 Function: INTERN_DVBT2_Active
1461 Parmeter: bEnable
1462 Return: MS_BOOL
1463 Remark:
1464 *************************************************************************************************/
INTERN_DVBT2_Active(MS_BOOL bEnable)1465 MS_BOOL INTERN_DVBT2_Active(MS_BOOL bEnable)
1466 {
1467 MS_U8 status = true;
1468
1469 DBG_INTERN_DVBT2(printf(" @INTERN_DVBT2_active\n"));
1470
1471 //// INTERN_DVBT2 Finite State Machine on/off //////////
1472 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1473
1474 // INTERN_DVBT2_SignalQualityReset();
1475 return status;
1476 }
1477 /************************************************************************************************
1478 Subject: Return lock status
1479 Function: INTERN_DVBT2_Lock
1480 Parmeter: eStatus :
1481 Return: MS_BOOL
1482 Remark:
1483 *************************************************************************************************/
INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout,MS_U16 u16DMD_DVBT2_FEC_Timeout)1484 DMD_T2_LOCK_STATUS INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout, MS_U16 u16DMD_DVBT2_FEC_Timeout)
1485 {
1486 // float fBER=0.0f;
1487
1488 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK))
1489 {
1490 #if 0
1491 // copy from msb1240 >>>>>
1492 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1493 {
1494 if ((fBerFilteredDVBT2 <= 0.0) || ((fBerFilteredDVBT2/fBER) > 30.0 || (fBerFilteredDVBT2/fBER) < 0.03))
1495 fBerFilteredDVBT2 = fBER;
1496 else
1497 fBerFilteredDVBT2 = 0.9f*fBerFilteredDVBT2+0.1f*fBER;
1498 }
1499 // <<<<< copy from msb1240
1500 #endif
1501
1502 if (bFECLock == FALSE)
1503 {
1504 u32FecFirstLockTime = MsOS_GetSystemTime();
1505 DBG_INTERN_DVBT2(printf("++++++++[utopia]dvbt2 lock\n"));
1506 }
1507 #if 0
1508 if(INTERN_DVBT2_GetPostLdpcBer(&fBER) == TRUE)
1509 {
1510 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1511 {
1512 if(fLDPCBerFiltered <= 0.0)
1513 fLDPCBerFiltered = fBER;
1514 else
1515 fLDPCBerFiltered = 0.9f*fLDPCBerFiltered+0.1f*fBER;
1516 }
1517 DBG_INTERN_DVBT2(printf("[dvbt2]f_ber=%8.3e, g_ldpc_ber=%8.3e\n",fBER,fLDPCBerFiltered));
1518 }
1519 #endif
1520 u32FecLastLockTime = MsOS_GetSystemTime();
1521 bFECLock = TRUE;
1522 return E_DMD_T2_LOCK;
1523 }
1524 else
1525 {
1526 #if 0
1527 INTERN_DVBT2_SignalQualityReset();
1528 #endif
1529 if (bFECLock == TRUE)
1530 {
1531 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1532 {
1533 return E_DMD_T2_LOCK;
1534 }
1535 }
1536 bFECLock = FALSE;
1537 }
1538 /*
1539 #ifdef CHIP_KRITI
1540 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_NO_CHANNEL))
1541 {
1542 // DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- E_DMD_DVBT2_NO_CHANNEL \n"););
1543 return E_DMD_T2_UNLOCK;
1544 }
1545 #endif
1546 */
1547 if(!bP1Lock)
1548 {
1549 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_EVER_LOCK))
1550 {
1551 DBG_INTERN_DVBT2(printf("==> INTERN_DVBT2_Lock -- P1Lock \n"));
1552 bP1Lock = TRUE;
1553 }
1554 }
1555 if(bP1Lock)
1556 {
1557 DBG_INTERN_DVBT2(printf("P1Lock %ld\n",MsOS_GetSystemTime()));
1558 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_FEC_Timeout)
1559 {
1560 return E_DMD_T2_CHECKING;
1561 }
1562 }
1563 else
1564 {
1565 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT2_P1_Timeout)
1566 {
1567 return E_DMD_T2_CHECKING;
1568 }
1569 }
1570 return E_DMD_T2_UNLOCK;
1571
1572 }
1573
1574
INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)1575 MS_BOOL INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus)
1576 {
1577 MS_U16 u16Address = 0;
1578 MS_U8 cData = 0;
1579 MS_U8 cBitMask = 0;
1580 MS_U8 use_dsp_reg = 0;
1581
1582 switch( eStatus )
1583 {
1584 case E_DMD_DVBT2_FEC_LOCK:
1585 use_dsp_reg = 1;
1586 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //FEC lock,
1587 cBitMask = BIT(7);
1588 break;
1589
1590 case E_DMD_DVBT2_P1_LOCK:
1591 u16Address = 0x3082; //P1 HW Lock,
1592 cBitMask = BIT(3);
1593 break;
1594
1595 case E_DMD_DVBT2_DCR_LOCK:
1596 use_dsp_reg = 1;
1597 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //DCR Lock,
1598 cBitMask = BIT(2);
1599 break;
1600
1601 case E_DMD_DVBT2_AGC_LOCK:
1602 use_dsp_reg = 1;
1603 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //AGC Lock,
1604 cBitMask = BIT(0);
1605 break;
1606
1607 case E_DMD_DVBT2_MODE_DET:
1608 u16Address = 0x3082; //Mode CP Detect,
1609 cBitMask = BIT(1);
1610 break;
1611
1612 case E_DMD_DVBT2_P1_EVER_LOCK:
1613 use_dsp_reg = 1;
1614 u16Address = E_DMD_T2_DVBT2_LOCK_HIS; //P1 Ever Lock,
1615 cBitMask = BIT(5);
1616 break;
1617
1618 case E_DMD_DVBT2_L1_CRC_LOCK:
1619 u16Address = 0x2B41; //P1 Ever Lock,
1620 cBitMask = BIT(5)|BIT(6)|BIT(7);
1621 break;
1622
1623 case E_DMD_DVBT2_NO_CHANNEL:
1624 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1625 cBitMask = BIT(7);
1626 break;
1627
1628
1629 default:
1630 return FALSE;
1631 }
1632
1633 if (use_dsp_reg == 1)
1634 {
1635 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16Address, &cData) == FALSE)
1636 {
1637 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
1638 return FALSE;
1639 }
1640 }
1641 else
1642 {
1643 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1644 {
1645 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadReg fail \n"));
1646 return FALSE;
1647 }
1648 }
1649
1650 #ifdef MS_DEBUG
1651 MS_U8 u8tmp;
1652 MDrv_SYS_DMD_VD_MBX_ReadReg(0x20c4, &u8tmp);
1653 DBG_INTERN_DVBT2(printf(">>>>>>>>>> DVBT2 State=%d \n", u8tmp));
1654 #endif
1655
1656 if ((cData & cBitMask) == cBitMask)
1657 {
1658 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is lock \n", eStatus));
1659 return TRUE;
1660 }
1661 else
1662 {
1663 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock eStatus=%d is unlock \n", eStatus));
1664 return FALSE;
1665 }
1666
1667 }
1668
1669 /****************************************************************************
1670 Subject: To get the Post LDPC BER
1671 Function: INTERN_DVBT2_GetPostLdpcBer
1672 Parmeter: Quility
1673 Return: E_RESULT_SUCCESS
1674 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1675 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1676 We will not read the Period, and have the "/256/8"
1677 **************************************************************************/
INTERN_DVBT2_GetPostLdpcBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg,MS_U16 * FecType)1678 MS_BOOL INTERN_DVBT2_GetPostLdpcBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg, MS_U16 *FecType)
1679 {
1680 MS_BOOL status = true;
1681 MS_U8 reg=0;
1682 // MS_U16 BitErrPeriod;
1683 // MS_U32 BitErr;
1684 // MS_U16 FecType = 0;
1685
1686 /////////// Post-Viterbi BER /////////////
1687 /////////// Data BER /////////////
1688 // bank 0x33 0x02 [0] freeze
1689 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1690
1691 // bank 0x33 0x12 Data BER Window[15:0]
1692 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1693 *BitErrPeriod_reg = reg;
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1695 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg;
1696
1697 // bank 0x33 0x34 Data BER count[15:0]
1698 // bank 0x33 0x35 Data BER count[31:16]
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, ®);
1700 *BitErr_reg = reg;
1701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, ®);
1702 *BitErr_reg = (*BitErr_reg << 8) | reg;
1703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, ®);
1704 *BitErr_reg = (*BitErr_reg << 8) | reg;
1705 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, ®);
1706 *BitErr_reg = (*BitErr_reg << 8) | reg;
1707
1708 // bank 0x33 0x02 [0] freeze
1709 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1710
1711 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1712 *FecType = reg;
1713 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1714 *FecType = (*FecType << 8) | reg;
1715
1716 return status;
1717 }
1718
1719 #if 0
1720 MS_BOOL INTERN_DVBT2_GetPostLdpcBer(float *ber)
1721 {
1722 MS_BOOL status = true;
1723 MS_U8 reg=0;
1724 MS_U16 BitErrPeriod;
1725 MS_U32 BitErr;
1726 MS_U16 FecType = 0;
1727
1728 /////////// Post-Viterbi BER /////////////
1729
1730 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1731 {
1732 *ber = (float)-1.0;
1733 return false;
1734 }
1735
1736 /////////// Data BER /////////////
1737 // bank 0x33 0x02 [0] freeze
1738 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1739
1740 // bank 0x33 0x12 Data BER Window[15:0]
1741 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1742 BitErrPeriod = reg;
1743 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1744 BitErrPeriod = (BitErrPeriod << 8) | reg;
1745
1746 // bank 0x33 0x34 Data BER count[15:0]
1747 // bank 0x33 0x35 Data BER count[31:16]
1748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 3, ®);
1749 BitErr = reg;
1750 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 2, ®);
1751 BitErr = (BitErr << 8) | reg;
1752 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 1, ®);
1753 BitErr = (BitErr << 8) | reg;
1754 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x34 << 1) + 0, ®);
1755 BitErr = (BitErr << 8) | reg;
1756
1757 // bank 0x33 0x02 [0] freeze
1758 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1759
1760 if (BitErrPeriod == 0)
1761 //protect 0
1762 BitErrPeriod = 1;
1763
1764 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1765 FecType = reg;
1766 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1767 FecType = (FecType << 8) | reg;
1768
1769 if (FecType & 0x0180)
1770 {
1771 if (BitErr == 0)
1772 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1773 else
1774 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1775 }
1776 else
1777 {
1778 if (BitErr == 0)
1779 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1780 else
1781 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1782 }
1783
1784 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PostLDPCBER = %8.3e \n ", *ber));
1785
1786 if (status == FALSE)
1787 {
1788 printf("INTERN_DVBT2_GetPostLdpcBer Fail!\n");
1789 return FALSE;
1790 }
1791
1792 return status;
1793 }
1794 #endif
1795
1796 /****************************************************************************
1797 Subject: To get the Pre LDPC BER
1798 Function: INTERN_DVBT2_GetPreLdpcBer
1799 Parmeter: ber
1800 Return: E_RESULT_SUCCESS
1801 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1802 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1803 We will not read the Period, and have the "/256/8"
1804 *****************************************************************************/
INTERN_DVBT2_GetPreLdpcBer(MS_U32 * BitErr_reg,MS_U16 * BitErrPeriod_reg,MS_U16 * FecType)1805 MS_BOOL INTERN_DVBT2_GetPreLdpcBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg, MS_U16 *FecType)
1806 {
1807 MS_U8 status = true;
1808 MS_U8 reg=0;
1809 // MS_U16 BitErrPeriod;
1810 // MS_U32 BitErr;
1811 // MS_U16 FecType = 0;
1812
1813 /////////// Data BER /////////////
1814 // bank 0x33 0x02 [0] freeze
1815 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1816
1817 // bank 0x33 0x12 Data BER Window[15:0]
1818 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1819 *BitErrPeriod_reg = reg;
1820 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1821 *BitErrPeriod_reg = (*BitErrPeriod_reg << 8) | reg;
1822
1823 // bank 0x33 0x34 Data BER count[15:0]
1824 // bank 0x33 0x35 Data BER count[31:16]
1825 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 3, ®);
1826 *BitErr_reg = reg;
1827 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 2, ®);
1828 *BitErr_reg = (*BitErr_reg << 8) | reg;
1829 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 1, ®);
1830 *BitErr_reg = (*BitErr_reg << 8) | reg;
1831 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 0, ®);
1832 *BitErr_reg = (*BitErr_reg << 8) | reg;
1833
1834 // bank 0x33 0x02 [0] freeze
1835 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1836
1837 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1838 *FecType = reg;
1839 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1840 *FecType = (*FecType << 8) | reg;
1841
1842 return status;
1843 }
1844
1845 #if 0
1846 /****************************************************************************
1847 Subject: To get the Pre LDPC BER
1848 Function: INTERN_DVBT2_GetPreLdpcBer
1849 Parmeter: ber
1850 Return: E_RESULT_SUCCESS
1851 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1852 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1853 We will not read the Period, and have the "/256/8"
1854 *****************************************************************************/
1855 MS_BOOL INTERN_DVBT2_GetPreLdpcBer(float *ber)
1856 {
1857 MS_U8 status = true;
1858 MS_U8 reg=0;
1859 MS_U16 BitErrPeriod;
1860 MS_U32 BitErr;
1861 MS_U16 FecType = 0;
1862
1863 /////////// Data BER /////////////
1864 // bank 0x33 0x02 [0] freeze
1865 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01); // avoid confliction
1866
1867 // bank 0x33 0x12 Data BER Window[15:0]
1868 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x25, ®);
1869 BitErrPeriod = reg;
1870 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x24, ®);
1871 BitErrPeriod = (BitErrPeriod << 8) | reg;
1872
1873 // bank 0x33 0x34 Data BER count[15:0]
1874 // bank 0x33 0x35 Data BER count[31:16]
1875 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 3, ®);
1876 BitErr = reg;
1877 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 2, ®);
1878 BitErr = (BitErr << 8) | reg;
1879 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 1, ®);
1880 BitErr = (BitErr << 8) | reg;
1881 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE + (0x32 << 1) + 0, ®);
1882 BitErr = (BitErr << 8) | reg;
1883
1884 // bank 0x33 0x02 [0] freeze
1885 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00); // avoid confliction
1886
1887 if (BitErrPeriod == 0)
1888 //protect 0
1889 BitErrPeriod = 1;
1890
1891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8f, ®); //FEC Type[8:7]
1892 FecType = reg;
1893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x8e, ®); //FEC Type[8:7]
1894 FecType = (FecType << 8) | reg;
1895
1896 if (FecType & 0x0180)
1897 {
1898 if (BitErr == 0)
1899 *ber = (float)0.5 / (float)(BitErrPeriod * 64800);
1900 else
1901 *ber = (float)BitErr / (float)(BitErrPeriod * 64800);
1902 }
1903 else
1904 {
1905 if (BitErr == 0)
1906 *ber = (float)0.5 / (float)(BitErrPeriod * 16200);
1907 else
1908 *ber = (float)BitErr / (float)(BitErrPeriod * 16200);
1909 }
1910
1911 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PreLDPCBER = %8.3e \n ", *ber));
1912
1913 if (status == FALSE)
1914 {
1915 printf("INTERN_DVBT2_GetPreLdpcBer Fail!\n");
1916 return FALSE;
1917 }
1918
1919 return status;
1920 }
1921 #endif
1922
1923 /****************************************************************************
1924 Subject: To get the Packet error
1925 Function: INTERN_DVBT2_GetPacketErr
1926 Parmeter: pktErr
1927 Return: E_RESULT_SUCCESS
1928 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT2_VIT_STATUS_NG
1929 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1930 We will not read the Period, and have the "/256/8"
1931 *****************************************************************************/
INTERN_DVBT2_GetPacketErr(MS_U16 * u16PktErr)1932 MS_BOOL INTERN_DVBT2_GetPacketErr(MS_U16 *u16PktErr)
1933 {
1934 MS_BOOL status = true;
1935 MS_U8 reg = 0;
1936 MS_U16 PktErr;
1937
1938 //freeze
1939 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x01);
1940 //read packet error
1941 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5B, ®);
1942 PktErr = reg;
1943 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FEC_REG_BASE+0x5A, ®);
1944 PktErr = (PktErr << 8) | reg;
1945
1946 *u16PktErr = PktErr;
1947 //release
1948 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2FEC_REG_BASE+0x04, 0x00);
1949
1950 DBG_GET_SIGNAL(printf("INTERN_DVBT2 PktErr = %d \n ", (int)PktErr));
1951
1952 *u16PktErr = PktErr;
1953
1954 return status;
1955 }
1956
1957 /****************************************************************************
1958 Subject: To get the DVBT2 parameter
1959 Function: INTERN_DVBT2_Get_L1_Info
1960 Parmeter: point to return parameter
1961 Return: TRUE
1962 FALSE
1963 Remark: The TPS parameters will be available after TPS lock
1964 *****************************************************************************/
INTERN_DVBT2_Get_L1_Parameter(MS_U16 * pu16L1_parameter,DMD_DVBT2_SIGNAL_INFO eSignalType)1965 MS_BOOL INTERN_DVBT2_Get_L1_Parameter( MS_U16 * pu16L1_parameter, DMD_DVBT2_SIGNAL_INFO eSignalType)
1966 {
1967 MS_U8 u8Data = 0;
1968 MS_U16 FecType = 0;
1969 MS_U16 u16Data = 0;
1970 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
1971 {
1972 if (eSignalType == T2_MODUL_MODE)
1973 {
1974 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1975 return FALSE;
1976
1977 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(5) | BIT(4) | BIT(3))) >> 3;
1978 }
1979 else if (eSignalType == T2_FFT_VALUE)
1980 {
1981 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2TDP_REG_BASE + (0x40 * 2) + 1, &u8Data) == FALSE)
1982 {
1983 return FALSE;
1984 }
1985 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
1986 }
1987 else if (eSignalType == T2_GUARD_INTERVAL)
1988 {
1989 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2TDP_REG_BASE + (0x40 * 2) + 1, &u8Data) == FALSE)
1990 {
1991 return FALSE;
1992 }
1993 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(6) | BIT(5) | BIT(4))) >> 4;
1994 }
1995 else if (eSignalType == T2_CODE_RATE)
1996 {
1997 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
1998 {
1999 return FALSE;
2000 }
2001 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(2) | BIT(1) | BIT(0)));
2002 }
2003 else if (eSignalType == T2_PREAMBLE)
2004 {
2005 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
2006 {
2007 return FALSE;
2008 }
2009 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(4))) >> 4;
2010 }
2011 else if (eSignalType == T2_S1_SIGNALLING)
2012 {
2013 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
2014 {
2015 return FALSE;
2016 }
2017 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(3) | BIT(2) | BIT(1))) >> 1;
2018 }
2019 else if (eSignalType == T2_PILOT_PATTERN)
2020 {
2021 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x36 * 2), &u8Data) == FALSE)
2022 {
2023 return FALSE;
2024 }
2025 *pu16L1_parameter = (((MS_U16) u8Data) & 0x0F);
2026 }
2027 else if (eSignalType == T2_BW_EXT)
2028 {
2029 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x30 * 2) + 1, &u8Data) == FALSE)
2030 {
2031 return FALSE;
2032 }
2033 *pu16L1_parameter = (((MS_U16) u8Data) & (BIT(0)));
2034 }
2035 else if (eSignalType == T2_PAPR_REDUCTION)
2036 {
2037 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2), &u8Data) == FALSE)
2038 {
2039 return FALSE;
2040 }
2041 *pu16L1_parameter = (((MS_U16) u8Data) & 0xF0) >> 4;
2042 }
2043 else if (eSignalType == T2_OFDM_SYMBOLS_PER_FRAME)
2044 {
2045 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2), &u8Data) == FALSE)
2046 {
2047 return FALSE;
2048 }
2049 *pu16L1_parameter = (MS_U16) u8Data;
2050 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3C * 2) + 1, &u8Data) == FALSE)
2051 {
2052 return FALSE;
2053 }
2054 *pu16L1_parameter |= (((MS_U16) u8Data) & 0x0F) << 8;
2055 }
2056 else if (eSignalType == T2_PLP_ROTATION)
2057 {
2058 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x47 * 2), &u8Data) == FALSE)
2059 {
2060 return FALSE;
2061 }
2062 *pu16L1_parameter = (((MS_U16) u8Data) & BIT(6)) >> 6;
2063 }
2064 else if (eSignalType == T2_PLP_FEC_TYPE)
2065 {
2066 //FEC Type[8:7]
2067 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8f, &u8Data) == FALSE) return FALSE;
2068 FecType = u8Data;
2069 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + 0x8e, &u8Data) == FALSE) return FALSE;
2070 FecType = (FecType << 8) | u8Data;
2071
2072 *pu16L1_parameter = (FecType & 0x0180) >> 7;
2073 }
2074 else if (eSignalType == T2_NUM_PLP)
2075 {
2076 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x42 * 2), &u8Data) == FALSE)
2077 {
2078 return FALSE;
2079 }
2080 *pu16L1_parameter = (MS_U16)u8Data;
2081 }
2082 else if (eSignalType == T2_PLP_TYPE)
2083 {
2084 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x45 * 2) + 1, &u8Data) == FALSE)
2085 {
2086 return FALSE;
2087 }
2088 *pu16L1_parameter = ((MS_U16) u8Data) & 0x07;
2089 }
2090 else if (eSignalType == T2_PLP_TIME_IL_TYPE)
2091 {
2092 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x48 * 2) + 1, &u8Data) == FALSE)
2093 {
2094 return FALSE;
2095 }
2096 *pu16L1_parameter = (((MS_U16) u8Data) & 0x10) >> 4;
2097 }
2098 else if (eSignalType == T2_PLP_TIME_IL_LENGTH)
2099 {
2100 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x49 * 2) + 1, &u8Data) == FALSE)
2101 {
2102 return FALSE;
2103 }
2104 *pu16L1_parameter = ((MS_U16) u8Data) & 0xFF;
2105 }
2106 else if (eSignalType == T2_DAT_ISSY)
2107 {
2108 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE)
2109 {
2110 return FALSE;
2111 }
2112 *pu16L1_parameter = (((MS_U16) u8Data) & 0x10) >> 4;
2113 }
2114 else if (eSignalType == T2_PLP_MODE)
2115 {
2116 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x01) == FALSE)
2117 {
2118 return FALSE;
2119 }
2120 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2), 0x16) == FALSE)
2121 {
2122 return FALSE;
2123 }
2124 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2DJB_REG_BASE + (0x61 * 2), &u8Data) == FALSE)
2125 {
2126 return FALSE;
2127 }
2128 if (MDrv_SYS_DMD_VD_MBX_WriteReg(T2DJB_REG_BASE + (0x60 * 2) + 1, 0x00) == FALSE)
2129 {
2130 return FALSE;
2131 }
2132 *pu16L1_parameter = ((MS_U16) u8Data) & 0x03;
2133 }
2134 else if (eSignalType == T2_L1_MODULATION)
2135 {
2136 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x31 * 2) + 1, &u8Data) == FALSE)
2137 {
2138 return FALSE;
2139 }
2140 *pu16L1_parameter = ((MS_U16) u8Data) & 0x0F;
2141 }
2142 else if (eSignalType == T2_NUM_T2_FRAMES)
2143 {
2144 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x3b * 2), &u8Data) == FALSE)
2145 {
2146 return FALSE;
2147 }
2148 *pu16L1_parameter = ((MS_U16) u8Data) & 0xFF;
2149 }
2150 else if (eSignalType == T2_PLP_NUM_BLOCKS_MAX)
2151 {
2152 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x55 * 2) + 1, &u8Data) == FALSE) return FALSE;
2153 u16Data = u8Data & 0x03;
2154 if (MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x55 * 2), &u8Data) == FALSE) return FALSE;
2155 u16Data = (u16Data << 8) | u8Data;
2156
2157 *pu16L1_parameter = u16Data;
2158 }
2159 else if (eSignalType == T2_FEF_ENABLE)
2160 {
2161
2162 if (MDrv_SYS_DMD_VD_MBX_ReadDSPReg(0x00F1, &u8Data) == FALSE)
2163 {
2164 DBG_INTERN_DVBT2(printf(">INTERN_DVBT2_GetLock MBX_ReadDspReg fail \n"));
2165 return FALSE;
2166 }
2167 *pu16L1_parameter = ((MS_U16) u8Data) & 0x01;
2168 }
2169 else
2170 {
2171 return FALSE;
2172 }
2173
2174 return TRUE;
2175
2176 }
2177
2178 return FALSE;
2179 }
2180
2181
2182 /****************************************************************************
2183 Subject: Read the signal to noise ratio (SNR)
2184 Function: INTERN_DVBT2_GetSNR
2185 Parmeter: None
2186 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
2187 Remark:
2188 *****************************************************************************/
INTERN_DVBT2_GetSNR(MS_U16 * u16_snr100,MS_U8 * snr_cali,MS_U8 * u8_gi)2189 MS_BOOL INTERN_DVBT2_GetSNR (MS_U16 *u16_snr100, MS_U8 *snr_cali, MS_U8 *u8_gi)
2190 {
2191 MS_U8 status = true;
2192 MS_U8 reg=0, reg_frz=0;
2193 // MS_U16 u16_snr100 = 0;
2194 // float f_snr;
2195 // MS_U8 u8_win = 0;
2196 // MS_U8 u8_gi = 0;
2197
2198 // freeze
2199 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0xef, ®_frz);
2200 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz|0x80);
2201
2202 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_H,®);
2203 *u16_snr100 = reg;
2204 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_L,®);
2205 *u16_snr100 = (*u16_snr100<<8)|reg;
2206
2207 // unfreeze
2208 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz);
2209
2210 // f_snr = (float)u16_snr100/100.0;
2211
2212 // snr cali
2213 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, ®);
2214 *snr_cali = (reg>>2)&0x01;
2215
2216 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x31*2, ®);
2217 *u8_gi = (reg>>1)&0x07;
2218
2219 return status;
2220 #if 0
2221 if (u8_win == 1)
2222 {
2223 float snr_offset = 0.0;
2224 float snr_cali = 0.0;
2225
2226 if (u8_gi == 0) snr_offset = 0.157;
2227 else if(u8_gi == 1) snr_offset = 0.317;
2228 else if(u8_gi == 2) snr_offset = 0.645;
2229 else if(u8_gi == 3) snr_offset = 1.335;
2230 else if(u8_gi == 4) snr_offset = 0.039;
2231 else if(u8_gi == 5) snr_offset = 0.771;
2232 else if(u8_gi == 6) snr_offset = 0.378;
2233
2234 snr_cali = f_snr - snr_offset;
2235 if (snr_cali > 0.0) f_snr = snr_cali;
2236 }
2237 //use Polynomial curve fitting to fix snr
2238 //snr_poly = 0.0027945*pow(*fSNR,3) - 0.2266*pow(*fSNR,2) + 6.0101*(*fSNR) - 53.3621;
2239 //f_snr = f_snr + snr_poly;
2240
2241 if (status == true)
2242 return f_snr;
2243 else
2244 return -1;
2245 #endif
2246
2247 }
2248
2249 #if 0
2250 float INTERN_DVBT2_GetSNR (void)
2251 {
2252 MS_U8 status = true;
2253 MS_U8 reg=0, reg_frz=0;
2254 MS_U16 u16_snr100 = 0;
2255 float f_snr;
2256 MS_U8 u8_win = 0;
2257 MS_U8 u8_gi = 0;
2258
2259 // freeze
2260 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE+0xef, ®_frz);
2261 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz|0x80);
2262
2263 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_H,®);
2264 u16_snr100 = reg;
2265 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg((MS_U32)E_DMD_T2_SNR_L,®);
2266 u16_snr100 = (u16_snr100<<8)|reg;
2267
2268 // unfreeze
2269 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE+0xef, reg_frz);
2270
2271 f_snr = (float)u16_snr100/100.0;
2272
2273 // snr cali
2274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2FDP_REG_BASE+0x01*2, ®);
2275 u8_win = (reg>>2)&0x01;
2276
2277 if (u8_win == 1)
2278 {
2279 float snr_offset = 0.0;
2280 float snr_cali = 0.0;
2281
2282 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE+0x31*2, ®);
2283 u8_gi = (reg>>1)&0x07;
2284
2285 if (u8_gi == 0) snr_offset = 0.157;
2286 else if(u8_gi == 1) snr_offset = 0.317;
2287 else if(u8_gi == 2) snr_offset = 0.645;
2288 else if(u8_gi == 3) snr_offset = 1.335;
2289 else if(u8_gi == 4) snr_offset = 0.039;
2290 else if(u8_gi == 5) snr_offset = 0.771;
2291 else if(u8_gi == 6) snr_offset = 0.378;
2292
2293 snr_cali = f_snr - snr_offset;
2294 if (snr_cali > 0.0) f_snr = snr_cali;
2295 }
2296 //use Polynomial curve fitting to fix snr
2297 //snr_poly = 0.0027945*pow(*fSNR,3) - 0.2266*pow(*fSNR,2) + 6.0101*(*fSNR) - 53.3621;
2298 //f_snr = f_snr + snr_poly;
2299
2300 if (status == true)
2301 return f_snr;
2302 else
2303 return -1;
2304
2305 }
2306 #endif
2307
2308 #if 0
2309 MS_BOOL INTERN_DVBT2_GetSignalStrength(MS_U16 *strength,const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2310 {
2311 MS_U8 status = true;
2312 float ch_power_db = 0.0f;
2313 float ch_power_ref = 11.0f;
2314 float ch_power_rel = 0.0f;
2315 //MS_U8 u8_index = 0;
2316 MS_U16 L1_info_qam, L1_info_cr;
2317 // MS_U8 demodState = 0;
2318
2319 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2320 {
2321 *strength = 0;
2322 return TRUE;
2323 }
2324 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
2325
2326 // if (INTERN_DVBT2_Lock(COFDM_TPS_LOCK))
2327 //if (INTERN_DVBT2_Lock(COFDM_AGC_LOCK))
2328 /* Actually, it's more reasonable, that signal level depended on cable input power level
2329 * thougth the signal isn't dvb-t signal.
2330 */
2331
2332 #if 0
2333 // use pointer of IFAGC table to identify
2334 // case 1: RFAGC from SAR, IFAGC controlled by demod
2335 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
2336 status &= HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
2337 sDMD_DVBT2_InitData->pTuner_RfagcSsi, sDMD_DVBT2_InitData->u16Tuner_RfagcSsi_Size,
2338 sDMD_DVBT2_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_HiRef_Size,
2339 sDMD_DVBT2_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_LoRef_Size,
2340 sDMD_DVBT2_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_HiRef_Size,
2341 sDMD_DVBT2_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_LoRef_Size);
2342 #endif
2343
2344 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2345 printf("[dvbt2] QAM parameter retrieve failure\n");
2346
2347 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2348 printf("[dvbt2]code rate parameter retrieve failure\n");
2349
2350 /*
2351 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2352 {
2353 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)L1_info_qam)
2354 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)L1_info_cr))
2355 {
2356 ch_power_ref = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2357 break;
2358 }
2359 else
2360 {
2361 u8_index++;
2362 }
2363 }
2364 */
2365 ch_power_ref = dvbt2_ssi_dbm_nordigp1[(MS_U8)L1_info_qam][(MS_U8)L1_info_cr];
2366
2367 // status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + (0x62*2), &demodState);
2368
2369 if (ch_power_ref > 10.0f)
2370 *strength = 0;
2371 else
2372 {
2373 // For Nordig's SSI test items
2374 if ( (L1_info_qam == 3) //256qam
2375 && (L1_info_cr > 0 && L1_info_cr < 4) // CR 3/5,2/3,3/4
2376 )
2377 {
2378 MS_U8 u8_x = L1_info_cr - 1;
2379 float f_ssi = 0.0;
2380
2381 if(ch_power_db >= -45)f_ssi = 100;
2382 else if (ch_power_db >= -50) f_ssi = fT2_SSI_formula[u8_x][0]*(ch_power_db + 50) + fT2_SSI_formula[u8_x][1];
2383 else if (ch_power_db >= -60) f_ssi = fT2_SSI_formula[u8_x][2]*(ch_power_db + 60) + fT2_SSI_formula[u8_x][3];
2384 else if (ch_power_db >= -70) f_ssi = fT2_SSI_formula[u8_x][4]*(ch_power_db + 70) + fT2_SSI_formula[u8_x][5];
2385 else if (ch_power_db >= -80) f_ssi = fT2_SSI_formula[u8_x][6]*(ch_power_db + 80) + fT2_SSI_formula[u8_x][7];
2386 else if (ch_power_db >= -95) f_ssi = fT2_SSI_formula[u8_x][8]*(ch_power_db + 95) + fT2_SSI_formula[u8_x][9];
2387 else if (ch_power_db >= -100) f_ssi = fT2_SSI_formula[u8_x][10]*(ch_power_db + 100) + fT2_SSI_formula[u8_x][11];
2388
2389 if (f_ssi > 100) *strength = 100;
2390 else if (f_ssi < 0) *strength = 0;
2391 else *strength = (MS_U16)(f_ssi+0.5);
2392
2393 DBG_GET_SIGNAL(printf(">>> SSI... RF_level=%d, f_ssi=%d, ssi=%d, cr=%d, mod=%d\n", (MS_S16)ch_power_db, (MS_S16)f_ssi, (MS_S16)(*strength), L1_info_cr, L1_info_qam));
2394 }
2395 else
2396 {
2397 ch_power_rel = ch_power_db - ch_power_ref;
2398 /*
2399 if (demodState != 0x09)
2400 {
2401 ch_power_rel = ch_power_db - (-50.0f);
2402 }
2403 else
2404 {
2405 ch_power_rel = ch_power_db - ch_power_ref;
2406 }
2407 */
2408 if ( ch_power_rel < -15.0f )
2409 {
2410 *strength = 0;
2411 }
2412 else if ( ch_power_rel < 0.0f )
2413 {
2414 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
2415 }
2416 else if ( ch_power_rel < 20 )
2417 {
2418 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
2419 }
2420 else if ( ch_power_rel < 35.0f )
2421 {
2422 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
2423 }
2424 else
2425 {
2426 *strength = 100;
2427 }
2428 }
2429 }
2430
2431 if (FALSE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) )
2432 {
2433 *strength = 0;
2434 return TRUE;
2435 }
2436
2437 DBG_GET_SIGNAL(printf(">>> ch_power_ref(dB) = %d , ch_power_db(dB) = %d, ch_power_rel(dB) = %d<<<\n", (MS_S16)ch_power_ref, (MS_S16)ch_power_db, (MS_S16)ch_power_rel));
2438 DBG_GET_SIGNAL(printf(">>> SSI_CH_PWR(dB) = %d , Score = %d<<<\n", (MS_S16)ch_power_db, *strength));
2439 DBG_GET_SIGNAL(printf(">>> SSI = %d <<<\n", (int)*strength));
2440
2441 return status;
2442 }
2443 #endif
2444
2445 #if 0
2446 /****************************************************************************
2447 Subject: To get the DVT Signal quility
2448 Function: INTERN_DVBT2_GetSignalQuality
2449 Parmeter: Quility
2450 Return: E_RESULT_SUCCESS
2451 E_RESULT_FAILURE
2452 Remark: Here we have 4 level range
2453 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_100)
2454 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_60)
2455 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT2_SIGNAL_BASE_10)
2456 <4>.4th Range => Quality <10
2457 *****************************************************************************/
2458 MS_BOOL INTERN_DVBT2_GetSignalQuality(MS_U16 *quality, const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
2459 {
2460 // float ber_sqi, SQI;
2461 float fber;
2462 float cn_rec = 0;
2463 float cn_ref = 0;
2464 float cn_rel = 0;
2465
2466 #if 0
2467 float fBerTH1[] = {1E-4, 1E-4*(1.0-DVBT2_BER_TH_HY), 1E-4*(1.0+DVBT2_BER_TH_HY), 1E-4};
2468 float fBerTH2[] = {3E-7, 3E-7, 3E-7*(1.0-DVBT2_BER_TH_HY), 3E-7*(1.0+DVBT2_BER_TH_HY)};
2469 float BER_SQI = (float)0.0;
2470 float SQI = (float)0.0;
2471 static MS_U8 u8SQIState = 0;
2472 #endif
2473
2474 MS_U8 status = true;
2475 MS_U16 L1_info_qam = 0, L1_info_cr = 0, i = 0;
2476
2477 DBG_INTERN_DVBT2_TIME(printf("INTERN_DVBT2_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
2478
2479 if (TRUE == INTERN_DVBT2_GetLock(E_DMD_DVBT2_P1_LOCK) )
2480 {
2481 #if 1 // copy from msb1240
2482 if (fBerFilteredDVBT2 < 0.0)
2483 {
2484 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2485 {
2486 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2487 return FALSE;
2488 }
2489 fBerFilteredDVBT2 = fber;
2490 }
2491 else
2492 {
2493 fber = fBerFilteredDVBT2;
2494 }
2495
2496 if (fber > fBerTH1[u8SQIState])
2497 {
2498 BER_SQI = 0.0;
2499 u8SQIState = 1;
2500 }
2501 else if (fber >=fBerTH2[u8SQIState])
2502 {
2503 BER_SQI = 100.0/15;
2504 u8SQIState = 2;
2505 }
2506 else
2507 {
2508 BER_SQI = 100.0/6;
2509 u8SQIState = 3;
2510 }
2511
2512 cn_rec = INTERN_DVBT2_GetSNR();
2513 if (cn_rec < 0.0)
2514 return FALSE;
2515
2516 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2517 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2518 L1_info_qam = 0xff;
2519 L1_info_cr = 0xff;
2520
2521 cn_ref = (float)-1.0;
2522 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2523 printf("[dvbt2] QAM parameter retrieve failure\n");
2524
2525 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2526 printf("[dvbt2]code rate parameter retrieve failure\n");
2527
2528 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2529 {
2530 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2531 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2532 {
2533 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2534 break;
2535 }
2536 }
2537
2538 if (cn_ref < 0.0)
2539 {
2540 SQI = (float)0.0;
2541 printf("SQI is zero, 1\n");
2542 }
2543 else
2544 {
2545 // 0.7, snr offset
2546 cn_rel = cn_rec - cn_ref + 0.7f;
2547 if (cn_rel > 3.0)
2548 SQI = 100;
2549 else if (cn_rel >= -3)
2550 {
2551 SQI = (cn_rel+3)*BER_SQI;
2552 if (SQI > 100.0) SQI = 100.0;
2553 else if (SQI < 0.0) SQI = 0.0;
2554 }
2555 else
2556 {
2557 SQI = (float)0.0;
2558 printf("SQI is zero, 2\n");
2559 }
2560 }
2561
2562 *quality = (MS_U16)SQI;
2563 #else
2564 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
2565 {
2566 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
2567 }
2568 ///////// Get Pre-BCH (Post-LDPC) BER to determine BER_SQI //////////
2569 if(fLDPCBerFiltered<= 0.0)
2570 {
2571 if (INTERN_DVBT2_GetPostLdpcBer(&fber) == FALSE)
2572 {
2573 DBG_INTERN_DVBT2(printf("GetPostViterbiBer Fail!\n"));
2574 return FALSE;
2575 }
2576 fLDPCBerFiltered = fber;
2577 }
2578 else
2579 {
2580 fber = fLDPCBerFiltered;
2581 }
2582 /*
2583 if (fber > 1.0E-3)
2584 ber_sqi = 0.0;
2585 else if (fber > 8.5E-7)
2586 #ifdef MSOS_TYPE_LINUX
2587 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
2588 #else
2589 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
2590 #endif
2591 else
2592 ber_sqi = 100.0;
2593 */
2594 if (fber > 1E-4)
2595 ber_sqi = 0.0;
2596 else if (fber >= 1E-7)
2597 ber_sqi = 100.0 / 15;
2598 else
2599 ber_sqi = 100.0 / 6;
2600
2601 cn_rec = INTERN_DVBT2_GetSNR();
2602
2603 if (cn_rec == -1) //get SNR return fail
2604 status = false;
2605
2606 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2607 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2608 L1_info_qam = 0xff;
2609 L1_info_cr = 0xff;
2610
2611 cn_ref = (float)-1.0;
2612 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_qam, T2_MODUL_MODE) == FALSE)
2613 printf("[dvbt2] QAM parameter retrieve failure\n");
2614
2615 if(INTERN_DVBT2_Get_L1_Parameter(&L1_info_cr, T2_CODE_RATE) == FALSE)
2616 printf("[dvbt2]code rate parameter retrieve failure\n");
2617
2618 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
2619 {
2620 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
2621 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
2622 {
2623 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
2624 break;
2625 }
2626 }
2627
2628 if (cn_ref == -1.0)
2629 SQI = (float)0.0;
2630 else
2631 {
2632 cn_rel = cn_rec - cn_ref;
2633 if (cn_rel > 3.0)
2634 SQI = 100;
2635 else if (cn_rel >= -3)
2636 {
2637 SQI = (cn_rel+3)*ber_sqi;
2638 if (SQI > 100.0) SQI = 100.0;
2639 else if (SQI < 0.0) SQI = 0.0;
2640 }
2641 else
2642 SQI = (float)0.0;
2643 }
2644
2645 // SQI patch, 256qam, R3/4 CN=20.8, SQI=0~13
2646 if ((L1_info_qam==_T2_256QAM) && (L1_info_cr==_T2_CR3Y4))
2647 {
2648 if ( (cn_rec > 20.6) && (cn_rec < 20.9))
2649 {
2650 if (SQI > 3) SQI -= 3;
2651 }
2652 else if ( (cn_rec >= 20.9) && (cn_rec < 21.2))
2653 {
2654 if (SQI > 9) SQI -= 9;
2655 }
2656 }
2657
2658 *quality = (MS_U16)SQI;
2659 #endif
2660 }
2661 else
2662 {
2663 *quality = 0;
2664 }
2665
2666 DBG_GET_SIGNAL(printf("SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, L1_info_qam, L1_info_cr));
2667 DBG_GET_SIGNAL(printf("BER = %8.3e\n", fber));
2668 DBG_GET_SIGNAL(printf("Signal Quility = %d\n", *quality));
2669 return status;
2670 }
2671 #endif
2672
2673 /****************************************************************************
2674 Subject: To get the DVBT Carrier Freq Offset
2675 Function: INTERN_DVBT2_Get_FreqOffset
2676 Parmeter: Frequency offset (in KHz), bandwidth
2677 Return: E_RESULT_SUCCESS
2678 E_RESULT_FAILURE
2679 Remark:
2680 *****************************************************************************/
INTERN_DVBT2_Get_FreqOffset(MS_U32 * CfoTd_reg,MS_U32 * CfoFd_reg,MS_U32 * Icfo_reg,MS_U8 * fft_reg)2681 MS_BOOL INTERN_DVBT2_Get_FreqOffset(MS_U32 *CfoTd_reg, MS_U32 *CfoFd_reg, MS_U32 *Icfo_reg, MS_U8 *fft_reg)
2682 {
2683 // float N, FreqB;
2684 // float FreqCfoTd, FreqCfoFd, FreqIcfo;
2685 // MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2686 MS_U8 reg_frz=0, reg=0;
2687 MS_U8 status;
2688
2689 #if 0
2690 FreqB = (float)u8BW * 8 / 7;
2691 #endif
2692
2693 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2694
2695 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2696
2697 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2698 *CfoTd_reg = reg;
2699
2700 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2701 *CfoTd_reg = (*CfoTd_reg << 8)|reg;
2702
2703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2704 *CfoTd_reg = (*CfoTd_reg << 8)|reg;
2705 #if 0
2706 FreqCfoTd = (float)RegCfoTd;
2707
2708 if (RegCfoTd & 0x800000)
2709 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2710
2711 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2712 #endif
2713
2714 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2715
2716 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2717 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2718
2719 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2720
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2722 *CfoFd_reg = reg;
2723
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2725 *CfoFd_reg = (*CfoFd_reg << 8)|reg;
2726
2727 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2728 *CfoFd_reg = (*CfoFd_reg << 8)|reg;
2729
2730 #if 0
2731 FreqCfoFd = (float)RegCfoFd;
2732
2733 if (RegCfoFd & 0x800000)
2734 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2735
2736 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2737 #endif
2738
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2740 *Icfo_reg = reg & 0x07;
2741
2742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2743 *Icfo_reg = (*Icfo_reg << 8)|reg;
2744
2745 #if 0
2746 FreqIcfo = (float)RegIcfo;
2747
2748 if (RegIcfo & 0x400)
2749 FreqIcfo = FreqIcfo - (float)0x800;
2750 #endif
2751
2752 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2753 *fft_reg = reg & 0x30;
2754
2755 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2756 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2757 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2758
2759 #if 0
2760 switch (*fft_reg)
2761 {
2762 case 0x00: N = 2048; break;
2763 case 0x20: N = 4096; break;
2764 case 0x10:
2765 default: N = 8192; break;
2766 }
2767
2768 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2769
2770
2771 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2772 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2773 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2774 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2775 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2776 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2777 #endif
2778
2779 if (status == TRUE)
2780 return TRUE;
2781 else
2782 return FALSE;
2783 }
2784
2785 #if 0
2786 /****************************************************************************
2787 Subject: To get the DVBT Carrier Freq Offset
2788 Function: INTERN_DVBT2_Get_FreqOffset
2789 Parmeter: Frequency offset (in KHz), bandwidth
2790 Return: E_RESULT_SUCCESS
2791 E_RESULT_FAILURE
2792 Remark:
2793 *****************************************************************************/
2794 MS_BOOL INTERN_DVBT2_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2795 {
2796 float N, FreqB;
2797 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2798 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2799 MS_U8 reg_frz=0, reg=0;
2800 MS_U8 status;
2801
2802 FreqB = (float)u8BW * 8 / 7;
2803
2804 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2805
2806 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2807
2808 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2809 RegCfoTd = reg;
2810
2811 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2812 RegCfoTd = (RegCfoTd << 8)|reg;
2813
2814 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2815 RegCfoTd = (RegCfoTd << 8)|reg;
2816
2817 FreqCfoTd = (float)RegCfoTd;
2818
2819 if (RegCfoTd & 0x800000)
2820 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2821
2822 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2823
2824 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2825
2826 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2827 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2828
2829 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2830
2831 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2832 RegCfoFd = reg;
2833
2834 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2835 RegCfoFd = (RegCfoFd << 8)|reg;
2836
2837 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2838 RegCfoFd = (RegCfoFd << 8)|reg;
2839
2840 FreqCfoFd = (float)RegCfoFd;
2841
2842 if (RegCfoFd & 0x800000)
2843 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2844
2845 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2846
2847 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2848 RegIcfo = reg & 0x07;
2849
2850 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2851 RegIcfo = (RegIcfo << 8)|reg;
2852
2853 FreqIcfo = (float)RegIcfo;
2854
2855 if (RegIcfo & 0x400)
2856 FreqIcfo = FreqIcfo - (float)0x800;
2857
2858 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2859 reg = reg & 0x30;
2860
2861 switch (reg)
2862 {
2863 case 0x00: N = 2048; break;
2864 case 0x20: N = 4096; break;
2865 case 0x10:
2866 default: N = 8192; break;
2867 }
2868
2869 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2870 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2871 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2872 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2873 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2874 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2875 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
2876 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
2877 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
2878 DBG_GET_SIGNAL(printf("CFOE = %f\n", *pFreqOff));
2879
2880 if (status == TRUE)
2881 return TRUE;
2882 else
2883 return FALSE;
2884 }
2885 #endif
2886
INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)2887 void INTERN_DVBT2_Power_ON_OFF(MS_U8 bPowerOn)
2888 {
2889
2890 bPowerOn = bPowerOn;
2891 }
2892
INTERN_DVBT2_Power_Save(void)2893 MS_BOOL INTERN_DVBT2_Power_Save(void)
2894 {
2895
2896 return TRUE;
2897 }
2898
INTERN_DVBT2_Version(MS_U16 * ver)2899 MS_BOOL INTERN_DVBT2_Version(MS_U16 *ver)
2900 {
2901
2902 MS_U8 status = true;
2903 MS_U8 tmp = 0;
2904 MS_U16 u16_INTERN_DVBT2_Version;
2905
2906 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2907 u16_INTERN_DVBT2_Version = tmp;
2908 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2909 u16_INTERN_DVBT2_Version = u16_INTERN_DVBT2_Version<<8|tmp;
2910 *ver = u16_INTERN_DVBT2_Version;
2911
2912 return status;
2913 }
2914
INTERN_DVBT2_Version_minor(MS_U8 * ver2)2915 MS_BOOL INTERN_DVBT2_Version_minor(MS_U8 *ver2)
2916 {
2917
2918 MS_U8 status = true;
2919
2920 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2921
2922 return status;
2923 }
2924
2925
INTERN_DVBT2_Show_Demod_Version(void)2926 MS_BOOL INTERN_DVBT2_Show_Demod_Version(void)
2927 {
2928
2929 MS_BOOL status = true;
2930 MS_U16 u16_INTERN_DVBT2_Version = 0;
2931 MS_U8 u8_minor_ver = 0;
2932
2933 status &= INTERN_DVBT2_Version(&u16_INTERN_DVBT2_Version);
2934 status &= INTERN_DVBT2_Version_minor(&u8_minor_ver);
2935 printf("[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT2_Version,u8_minor_ver);
2936
2937 return status;
2938 }
2939
2940 #if 0
2941 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value)
2942 {
2943 dvbt2_ssi_dbm_nordigp1[constel][code_rate] = write_value;
2944 return TRUE;
2945 /*
2946 MS_U8 u8_index = 0;
2947 MS_BOOL bRet = false;
2948
2949 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2950 {
2951 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
2952 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
2953 {
2954 dvbt2_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2955 bRet = true;
2956 break;
2957 }
2958 else
2959 {
2960 u8_index++;
2961 }
2962 }
2963 return bRet;
2964 */
2965 }
2966
2967 MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value)
2968 {
2969 *read_value = dvbt2_ssi_dbm_nordigp1[constel][code_rate];
2970 return TRUE;
2971 /*
2972 MS_U8 u8_index = 0;
2973 MS_BOOL bRet = false;
2974
2975 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2976 {
2977 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)constel)
2978 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)code_rate))
2979 {
2980 *read_value = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
2981 bRet = true;
2982 break;
2983 }
2984 else
2985 {
2986 u8_index++;
2987 }
2988 }
2989 return bRet;
2990 */
2991 }
2992 #endif
2993
INTERN_DVBT2_GetPlpBitMap(MS_U8 * u8PlpBitMap)2994 MS_BOOL INTERN_DVBT2_GetPlpBitMap(MS_U8* u8PlpBitMap)
2995 {
2996 MS_BOOL status = TRUE;
2997 MS_U8 u8Data = 0;
2998 MS_U8 indx = 0;
2999
3000 DBG_INTERN_DVBT2(printf("INTERN_DVBT2_GetPlpBitMap\n"));
3001
3002 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
3003 if (u8Data != 0x30)
3004 {
3005 DBG_INTERN_DVBT2(printf("\n[INTERN_DVBT2_GetPlpBitMap] Check L1 NOT Ready !! E_DMD_T2_L1_FLAG = 0x%x\n", u8Data));
3006 return FALSE;
3007 }
3008 while (indx < 32)
3009 {
3010 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_PLP_ID_ARR + indx, &u8Data);
3011 u8PlpBitMap[indx] = u8Data;
3012 indx++;
3013 }
3014
3015 if (status)
3016 {
3017 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap data+++++++++++++++\n"));
3018 for (indx = 0; indx < 32; indx++)
3019 DBG_INTERN_DVBT2(printf("[%d] ", u8PlpBitMap[indx]));
3020 DBG_INTERN_DVBT2(printf("\n+++++++++u8PlpBitMap end+++++++++++++++\n"));
3021 }
3022 return status;
3023 }
3024
INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID,MS_U8 * u8GroupID)3025 MS_BOOL INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID, MS_U8* u8GroupID)
3026 {
3027 MS_BOOL status = TRUE;
3028 MS_U8 u8Data = 0;
3029 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_L1_FLAG, &u8Data); // check L1 ready
3030 if (u8Data != 0x30)
3031 {
3032 printf(">>>dvbt2 L1 not ready yet\n");
3033 return FALSE;
3034 }
3035 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_T2_DVBT2_LOCK_HIS, &u8Data);
3036
3037 if ((u8Data & BIT(7)) == 0x00)
3038 {
3039 printf(">>>dvbt2 is un-lock\n");
3040 return FALSE;
3041 }
3042 // assign PLP-ID value
3043 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x78) * 2, u8PlpID);
3044 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x01); // MEM_EN
3045 MsOS_DelayTask(1);
3046 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(T2L1_REG_BASE + (0x79) * 2, u8GroupID);
3047 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(T2L1_REG_BASE + (0x01) * 2 + 1, 0x00); // ~MEM_EN
3048
3049 return status;
3050 }
3051
INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID,MS_U8 u8GroupID)3052 MS_BOOL INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID, MS_U8 u8GroupID)
3053 {
3054 MS_BOOL status = TRUE;
3055
3056 // assign Group-ID and PLP-ID value (must be written in order)
3057 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_GROUP_ID, u8GroupID);
3058 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_T2_PLP_ID, u8PlpID);
3059
3060 return status;
3061 }
3062
3063 #if (INTERN_DVBT2_INTERNAL_DEBUG == 1)
INTERN_DVBT2_get_demod_state(MS_U8 * state)3064 void INTERN_DVBT2_get_demod_state(MS_U8* state)
3065 {
3066 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
3067 return;
3068 }
3069
INTERN_DVBT2_Show_ChannelLength(void)3070 MS_BOOL INTERN_DVBT2_Show_ChannelLength(void)
3071 {
3072 MS_U8 status = true;
3073 MS_U8 tmp = 0;
3074 MS_U16 len = 0;
3075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
3076 len = tmp;
3077 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
3078 len = (len<<8)|tmp;
3079 printf("[dvbt]Hw_channel=%d\n",len);
3080 return status;
3081 }
3082
INTERN_DVBT2_Show_SW_ChannelLength(void)3083 MS_BOOL INTERN_DVBT2_Show_SW_ChannelLength(void)
3084 {
3085 MS_U8 status = true;
3086 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
3087 MS_U16 sw_len = 0;
3088 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
3089 sw_len = tmp;
3090 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
3091 sw_len = (sw_len<<8)|tmp;
3092 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
3093 peak_num = tmp;
3094 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
3095 insideGI = tmp&0x01;
3096 stoptracking = (tmp&0x02)>>1;
3097 flag_short_echo = (tmp&0x0C)>>2;
3098 fsa_mode = (tmp&0x30)>>4;
3099
3100 printf("[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
3101 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
3102
3103 return status;
3104 }
3105
INTERN_DVBT2_Show_ACI_CI(void)3106 MS_BOOL INTERN_DVBT2_Show_ACI_CI(void)
3107 {
3108
3109 #define BIT4 0x10
3110 MS_U8 status = true;
3111 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
3112
3113 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
3114 digACI = (tmp&BIT4)>>4;
3115
3116 // get flag_CI
3117 // 0: No interference
3118 // 1: CCI
3119 // 2: in-band ACI
3120 // 3: N+1 ACI
3121 // flag_ci = (tmp&0xc0)>>6;
3122 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
3123 flag_CI = (tmp&0xC0)>>6;
3124 td_coef = (tmp&0x0C)>>2;
3125
3126 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
3127
3128 printf("[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
3129
3130 return status;
3131 }
3132
INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)3133 MS_BOOL INTERN_DVBT2_Show_FD_CH_LEN_S_SEL(void)
3134 {
3135 MS_U8 status = true;
3136 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
3137 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
3138 fd = tmp;
3139 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
3140 ch_len = tmp;
3141 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
3142 snr_sel = (tmp>>4)&0x03;
3143 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
3144 pertone_num = tmp;
3145
3146 printf("[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
3147
3148 return status;
3149 }
3150
INTERN_DVBT2_Get_CFO(void)3151 MS_BOOL INTERN_DVBT2_Get_CFO(void)
3152 {
3153 #if 0
3154 float N = 0, FreqB = 0;
3155 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
3156 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
3157 MS_U8 reg_frz = 0, reg = 0;
3158 MS_U8 status = 0;
3159 MS_U8 u8BW = 8;
3160
3161 FreqB = (float)u8BW * 8 / 7;
3162
3163 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
3164
3165 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
3166
3167 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
3168 RegCfoTd = reg;
3169
3170 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
3171 RegCfoTd = (RegCfoTd << 8)|reg;
3172
3173 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
3174 RegCfoTd = (RegCfoTd << 8)|reg;
3175
3176 FreqCfoTd = (float)RegCfoTd;
3177
3178 if (RegCfoTd & 0x800000)
3179 FreqCfoTd = FreqCfoTd - (float)0x1000000;
3180
3181 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
3182
3183 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
3184
3185 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
3186 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
3187
3188 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
3189
3190 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
3191 RegCfoFd = reg;
3192
3193 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
3194 RegCfoFd = (RegCfoFd << 8)|reg;
3195
3196 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
3197 RegCfoFd = (RegCfoFd << 8)|reg;
3198
3199 FreqCfoFd = (float)RegCfoFd;
3200
3201 if (RegCfoFd & 0x800000)
3202 FreqCfoFd = FreqCfoFd - (float)0x1000000;
3203
3204 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
3205
3206 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
3207 RegIcfo = reg & 0x07;
3208
3209 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
3210 RegIcfo = (RegIcfo << 8)|reg;
3211
3212 FreqIcfo = (float)RegIcfo;
3213
3214 if (RegIcfo & 0x400)
3215 FreqIcfo = FreqIcfo - (float)0x800;
3216
3217 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
3218 reg = reg & 0x30;
3219
3220 switch (reg)
3221 {
3222 case 0x00: N = 2048; break;
3223 case 0x20: N = 4096; break;
3224 case 0x10:
3225 default: N = 8192; break;
3226 }
3227
3228 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
3229 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
3230 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
3231 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
3232 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
3233
3234 printf("[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
3235 return status;
3236 #endif
3237 return true;
3238 }
INTERN_DVBT2_Get_SFO(void)3239 MS_BOOL INTERN_DVBT2_Get_SFO(void)
3240 {
3241 #if 0
3242 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
3243 MS_BOOL status = true;
3244 MS_U8 reg = 0;
3245 float FreqB = 9.143, FreqS = 45.473; //20.48
3246 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
3247 float sfo_value = 0;
3248
3249 // get Reg_TDP_SFO,
3250 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
3251 Reg_TDP_SFO = reg;
3252 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
3253 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
3254 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
3255 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
3256
3257 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
3258
3259 // get Reg_FDP_SFO,
3260 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
3261 Reg_FDP_SFO = reg;
3262 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
3263 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
3264 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
3265 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
3266
3267 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
3268
3269 // get Reg_FSA_SFO,
3270 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
3271 Reg_FSA_SFO = reg;
3272 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
3273 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
3274 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
3275 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
3276
3277 // get Reg_FSA_IN,
3278 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
3279 Reg_FSA_IN = reg;
3280 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
3281 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
3282 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
3283
3284 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
3285 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
3286
3287 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
3288 // printf("\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
3289 printf("[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
3290
3291
3292 return status;
3293 #endif
3294 return true;
3295 }
3296
INTERN_DVBT2_Get_SYA_status(void)3297 void INTERN_DVBT2_Get_SYA_status(void)
3298 {
3299 MS_U8 status = true;
3300 MS_U8 sya_k = 0,reg = 0;
3301 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
3302
3303 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
3304 sya_k = reg;
3305
3306 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
3307 sya_th = reg;
3308 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
3309 sya_th = (sya_th<<8)|reg;
3310
3311 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
3312 sya_offset = reg;
3313 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
3314 sya_offset = (sya_offset<<8)|reg;
3315
3316 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
3317 len_m = reg;
3318 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
3319 len_m = (len_m<<8)|reg;
3320
3321 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
3322 len_b = reg;
3323 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
3324 len_b = (len_b<<8)|reg;
3325
3326
3327 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
3328 len_a = reg;
3329 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
3330 len_a = (len_a<<8)|reg;
3331
3332
3333 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
3334 tracking_reg = reg;
3335
3336
3337 printf("[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
3338 printf("[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
3339
3340 return;
3341 }
3342
INTERN_DVBT2_Get_cci_status(void)3343 void INTERN_DVBT2_Get_cci_status(void)
3344 {
3345 MS_U8 status = true;
3346 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
3347
3348 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
3349 cci_fsweep = reg;
3350
3351 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
3352 cci_kp = reg;
3353
3354 printf("[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
3355
3356 return;
3357 }
3358
INTERN_DVBT2_Show_PRESFO_Info(void)3359 MS_BOOL INTERN_DVBT2_Show_PRESFO_Info(void)
3360 {
3361 MS_U8 tmp = 0;
3362 MS_BOOL status = TRUE;
3363 printf("\n[SFO]");
3364 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
3365 printf("[%x]",tmp);
3366 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
3367 printf("[%x]",tmp);
3368 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
3369 printf("[%x]",tmp);
3370 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
3371 printf("[%x]",tmp);
3372 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
3373 printf("[%x]",tmp);
3374 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
3375 printf("[%x]",tmp);
3376 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
3377 printf("[%x]",tmp);
3378 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
3379 printf("[%x][End]",tmp);
3380
3381 return status;
3382 }
3383
INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 * locktime)3384 MS_BOOL INTERN_DVBT2_Get_Lock_Time_Info(MS_U16 *locktime)
3385 {
3386 MS_BOOL status = true;
3387
3388 *locktime = 0xffff;
3389 printf("[dvbt]INTERN_DVBT2_Get_Lock_Time_Info not implement\n");
3390
3391 status = false;
3392 return status;
3393 }
3394
3395
INTERN_DVBT2_Show_Lock_Time_Info(void)3396 MS_BOOL INTERN_DVBT2_Show_Lock_Time_Info(void)
3397 {
3398 MS_U16 locktime = 0;
3399 MS_BOOL status = TRUE;
3400 status &= INTERN_DVBT2_Get_Lock_Time_Info(&locktime);
3401 printf("[DVBT]lock_time = %d ms\n",locktime);
3402 return status;
3403 }
3404
INTERN_DVBT2_Show_BER_Info(void)3405 MS_BOOL INTERN_DVBT2_Show_BER_Info(void)
3406 {
3407 MS_U8 tmp = 0;
3408 MS_BOOL status = TRUE;
3409 printf("\n[BER]");
3410 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
3411 printf("[%x,",tmp);
3412 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
3413 printf("%x]",tmp);
3414 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
3415 printf("[%x,",tmp);
3416 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
3417 printf("%x]",tmp);
3418 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
3419 printf("[%x,",tmp);
3420 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
3421 printf("%x][End]",tmp);
3422
3423 return status;
3424
3425 }
3426
3427
INTERN_DVBT2_Show_AGC_Info(void)3428 MS_BOOL INTERN_DVBT2_Show_AGC_Info(void)
3429 {
3430 MS_U8 tmp = 0;
3431 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
3432 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
3433 MS_U16 if_agc_err = 0;
3434 MS_BOOL status = TRUE;
3435 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
3436
3437 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
3438 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
3439 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
3440 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
3441 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
3442 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
3443
3444
3445 // select IF gain to read
3446 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3447 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
3448
3449 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3450 if_agc_gain = tmp;
3451 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3452 if_agc_gain = (if_agc_gain<<8)|tmp;
3453
3454
3455 // select d1 gain to read.
3456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
3457 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
3458
3459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
3460 d1_gain = tmp;
3461 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
3462 d1_gain = (d1_gain<<8)|tmp;
3463
3464 // select d2 gain to read.
3465 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
3466 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
3467
3468 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
3469 d2_gain = tmp;
3470 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
3471 d2_gain = (d2_gain<<8)|tmp;
3472
3473 // select IF gain err to read
3474 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
3475 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
3476
3477 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
3478 if_agc_err = tmp;
3479 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
3480 if_agc_err = (if_agc_err<<8)|tmp;
3481
3482 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
3483 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
3484 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
3485
3486
3487
3488 printf("[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
3489 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
3490
3491 printf("[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
3492 printf("[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
3493
3494 return status;
3495 }
3496
INTERN_DVBT2_Show_WIN_Info(void)3497 MS_BOOL INTERN_DVBT2_Show_WIN_Info(void)
3498 {
3499 MS_U8 tmp = 0;
3500 MS_U8 trigger = 0;
3501 MS_U16 win_len = 0;
3502
3503 MS_BOOL status = TRUE;
3504
3505 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
3506 win_len = tmp;
3507 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
3508 win_len = (win_len<<8)|tmp;
3509
3510 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
3511
3512 printf("[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
3513
3514 return status;
3515 }
3516
INTERN_DVBT2_Show_td_coeff(void)3517 void INTERN_DVBT2_Show_td_coeff(void)
3518 {
3519 MS_U8 status = true;
3520 MS_U8 w1 = 0,w2 = 0,reg = 0;
3521
3522 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
3523 w1 = reg;
3524
3525 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
3526 w2 = reg;
3527
3528 printf("[td]w1=0x%x, w2=0x%x\n",w1,w2);
3529
3530 return;
3531 }
3532
3533 /********************************************************
3534 *Constellation (b2 ~ b0) : 0~3 => QPSK, 16QAM, 64QAM, 256QAM
3535 *Code Rate (b5 ~ b3) : 0~5 => 1/2, 3/5, 2/3, 3/4, 4/5, 5/6
3536 *GI (b8 ~ b6) : 0~6 => 1/32, 1/16, 1/8, 1/4, 1/128, 19/128, 19/256
3537 *FFT (b11 ~ b9) : 0~7 => 2K, 8K, 4K, 1K, 16K, 32K, 8KE, 32KE
3538 *Preamble(b12) : 0~1 => mixed, not_mixed
3539 *S1_Signaling(b14~b13) : 0~3 => t2_siso, t2_miso, "non_t2, reserved
3540 *pilot_pattern(b18~b15) : 0~8 => PP1, PP2, PP3, PP4, PP5, PP6, PP7, PP8
3541 *BW_Extend(b19) : 0~1 => normal, extension
3542 *PAPR(b22~b20) : 0~4 => none, ace, tr, tr_and_ace, reserved
3543 ********************************/
INTERN_DVBT2_Show_Modulation_info(void)3544 MS_BOOL INTERN_DVBT2_Show_Modulation_info(void)
3545 {
3546 MS_BOOL bRet = TRUE;
3547 MS_U16 u16Data = 0;
3548
3549 char* cConStr[] = {"qpsk", "16qam", "64qam", "256qam"};
3550 char* cCRStr[] = {"1_2", "3_5", "2_3", "3_4", "4_5", "5_6"};
3551 char* cGIStr[] = {"1_32", "1_16", "1_8", "1_4", "1_128", "19_128", "19_256"};
3552 char* cFFTStr[] = {"2k", "8k", "4k", "1k", "16k", "32k", "8k", "32k"};
3553 char* cPreAStr[] = {"mixed", "not_mixed"};
3554 char* cS1SStr[] = {"t2_siso", "t2_miso", "non_t2", "reserved"};
3555 char* cPPSStr[] = {"PP1", "PP2", "PP3", "PP4", "PP5", "PP6", "PP7", "PP8", "reserved"};
3556 char* cBWStr[] = {"normal", "extension"};
3557 char* cPAPRStr[] = {"none", "ace", "tr", "tr_and_ace", "reserved"};
3558
3559 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
3560 {
3561
3562 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_MODUL_MODE) == FALSE)
3563 {
3564 printf("T2_MODUL_MODE Error!\n");
3565 bRet = FALSE;
3566 }
3567 u16Data &= 0x07;
3568 //*L1_Info = (MS_U64)(u16Data);
3569 printf("T2 Constellation:%s\n", cConStr[u16Data]);
3570
3571 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_CODE_RATE) == FALSE)
3572 {
3573 printf(("T2_CODE_RATE Error!\n"));
3574 bRet = FALSE;
3575 }
3576 u16Data &= 0x07;
3577 //*L1_Info |= (MS_U64)(u16Data << 3);
3578 printf("T2 Code Rate:%s\n", cCRStr[u16Data]);
3579
3580 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_GUARD_INTERVAL) == FALSE)
3581 {
3582 printf("T2_GUARD_INTERVAL Error!\n");
3583 bRet = FALSE;
3584 }
3585 u16Data &= 0x07;
3586 //*L1_Info |= (MS_U64)(u16Data << 6);
3587 printf("T2 GI:%s\n", cGIStr[u16Data]);
3588
3589 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_FFT_VALUE) == FALSE)
3590 {
3591 printf("T2_FFT_VALUE Error!\n");
3592 bRet = FALSE;
3593 }
3594 u16Data &= 0x07;
3595 //*L1_Info |= (MS_U64)(u16Data << 9);
3596 printf("T2 FFT:%s\n", cFFTStr[u16Data]);
3597
3598 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PREAMBLE) == FALSE)
3599 {
3600 printf("T2_PREAMBLE Error!\n");
3601 bRet = FALSE;
3602 }
3603 u16Data &= 0x01;
3604 //*L1_Info |= (MS_U64)(u16Data << 12);
3605 printf("Preamble:%s\n", cPreAStr[u16Data]);
3606
3607 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_S1_SIGNALLING) == FALSE)
3608 {
3609 printf("T2_S1_SIGNALLING Error!\n");
3610 bRet = FALSE;
3611 }
3612 u16Data &= 0x03;
3613 if (u16Data > 2)
3614 u16Data = 3;
3615 //*L1_Info |= (MS_U64)(u16Data << 13);
3616 printf("S1 Signalling:%s\n", cS1SStr[u16Data]);
3617
3618 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PILOT_PATTERN) == FALSE)
3619 {
3620 printf("T2_PILOT_PATTERN Error!\n");
3621 bRet = FALSE;
3622 }
3623 u16Data &= 0x0F;
3624 if (u16Data > 7)
3625 u16Data = 8;
3626 //*L1_Info |= (MS_U64)(u16Data << 15);
3627 printf("PilotPattern:%s\n", cPPSStr[u16Data]);
3628
3629 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_BW_EXT) == FALSE)
3630 {
3631 printf("T2_BW_EXT Error!\n");
3632 bRet = FALSE;
3633 }
3634 u16Data &= 0x01;
3635 //*L1_Info |= (MS_U64)(u16Data << 19);
3636 printf("BW EXT:%s\n", cBWStr[u16Data]);
3637
3638 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_PAPR_REDUCTION) == FALSE)
3639 {
3640 printf("T2_PAPR_REDUCTION Error!\n");
3641 bRet = FALSE;
3642 }
3643 u16Data &= 0x07;
3644 if (u16Data > 3)
3645 u16Data = 4;
3646 //*L1_Info |= (MS_U64)(u16Data << 20);
3647 printf("T2 PAPR:%s\n", cPAPRStr[u16Data]);
3648
3649 if (INTERN_DVBT2_Get_L1_Parameter(&u16Data, T2_OFDM_SYMBOLS_PER_FRAME) == FALSE)
3650 {
3651 printf("T2_OFDM_SYMBOLS_PER_FRAME Error!\n");
3652 bRet = FALSE;
3653 }
3654 u16Data &= 0xFFF;
3655 //*L1_Info |= (MS_U64)(u16Data << 23);
3656 printf("T2 OFDM Symbols:%u\n", u16Data);
3657 }
3658 else
3659 {
3660 printf("INVALID\n");
3661 return FALSE;
3662 }
3663
3664 return bRet;
3665
3666 }
3667
3668
INTERN_DVBT2_Show_BER_PacketErr(void)3669 void INTERN_DVBT2_Show_BER_PacketErr(void)
3670 {
3671 // float f_ber = 0;
3672 MS_U16 packetErr = 0;
3673 // INTERN_DVBT2_GetPostLdpcBer(&f_ber);
3674 INTERN_DVBT2_GetPacketErr(&packetErr);
3675
3676 // printf("[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
3677 return;
3678 }
3679
INTERN_DVBT2_Show_Lock_Info(void)3680 MS_BOOL INTERN_DVBT2_Show_Lock_Info(void)
3681 {
3682
3683 printf("[dvbt]INTERN_DVBT2_Show_Lock_Info not implement!!!\n");
3684 return false;
3685 }
3686
3687
INTERN_DVBT2_Show_Demod_Info(void)3688 MS_BOOL INTERN_DVBT2_Show_Demod_Info(void)
3689 {
3690 MS_U8 demod_state = 0;
3691 MS_BOOL status = true;
3692 static MS_U8 counter = 0;
3693
3694 INTERN_DVBT2_get_demod_state(&demod_state);
3695
3696 printf("==========[dvbt]state=%d\n",demod_state);
3697 if (demod_state < 5)
3698 {
3699 INTERN_DVBT2_Show_Demod_Version();
3700 INTERN_DVBT2_Show_AGC_Info();
3701 INTERN_DVBT2_Show_ACI_CI();
3702 }
3703 else if(demod_state < 8)
3704 {
3705 INTERN_DVBT2_Show_Demod_Version();
3706 INTERN_DVBT2_Show_AGC_Info();
3707 INTERN_DVBT2_Show_ACI_CI();
3708 INTERN_DVBT2_Show_ChannelLength();
3709 INTERN_DVBT2_Get_CFO();
3710 INTERN_DVBT2_Get_SFO();
3711 INTERN_DVBT2_Show_td_coeff();
3712 }
3713 else if(demod_state < 11)
3714 {
3715 INTERN_DVBT2_Show_Demod_Version();
3716 INTERN_DVBT2_Show_AGC_Info();
3717 INTERN_DVBT2_Show_ACI_CI();
3718 INTERN_DVBT2_Show_ChannelLength();
3719 INTERN_DVBT2_Get_CFO();
3720 INTERN_DVBT2_Get_SFO();
3721 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3722 INTERN_DVBT2_Get_SYA_status();
3723 INTERN_DVBT2_Show_td_coeff();
3724 }
3725 else if((demod_state == 11) && ((counter%4) == 0))
3726 {
3727 INTERN_DVBT2_Show_Demod_Version();
3728 INTERN_DVBT2_Show_AGC_Info();
3729 INTERN_DVBT2_Show_ACI_CI();
3730 INTERN_DVBT2_Show_ChannelLength();
3731 INTERN_DVBT2_Get_CFO();
3732 INTERN_DVBT2_Get_SFO();
3733 INTERN_DVBT2_Show_FD_CH_LEN_S_SEL();
3734 INTERN_DVBT2_Get_SYA_status();
3735 INTERN_DVBT2_Show_td_coeff();
3736 INTERN_DVBT2_Show_Modulation_info();
3737 INTERN_DVBT2_Show_BER_PacketErr();
3738 }
3739 else
3740 status = false;
3741
3742 printf("===========================\n");
3743 counter++;
3744
3745 return status;
3746 }
3747 #endif