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95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102
103 #define _INTERN_DVBT_C_
104 #ifdef MSOS_TYPE_LINUX
105 #include <math.h>
106 #endif
107 #include "MsCommon.h"
108 #include "MsIRQ.h"
109 #include "MsOS.h"
110 //#include "apiPWS.h"
111
112 #include "MsTypes.h"
113 #include "drvBDMA.h"
114 //#include "drvIIC.h"
115 //#include "msAPI_Tuner.h"
116 //#include "msAPI_MIU.h"
117 //#include "BinInfo.h"
118 //#include "halVif.h"
119 #include "drvDMD_INTERN_DVBT.h"
120 #include "halDMD_INTERN_DVBT.h"
121 #include "halDMD_INTERN_common.h"
122 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
123 #include "InfoBlock.h"
124 #endif
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 #include "ULog.h"
129 #define TEST_EMBEDED_DEMOD 0
130 //U8 load_data_variable=1;
131 //-----------------------------------------------------------------------
132 #define BIN_ID_INTERN_DVBT_DEMOD BIN_ID_INTERN_DVBT
133
134 #define TDE_REG_BASE 0x2400UL
135 #define DIV_REG_BASE 0x2500UL
136 #define TR_REG_BASE 0x2600UL
137 #define FTN_REG_BASE 0x2700UL
138 #define FTNEXT_REG_BASE 0x2800UL
139
140
141
142 #if 0//ENABLE_SCAN_ONELINE_MSG
143 #define DBG_INTERN_DVBT_ONELINE(x) x
144 #else
145 #define DBG_INTERN_DVBT_ONELINE(x) // x
146 #endif
147
148 #ifdef MS_DEBUG
149 #define DBG_INTERN_DVBT(x) x
150 #define DBG_GET_SIGNAL(x) x
151 #define DBG_INTERN_DVBT_TIME(x) x
152 #define DBG_INTERN_DVBT_LOCK(x) x
153 #else
154 #define DBG_INTERN_DVBT(x) //x
155 #define DBG_GET_SIGNAL(x) //x
156 #define DBG_INTERN_DVBT_TIME(x) // x
157 #define DBG_INTERN_DVBT_LOCK(x) //x
158 #endif
159 #define DBG_DUMP_LOAD_DSP_TIME 0
160
161 #define INTERN_DVBT_TS_SERIAL_INVERSION 0
162 #define INTERN_DVBT_TS_PARALLEL_INVERSION 1
163 #define INTERN_DVBT_DTV_DRIVING_LEVEL 1
164
165 /*bryan temp close*/
166 #define INTERN_DVBT_INTERNAL_DEBUG 0
167
168 #define SIGNAL_LEVEL_OFFSET 0.00
169 #define TAKEOVERPOINT -59.0
170 #define TAKEOVERRANGE 0.5
171 #define LOG10_OFFSET -0.21
172 #define INTERN_DVBT_USE_SAR_3_ENABLE 0
173 #define INTERN_DVBT_GET_TIME msAPI_Timer_GetTime0()
174
175
176 #if 0//(FRONTEND_TUNER_TYPE==MSTAR_AVATAR2)
177 #define TUNER_VPP 2
178 #define IF_AGC_VPP 2
179 #else
180 #define TUNER_VPP 1
181 #define IF_AGC_VPP 2
182 #endif
183
184 #if (TUNER_VPP == 1)
185 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/5.0
186 #elif (TUNER_VPP == 2) // For Avatar tuner,ADC peak to peak voltage is 1 V
187 #define ADC_CH_I_PGA_GAIN_CTRL 0x5 // gain = 14.0/14.0
188 #endif
189
190 /*BEG INTERN_DVBT_DSPREG_TABLE*/
191 #define D_DMD_DVBT_PARAM_VERSION 0x01
192 #define D_DMD_DVBT_OP_AUTO_SCAN_MODE_EN 0x01 // 0 for normal channel change, 1 for auto scanning
193 #define D_DMD_DVBT_OP_RFAGC_EN 0x00
194 #define D_DMD_DVBT_OP_HUMDET_EN 0x01
195 #define D_DMD_DVBT_OP_AUTO_RF_MAX_EN 0x00
196 #define D_DMD_DVBT_OP_DCR_EN 0x01
197 #define D_DMD_DVBT_OP_IIS_EN 0x01
198 #define D_DMD_DVBT_OP_IQB_EN 0x00
199 #define D_DMD_DVBT_OP_AUTO_IQ_SWAP_EN 0x01
200 #define D_DMD_DVBT_OP_ACI_EN 0x01
201 #define D_DMD_DVBT_OP_CCI_EN 0x01
202 #define D_DMD_DVBT_OP_FIX_MODE_CP_EN 0x00
203 #define D_DMD_DVBT_OP_FIX_TPS_EN 0x00
204 #define D_DMD_DVBT_CFG_BW 0x00 // BW: 0..3 for 5M, 6M, 7M, 8M Channel Allocation
205 #define D_DMD_DVBT_CFG_MODE 0x00 // 0, 1, 2 for 2K, 8K, 4K OFDM subcarriers
206 #define D_DMD_DVBT_CFG_CP 0x00 // 0..3 for Intervals of 1/32, 1/16, 1/8, 1/4
207 #define D_DMD_DVBT_CFG_LP_SEL 0x00 // HP or LP selection, 0:HP, 1:LP
208 #define D_DMD_DVBT_CFG_CSTL 0x02 // constellation, 0, 1, 2 for QPSK, 16QAM, 64QAM
209 #define D_DMD_DVBT_CFG_HIER 0x00 // 0..7 for None, Alpha = 1, 2, 4, or add 4 for indepth interleaver
210 #define D_DMD_DVBT_CFG_HPCR 0x01 // HP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
211 #define D_DMD_DVBT_CFG_LPCR 0x02 // LP CR, 0..4 for Rates of 1/2, 2/3, 3/4, 5/6, 7/8
212 #define D_DMD_DVBT_CFG_RFMAX 0x01 // work for RF AGC external mode enable.
213 #define D_DMD_DVBT_CFG_ZIF 0x00 // 0 for IF, 1 for ZIF structure
214 #define D_DMD_DVBT_CFG_RSSI 0x00 // 0 for NOT using RSSI, 1 for using RSSI
215 #define D_DMD_DVBT_CFG_RFAGC_REF 0x64
216 #define D_DMD_DVBT_CFG_IFAGC_REF_2K 0x4B //0xB0 YP for sensitivity test
217 #define D_DMD_DVBT_CFG_IFAGC_REF_8K 0x4B
218 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI 0x4B
219 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS 0xA0
220 #define D_DMD_DVBT_CFG_IFAGC_REF_2K_H 0x03 //0xB0 YP for sensitivity test
221 #define D_DMD_DVBT_CFG_IFAGC_REF_8K_H 0x03
222 #define D_DMD_DVBT_CFG_IFAGC_REF_ACI_H 0x00
223 #define D_DMD_DVBT_CFG_IFAGC_REF_IIS_H 0x00
224
225 #define D_DMD_DVBT_CFG_FC_L 0x20 // 9394, Fc = Fs - IF = 45474 - 36167 = 9307
226 #define D_DMD_DVBT_CFG_FC_H 0x4E
227 #define D_DMD_DVBT_CFG_FS_L 0xC0 // 45474, Fs = 45.4738MHz
228 #define D_DMD_DVBT_CFG_FS_H 0x5D
229 #define D_DMD_DVBT_CFG_IQ_SWAP 0x00 // 1: iq swap, 0: non iq swap
230
231 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_L 0xf0
232 #define D_DMD_DVBT_CFG_8M_DACI_DET_TH_H 0x0a
233 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_L 0xc4
234 #define D_DMD_DVBT_CFG_8M_ANM1_DET_TH_H 0x09
235 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_L 0xc4
236 #define D_DMD_DVBT_CFG_8M_ANP1_DET_TH_H 0x09
237 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_L 0xf0
238 #define D_DMD_DVBT_CFG_7M_DACI_DET_TH_H 0x0a
239 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_L 0xc4
240 #define D_DMD_DVBT_CFG_7M_ANM1_DET_TH_H 0x09
241 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_L 0xc4
242 #define D_DMD_DVBT_CFG_7M_ANP1_DET_TH_H 0x09
243
244 #define D_DMD_DVBT_CFG_CCI 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
245 #define D_DMD_DVBT_CFG_ICFO_RANGE 0x01 // ICFOE search range: 0: narrow , 1: medium, 2:large range
246 #define D_DMD_DVBT_CFG_TS_SERIAL 0x01 // 1: serial mode, 0: parallel mode.
247 //#define DMD_DVBT_CFG_TS_PARALLEL 0x00 // 1: serial mode, 0: parallel mode.
248 #if (INTERN_DVBT_TS_SERIAL_INVERSION)
249 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x01 // Inversion
250 #else
251 #define D_DMD_DVBT_CFG_TS_CLK_INV 0x00 // non-Inversion
252 #endif
253 #define D_DMD_DVBT_CFG_TS_DATA_SWAP 0x00 // TS data reverse, 1: reverse, 0: non-reverse.
254 //#define DMD_DVBT_CHECKSUM 0x00
255 /*END INTERN_DVBT_DSPREG_TABLE*/
256 #define DVBT_FS 45474 // 24000
257 #define FC_H 0x4E // 40474, Fc = Fs - IF = 45474 - 5000 = 40474 -> 0323 update
258 #define FC_L 0x20 // 0323 jason
259 #define FS_H ((DVBT_FS>>8)&0xFF) // FS=24000, Fs = 24MHz
260 #define FS_L (DVBT_FS&0xFF) // andy 2009-8-18 ¿ÀÈÄ 10:22:29 0x9E
261 #define SET_ZIF 0x00
262 #define IQB_EN 0x00
263
264 #define FORCE_MC 0x00 //0: auto 1: Force mode-cp
265 #define FORCE_TPS 0x00 //0: auto 1: Force TPS
266 #define AUTO_SCAN 0x00 // Auto Scan - 0:channel change, 1:auto-scan
267 #define CSTL 0x02 //0:QPSK 1:16 2: 64
268 #define HIER 0x00
269 #define HPCR 0x01 // HP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
270 #define LPCR 0x01 // LP_CR 0:1/2, 1:2/3, 2: 3/4, 3: 5/6, 4:7/8
271 #define FFT_MODE 0x01 // FFT mode - 0:2K, 1:8K
272 #define CP 0x00 // CP - 0:1/32, 1/16, 1/8, 1/4
273 #define LP_SEL 0x00 // LP select
274 #define IQ_SWAP 0x00 //0x01
275 #define PAL_I 0x00 // PAL_I: 0: Non-Pal-I CCI, 1: Pal-I CCI (for UK)
276 #define CFO_RANGE 0x01 //0: 500KHz 1: 900KHz
277 #define CFO_RANGE_TW 0x00 //0: 500KHz 1: 900KHz
278 #define TS_SER 0
279 #define TS_INV 0
280 #define FIF_H (MS_U8)(( (((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))>>8)
281 #define FIF_L (MS_U8)(( ((MS_U16)FS_H<<8)|FS_L) - (((MS_U16)FC_H<<8)|FC_L))
282 #define IF_INV_PWM 0x00
283 #define T_LOWIF 1
284
285 MS_U8 INTERN_DVBT_DSPREG[] =
286 {
287 0x00, 0x00, 0x00, D_DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01, 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, SET_ZIF, //00-0F
288 0x00, T_LOWIF, 0x00, FS_L, FS_H, FIF_L, FIF_H, FC_L, FC_H, 0x03, FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, //10-1F
289 LPCR, IQ_SWAP, 0x00, PAL_I, CFO_RANGE, D_DMD_DVBT_CFG_RFAGC_REF, D_DMD_DVBT_CFG_IFAGC_REF_2K, D_DMD_DVBT_CFG_IFAGC_REF_8K, D_DMD_DVBT_CFG_IFAGC_REF_ACI, D_DMD_DVBT_CFG_IFAGC_REF_IIS, //20-29
290 D_DMD_DVBT_CFG_IFAGC_REF_2K_H, D_DMD_DVBT_CFG_IFAGC_REF_8K_H, D_DMD_DVBT_CFG_IFAGC_REF_ACI_H, D_DMD_DVBT_CFG_IFAGC_REF_IIS_H, TS_SER, TS_INV, //2A-2F
291 0x00, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0xf0, 0x0a, 0xc4, 0x09, 0xc4, 0x09, 0x00, 0xd0, 0x80, //30-3F
292 0x7f, 0xa0, 0x23, 0x05, 0x05, 0x40, 0x34, 0x06, 0x00, 0x00, 0x00, 0x00, 0x45, 0x00, 0x65, 0x00, //40-4F
293 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //50-5F
294 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x33, 0x33, 0x01, 0x03, //60-6F
295 0x03, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //70-7E
296 /*
297 // 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07
298 0x00, 0x01, DMD_DVBT_OP_DCR_EN, 0x01, 0x01, 0x01, IQB_EN, 0x01,
299 // 0x08 0x09 0x0a 0x0b 0x0c 0x0d 0x0e 0xf
300 0x00, 0x00, FORCE_MC, FORCE_TPS, AUTO_SCAN, 0x00, 0x00, 0x00,
301 // 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17
302 0x00, SET_ZIF, 0xff, FC_L, FC_H, FS_L, FS_H, 0x03,
303 // 0x18 0x19 0x1a 0x1b 0x1c 0x1d 0x1e 0x1f
304 FFT_MODE, CP, LP_SEL, CSTL, HIER, HPCR, LPCR, IQ_SWAP,
305 // 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27
306 0x00, PAL_I, CFO_RANGE, DMD_DVBT_CFG_RFAGC_REF, DMD_DVBT_CFG_IFAGC_REF_2K, DMD_DVBT_CFG_IFAGC_REF_8K, DMD_DVBT_CFG_IFAGC_REF_ACI, DMD_DVBT_CFG_IFAGC_REF_IIS,
307 // 0x28 0x29 0x2a 0x2b 0x2c 0x2d 0x2e 0x2f
308 0x9A, 0x01, TS_SER, 0x00, TS_INV, 0x00, 0x00, 0xC8,
309 // 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F
310 0x00, 0xC8, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, T_LOWIF, 0x47, 0x8D, 0x01, 0x00, 0x00, 0x00, 0x00,
311 */
312 };
313 /*END INTERN_DVBT_DSPREG_TABLE*/
314 //-----------------------------------------------------------------------
315 /****************************************************************
316 *Local Variables *
317 ****************************************************************/
318 static MS_BOOL bFECLock=0;
319 static MS_BOOL bTPSLock = 0;
320 static MS_U32 u32ChkScanTimeStart = 0;
321 static MS_U32 u32FecFirstLockTime=0;
322 static MS_U32 u32FecLastLockTime=0;
323 //bryan temp mark
324 #if(0)
325 static float fViterbiBerFiltered=-1;
326 #endif
327 //Global Variables
328 S_CMDPKTREG gsCmdPacket;
329 //U8 gCalIdacCh0, gCalIdacCh1;
330
331 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
332 MS_U8 INTERN_DVBT_table[] = {
333 #include "fwDMD_INTERN_DVBT.dat"
334 };
335
336 #endif
337
338 /*bryan temp mark*/
339 #if(0)
340 static DMD_SSI_DBM_NORDIGP1 dvbt_ssi_dbm_nordigp1[] =
341 {
342 { _QPSK , _CR1Y2, -93},
343 { _QPSK , _CR2Y3, -91},
344 { _QPSK , _CR3Y4, -90},
345 { _QPSK , _CR5Y6, -89},
346 { _QPSK , _CR7Y8, -88},
347
348 { _16QAM , _CR1Y2, -87},
349 { _16QAM , _CR2Y3, -85},
350 { _16QAM , _CR3Y4, -84},
351 { _16QAM , _CR5Y6, -83},
352 { _16QAM , _CR7Y8, -82},
353
354 { _64QAM , _CR1Y2, -82},
355 { _64QAM , _CR2Y3, -80},
356 { _64QAM , _CR3Y4, -78},
357 { _64QAM , _CR5Y6, -77},
358 { _64QAM , _CR7Y8, -76},
359 { _UNKNOW_QAM , _UNKNOW_CR, 0.0},
360 };
361 #endif
362
363 /*bryan temp mark*/
364 #if(0)
365 static void INTERN_DVBT_SignalQualityReset(void);
366 #endif
367 MS_BOOL INTERN_DVBT_Show_Demod_Version(void);
368
369 #if(0)
INTERN_DVBT_SignalQualityReset(void)370 static void INTERN_DVBT_SignalQualityReset(void)
371 {
372 u32FecFirstLockTime=0;
373 fViterbiBerFiltered=-1;
374 }
375 #endif
376
INTERN_DVBT_DSPReg_Init(const MS_U8 * u8DVBT_DSPReg,MS_U8 u8Size)377 MS_BOOL INTERN_DVBT_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size)
378 {
379 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
380 MS_BOOL status = TRUE;
381 MS_U16 u16DspAddr = 0;
382
383 DBG_INTERN_DVBT(ULOGD("DEMOD","INTERN_DVBT_DSPReg_Init\n"));
384
385 for (idx = 0; idx<sizeof(INTERN_DVBT_DSPREG); idx++)
386 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBT_DSPREG[idx]);
387
388 if (u8DVBT_DSPReg != NULL)
389 {
390 /*temp solution until new dsp table applied.*/
391 // if (INTERN_DVBT_DSPREG[E_DMD_DVBT_PARAM_VERSION] == u8DVBT_DSPReg[0])
392 if (u8DVBT_DSPReg[0] >= 1)
393 {
394 u8DVBT_DSPReg+=2;
395 for (idx = 0; idx<u8Size; idx++)
396 {
397 u16DspAddr = *u8DVBT_DSPReg;
398 u8DVBT_DSPReg++;
399 u16DspAddr = (u16DspAddr) + ((*u8DVBT_DSPReg)<<8);
400 u8DVBT_DSPReg++;
401 u8Mask = *u8DVBT_DSPReg;
402 u8DVBT_DSPReg++;
403 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
404 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBT_DSPReg) & (u8Mask));
405 u8DVBT_DSPReg++;
406 DBG_INTERN_DVBT(ULOGD("DEMOD","DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
407 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
408 }
409 }
410 else
411 {
412 ULOGD("DEMOD","FATAL: parameter version incorrect\n");
413 }
414 }
415
416 return status;
417 }
418
419 /***********************************************************************************
420 Subject: Command Packet Interface
421 Function: INTERN_DVBT_Cmd_Packet_Send
422 Parmeter:
423 Return: MS_BOOL
424 Remark:
425 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)426 MS_BOOL INTERN_DVBT_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
427 {
428 MS_U8 status = true, indx;
429 MS_U8 reg_val=0, timeout = 0;
430 return TRUE;
431 //MsOS_ObtainMutex(_s32_Demod_DVBT_Mutex, MSOS_WAIT_FOREVER);
432 // ==== Command Phase ===================
433 DBG_INTERN_DVBT(ULOGD("DEMOD","--->INTERN_DVBT (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
434 pCmdPacket->param[0],pCmdPacket->param[1],
435 pCmdPacket->param[2],pCmdPacket->param[3],
436 pCmdPacket->param[4],pCmdPacket->param[5] ));
437
438 // wait _BIT_END clear
439 do
440 {
441 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
442 if((reg_val & _BIT_END) != _BIT_END)
443 {
444 break;
445 }
446 MsOS_DelayTask(5);
447 if (timeout++ > 200)
448 {
449 ULOGD("DEMOD","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n");
450 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
451 return false;
452 }
453 } while (1);
454
455 // set cmd_3:0 and _BIT_START
456 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
457 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
458 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
459
460
461 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
462 // wait _BIT_START clear
463 do
464 {
465 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
466 if((reg_val & _BIT_START) != _BIT_START)
467 {
468 break;
469 }
470 MsOS_DelayTask(5);
471 if (timeout++ > 200)
472 {
473 ULOGD("DEMOD","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n");
474 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
475 return false;
476 }
477 } while (1);
478
479 // ==== Data Phase ======================
480
481 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
482
483 for (indx = 0; indx < param_cnt; indx++)
484 {
485 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
486 //DBG_INTERN_DVBT(ULOGD("DEMOD","demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
487
488 // set param[indx] and _BIT_DRQ
489 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
490 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
491 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
492
493 // wait _BIT_DRQ clear
494 do
495 {
496 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
497 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
498 {
499 break;
500 }
501 MsOS_DelayTask(5);
502 if (timeout++ > 200)
503 {
504 ULOGD("DEMOD","---> INTERN_DVBT_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n");
505 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
506 return false;
507 }
508 } while (1);
509 }
510
511 // ==== End Phase =======================
512
513 // set _BIT_END to finish command
514 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
515 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
516 //MsOS_ReleaseMutex(_s32_Demod_DVBT_Mutex);
517 return status;
518 }
519
520
521 /***********************************************************************************
522 Subject: Command Packet Interface
523 Function: INTERN_DVBT_Cmd_Packet_Exe_Check
524 Parmeter:
525 Return: MS_BOOL
526 Remark:
527 ************************************************************************************/
INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)528 MS_BOOL INTERN_DVBT_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
529 {
530 return TRUE;
531 }
532
533 /***********************************************************************************
534 Subject: SoftStop
535 Function: INTERN_DVBT_SoftStop
536 Parmeter:
537 Return: MS_BOOL
538 Remark:
539 ************************************************************************************/
540
INTERN_DVBT_SoftStop(void)541 MS_BOOL INTERN_DVBT_SoftStop ( void )
542 {
543 #if 1
544 MS_U16 u8WaitCnt=0;
545
546 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
547 {
548 ULOGD("DEMOD",">> MB Busy!\n");
549 return FALSE;
550 }
551
552 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
553
554 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
555 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
556
557 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
558 {
559 #if TEST_EMBEDED_DEMOD
560 MsOS_DelayTask(1); // << Ken 20090629
561 #endif
562 if (u8WaitCnt++ >= 0x7FFF)
563 {
564 ULOGD("DEMOD",">> DVBT SoftStop Fail!\n");
565 return FALSE;
566 }
567 }
568
569 //HAL_DMD_RIU_WriteByte(0x103480, 0x01); // reset VD_MCU
570 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
571 #endif
572 return TRUE;
573 }
574
575
576 /***********************************************************************************
577 Subject: Reset
578 Function: INTERN_DVBT_Reset
579 Parmeter:
580 Return: MS_BOOL
581 Remark:
582 ************************************************************************************/
583 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
INTERN_DVBT_Reset(void)584 MS_BOOL INTERN_DVBT_Reset ( void )
585 {
586 DBG_INTERN_DVBT(ULOGD("DEMOD"," @INTERN_DVBT_reset\n"));
587
588 DBG_INTERN_DVBT_TIME(ULOGD("DEMOD","INTERN_DVBT_Reset, t = %ld\n",MsOS_GetSystemTime()));
589
590 // INTERN_DVBT_SoftStop();
591
592
593 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
594 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x72); // reset DVB-T
595 MsOS_DelayTask(5);
596 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
597 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x2002, 0x52);
598 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
599 MsOS_DelayTask(5);
600
601 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
602 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
603
604 bFECLock = FALSE;
605 bTPSLock = FALSE;
606 u32ChkScanTimeStart = MsOS_GetSystemTime();
607 return TRUE;
608 }
609
610 /***********************************************************************************
611 Subject: Exit
612 Function: INTERN_DVBT_Exit
613 Parmeter:
614 Return: MS_BOOL
615 Remark:
616 ************************************************************************************/
INTERN_DVBT_Exit(void)617 MS_BOOL INTERN_DVBT_Exit ( void )
618 {
619 return INTERN_DVBT_SoftStop();
620 }
621
622 /***********************************************************************************
623 Subject: Load DSP code to chip
624 Function: INTERN_DVBT_LoadDSPCode
625 Parmeter:
626 Return: MS_BOOL
627 Remark:
628 ************************************************************************************/
INTERN_DVBT_LoadDSPCode(void)629 static MS_BOOL INTERN_DVBT_LoadDSPCode(void)
630 {
631 MS_U8 udata = 0x00;
632 MS_U16 i;
633 MS_U16 fail_cnt=0;
634
635 #if (DBG_DUMP_LOAD_DSP_TIME==1)
636 MS_U32 u32Time;
637 #endif
638
639
640 #ifndef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
641 BININFO BinInfo;
642 MS_BOOL bResult;
643 MS_U32 u32GEAddr;
644 MS_U8 Data;
645 MS_S8 op;
646 MS_U32 srcaddr;
647 MS_U32 len;
648 MS_U32 SizeBy4K;
649 MS_U16 u16Counter=0;
650 MS_U8 *pU8Data;
651 #endif
652
653 #if 0
654 if(HAL_DMD_RIU_ReadByte(0x101E3E))
655 {
656 ULOGD("DEMOD","Warring! Reg[0x101E3E]=%d\n", HAL_DMD_RIU_ReadByte(0x101E3E));
657 return FALSE;
658 }
659 #endif
660
661 // MDrv_Sys_DisableWatchDog();
662
663
664 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
665 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
666 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
667 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
668 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
669 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
670
671 //// Load code thru VDMCU_IF ////
672 DBG_INTERN_DVBT(ULOGD("DEMOD",">Load Code...\n"));
673 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
674 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
675 {
676 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBT_table[i]); // write data to VD MCU 51 code sram
677 }
678 #else
679 BinInfo.B_ID = BIN_ID_INTERN_DVBT_DEMOD;
680 msAPI_MIU_Get_BinInfo(&BinInfo, &bResult);
681 if ( bResult != PASS )
682 {
683 return FALSE;
684 }
685 //ULOGD("DEMOD","\t DEMOD_MEM_ADR =%08LX\n", ((DEMOD_MEM_ADR & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
686
687 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
688 InfoBlock_Flash_2_Checking_Start(&BinInfo);
689 #endif
690
691 #if OBA2
692 MApi_BDMA_CopyFromResource(BinInfo.B_FAddr, _PA2VA((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8));
693 #else
694 msAPI_MIU_Copy(BinInfo.B_FAddr, ((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)), MemAlign(BinInfo.B_Len, 8), MIU_FLASH2SDRAM);
695 #endif
696
697 #ifdef SUPPORT_AP_BIN_IN_FLASH_2
698 InfoBlock_Flash_2_Checking_End(&BinInfo);
699 #endif
700
701 //W1BaseAddr = MDrv_Sys_GetXdataWindow1Base();
702
703 //bryan temp mark
704 //SizeBy4K=BinInfo.B_Len/0x1000;
705 SizeBy4K=BinInfo.B_Len>>12; //deivde to 4096
706
707 //ULOGD("DEMOD","\t RRR: SizeBy4K=%d (L=%d)\n", SizeBy4K,BinInfo.B_Len);
708
709 #if (DBG_DUMP_LOAD_DSP_TIME==1)
710 u32Time = msAPI_Timer_GetTime0();
711 #endif
712
713 u32GEAddr = _PA2VA(((DEMOD_MEM_MEMORY_TYPE & MIU1) ? (DEMOD_MEM_ADR | MIU_INTERVAL) : (DEMOD_MEM_ADR)));
714
715 for (i=0;i<=SizeBy4K;i++)
716 {
717 if(i==SizeBy4K)
718 len=BinInfo.B_Len%0x1000;
719 else
720 len=0x1000;
721
722 srcaddr = u32GEAddr+(0x1000*i);
723 //ULOGD("DEMOD","\t i = %08X\n", i);
724 //ULOGD("DEMOD","\t len = %08X\n", len);
725 op = 1;
726 u16Counter = 0 ;
727 //ULOGD("DEMOD","\t (B=0x%x)(Src=0x%x)Data =",i,srcaddr);
728 while(len--)
729 {
730 u16Counter ++ ;
731 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
732 //pU8Data = (U8 *)(srcaddr|0x80000000);
733 #if OBA2
734 pU8Data = (U8 *)(srcaddr);
735 #else
736 pU8Data = (U8 *)(srcaddr|0x80000000);
737 #endif
738 Data = *pU8Data;
739
740 #if 0
741 if(u16Counter < 0x100)
742 ULOGD("DEMOD","0x%bx,", Data);
743 #endif
744 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, Data); // write data to VD MCU 51 code sram
745
746 srcaddr += op;
747 }
748 // ULOGD("DEMOD","\n\n\n");
749 }
750
751 #if (DBG_DUMP_LOAD_DSP_TIME==1)
752 ULOGD("DEMOD","------> INTERN_DVBT Load DSP Time: (%lu)\n", msAPI_Timer_DiffTimeFromNow(u32Time)) ;
753 #endif
754
755 #endif
756
757 //// Content verification ////
758 DBG_INTERN_DVBT(ULOGD("DEMOD",">Verify Code...\n"));
759
760 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
761 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
762
763 #ifdef INTERN_DVBT_LOAD_FW_FROM_CODE_MEMORY
764 for ( i = 0; i < sizeof(INTERN_DVBT_table); i++)
765 {
766 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
767 if (udata != INTERN_DVBT_table[i])
768 {
769 ULOGD("DEMOD",">fail add = 0x%x\n", i);
770 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBT_table[i]);
771 ULOGD("DEMOD",">data = 0x%x\n", udata);
772
773 if (fail_cnt++ > 10)
774 {
775 ULOGD("DEMOD",">DVB-T DSP Loadcode fail!");
776 return false;
777 }
778 }
779 }
780 #else
781 for (i=0;i<=SizeBy4K;i++)
782 {
783 if(i==SizeBy4K)
784 len=BinInfo.B_Len%0x1000;
785 else
786 len=0x1000;
787
788 srcaddr = u32GEAddr+(0x1000*i);
789 //ULOGD("DEMOD","\t i = %08LX\n", i);
790 //ULOGD("DEMOD","\t len = %08LX\n", len);
791 op = 1;
792 u16Counter = 0 ;
793 //ULOGD("DEMOD","\t (B=0x%bx)(Src=0x%x)Data =",i,srcaddr);
794 while(len--)
795 {
796 u16Counter ++ ;
797 //ULOGD("DEMOD","file: %s, line: %d\n", __FILE__, __LINE__);
798 //pU8Data = (U8 *)(srcaddr|0x80000000);
799 #if OBA2
800 pU8Data = (U8 *)(srcaddr);
801 #else
802 pU8Data = (U8 *)(srcaddr|0x80000000);
803 #endif
804 Data = *pU8Data;
805
806 #if 0
807 if(u16Counter < 0x100)
808 ULOGD("DEMOD","0x%bx,", Data);
809 #endif
810 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
811 if (udata != Data)
812 {
813 ULOGD("DEMOD",">fail add = 0x%lx\n", (U32)((i*0x1000)+(0x1000-len)));
814 ULOGD("DEMOD",">code = 0x%x\n", Data);
815 ULOGD("DEMOD",">data = 0x%x\n", udata);
816
817 if (fail_cnt++ > 10)
818 {
819 ULOGD("DEMOD",">DVB-T DSP Loadcode fail!");
820 return false;
821 }
822 }
823
824 srcaddr += op;
825 }
826 // ULOGD("DEMOD","\n\n\n");
827 }
828 #endif
829
830 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
831 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
832 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
833 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
834
835 DBG_INTERN_DVBT(ULOGD("DEMOD",">DSP Loadcode done."));
836 //while(load_data_variable);
837
838
839 return TRUE;
840 }
841
842 /***********************************************************************************
843 Subject: DVB-T CLKGEN initialized function
844 Function: INTERN_DVBT_Power_On_Initialization
845 Parmeter:
846 Return: MS_BOOL
847 Remark:
848 ************************************************************************************/
INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)849 void INTERN_DVBT_InitClkgen(MS_BOOL bRFAGCTristateEnable)
850 {
851 HAL_DMD_RIU_WriteByte(0x103c0e,0x00);
852 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
853 HAL_DMD_RIU_WriteByte(0x112003, (HAL_DMD_RIU_ReadByte(0x112003)&(~(BIT(5))))); // Release Ana misc resest
854 // ----------------------------------------------
855 // start demod CLKGEN setting
856 // ----------------------------------------------
857 // *** Set register at CLKGEN1
858 // enable DMD MCU clock "bit[0] set 0"
859 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
860 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
861 // CLK_DMDMCU clock setting
862 // [0] disable clock
863 // [1] invert clock
864 // [4:2]
865 // 000:170 MHz(MPLL_DIV_BUf)
866 // 001:160MHz
867 // 010:144MHz
868 // 011:123MHz
869 // 100:108MHz
870 // 101:mem_clcok
871 // 110:mem_clock div 2
872 // 111:select XTAL
873 HAL_DMD_RIU_WriteByte(0x10331f,0x00);
874 HAL_DMD_RIU_WriteByte(0x10331e,0x10);//0331 patch
875
876 // set parallet ts clock
877 HAL_DMD_RIU_WriteByte(0x103301,0x05);
878 HAL_DMD_RIU_WriteByte(0x103300,0x14);
879
880 // enable atsc, DVBTC ts clock
881 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
882 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
883 HAL_DMD_RIU_WriteByte(0x103309,0x00);
884 HAL_DMD_RIU_WriteByte(0x103308,0x00);
885
886 // enable dvbc adc clock
887 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
888 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
889 HAL_DMD_RIU_WriteByte(0x103315,0x00);
890 HAL_DMD_RIU_WriteByte(0x103314,0x00);
891
892 // Reset TS divider
893 HAL_DMD_RIU_WriteByte(0x103302,0x01);
894 HAL_DMD_RIU_WriteByte(0x103302,0x00);
895
896
897 // enable clk_atsc_adcd_sync
898 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
899 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
900 HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
901 HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
902
903 // enable dvbt inner clock
904 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
905 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h06, 2'b11, 16'h0000);
906 HAL_DMD_RIU_WriteByte(0x111f13,0x00);
907 HAL_DMD_RIU_WriteByte(0x111f12,0x00);
908
909
910
911 // enable dvbt inner clock
912 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
913 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h08, 2'b11, 16'h0000);
914 HAL_DMD_RIU_WriteByte(0x111f21,0x44);
915 HAL_DMD_RIU_WriteByte(0x111f20,0x40);
916
917 // enable dvbc outer clock
918 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
919 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h09, 2'b11, 16'h0000);
920 HAL_DMD_RIU_WriteByte(0x111f23,0x08);
921 HAL_DMD_RIU_WriteByte(0x111f22,0x44);
922
923
924 HAL_DMD_RIU_WriteByte(0x111f25,0x04);
925
926 HAL_DMD_RIU_WriteByte(0x111f29,0x00);
927 HAL_DMD_RIU_WriteByte(0x111f28,0x00);
928
929 HAL_DMD_RIU_WriteByte(0x111f2d,0x00);
930 HAL_DMD_RIU_WriteByte(0x111f2c,0x41);
931
932
933 HAL_DMD_RIU_WriteByte(0x111f2f,0x0c);
934 HAL_DMD_RIU_WriteByte(0x111f2e,0x04);
935
936
937 HAL_DMD_RIU_WriteByte(0x111f31,0x00);
938 HAL_DMD_RIU_WriteByte(0x111f30,0x04);
939
940 HAL_DMD_RIU_WriteByte(0x111f33,0x3c);
941 HAL_DMD_RIU_WriteByte(0x111f32,0x00);
942
943
944 HAL_DMD_RIU_WriteByte(0x111f35,0x10);
945 HAL_DMD_RIU_WriteByte(0x111f34,0x10);
946
947 HAL_DMD_RIU_WriteByte(0x111f37,0x00);
948 HAL_DMD_RIU_WriteByte(0x111f36,0x11);
949
950 HAL_DMD_RIU_WriteByte(0x111f3b,0x00);
951 HAL_DMD_RIU_WriteByte(0x111f3a,0x00);
952
953 HAL_DMD_RIU_WriteByte(0x111f3d,0x0c);
954 HAL_DMD_RIU_WriteByte(0x111f3c,0x04);
955
956 HAL_DMD_RIU_WriteByte(0x111f45,0x04);
957 HAL_DMD_RIU_WriteByte(0x111f44,0x44);
958
959 HAL_DMD_RIU_WriteByte(0x111f69,0x00);
960 HAL_DMD_RIU_WriteByte(0x111f68,0x00);
961
962 HAL_DMD_RIU_WriteByte(0x111f6b,0x00);
963 HAL_DMD_RIU_WriteByte(0x111f6a,0x00);
964
965 HAL_DMD_RIU_WriteByte(0x111f6d,0x00);
966 HAL_DMD_RIU_WriteByte(0x111f6c,0x10);
967
968 HAL_DMD_RIU_WriteByte(0x111f6f,0x0c);
969 HAL_DMD_RIU_WriteByte(0x111f6e,0x40);
970
971 HAL_DMD_RIU_WriteByte(0x111f71,0x00);
972 HAL_DMD_RIU_WriteByte(0x111f70,0x00);
973
974 HAL_DMD_RIU_WriteByte(0x111f73,0x00);
975 HAL_DMD_RIU_WriteByte(0x111f72,0x00);
976
977 HAL_DMD_RIU_WriteByte(0x111f75,0x00);
978 HAL_DMD_RIU_WriteByte(0x111f74,0x00);
979
980 HAL_DMD_RIU_WriteByte(0x111f77,0x00);
981 HAL_DMD_RIU_WriteByte(0x111f76,0x00);
982
983 HAL_DMD_RIU_WriteByte(0x111f79,0x40);
984 HAL_DMD_RIU_WriteByte(0x111f78,0x00);
985
986 HAL_DMD_RIU_WriteByte(0x111f7b,0x00);
987 HAL_DMD_RIU_WriteByte(0x111f7a,0x04);
988
989 HAL_DMD_RIU_WriteByte(0x111f7d,0x00);
990 HAL_DMD_RIU_WriteByte(0x111f7c,0x00);
991
992 HAL_DMD_RIU_WriteByte(0x111f7f,0x40);
993 HAL_DMD_RIU_WriteByte(0x111f7e,0x40);
994
995 HAL_DMD_RIU_WriteByte(0x111fe1,0x04);
996 HAL_DMD_RIU_WriteByte(0x111fe0,0x04);
997
998 HAL_DMD_RIU_WriteByte(0x111ff0,0x04);
999
1000 HAL_DMD_RIU_WriteByte(0x111fe3,0x04);
1001 HAL_DMD_RIU_WriteByte(0x111fe2,0x0c);
1002
1003 HAL_DMD_RIU_WriteByte(0x111fe5,0x00);
1004 HAL_DMD_RIU_WriteByte(0x111fe4,0x00);
1005
1006 HAL_DMD_RIU_WriteByte(0x111fe7,0x00);
1007 HAL_DMD_RIU_WriteByte(0x111fe6,0x00);
1008
1009 HAL_DMD_RIU_WriteByte(0x111fe9,0x04);
1010 HAL_DMD_RIU_WriteByte(0x111fe8,0x0c);
1011
1012 HAL_DMD_RIU_WriteByte(0x111feb,0x88);
1013 HAL_DMD_RIU_WriteByte(0x111fea,0x00);
1014
1015 HAL_DMD_RIU_WriteByte(0x111fed,0x00);
1016 HAL_DMD_RIU_WriteByte(0x111fec,0x08);
1017
1018 HAL_DMD_RIU_WriteByte(0x111fef,0x00);
1019 HAL_DMD_RIU_WriteByte(0x111fee,0x88);
1020
1021 HAL_DMD_RIU_WriteByte(0x15298f,0x00);
1022 HAL_DMD_RIU_WriteByte(0x15298e,0x00);
1023
1024 HAL_DMD_RIU_WriteByte(0x152991,0x00);
1025 HAL_DMD_RIU_WriteByte(0x152990,0x00);
1026 HAL_DMD_RIU_WriteByte(0x152992,0x00);
1027
1028 HAL_DMD_RIU_WriteByte(0x1529e5,0x00);
1029 HAL_DMD_RIU_WriteByte(0x1529e4,0x00);
1030
1031
1032 HAL_DMD_RIU_WriteByte(0x152971,0x10);
1033 HAL_DMD_RIU_WriteByte(0x152970,0x01);
1034
1035 HAL_DMD_RIU_WriteByte(0x111f42,0x04);
1036
1037 // 32+4K xdata sram
1038 //wriu 0x1117e0 0x23
1039 //wriu 0x1117e1 0x21
1040
1041 //wriu 0x1117e4 0x01
1042 //wriu 0x1117e6 0x11
1043 HAL_DMD_RIU_WriteByte(0x1117e0,0x23);
1044 HAL_DMD_RIU_WriteByte(0x1117e1,0x21);
1045 HAL_DMD_RIU_WriteByte(0x1117e4,0x01);
1046 HAL_DMD_RIU_WriteByte(0x1117e6,0x11);
1047
1048 HAL_DMD_RIU_WriteByte(0x101e39,0x03);
1049 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1050 }
1051
1052 /***********************************************************************************
1053 Subject: Power on initialized function
1054 Function: INTERN_DVBT_Power_On_Initialization
1055 Parmeter:
1056 Return: MS_BOOL
1057 Remark:
1058 ************************************************************************************/
1059
INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBT_DSPRegInitExt,MS_U8 u8DMD_DVBT_DSPRegInitSize)1060 MS_BOOL INTERN_DVBT_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize)
1061 {
1062 MS_U16 status = true;
1063 MS_U8 cData = 0;
1064 //U8 cal_done;
1065 DBG_INTERN_DVBT(ULOGD("DEMOD","INTERN_DVBT_Power_On_Initialization\n"));
1066
1067 #if defined(PWS_ENABLE)
1068 Mapi_PWS_Stop_VDMCU();
1069 #endif
1070
1071 INTERN_DVBT_InitClkgen(bRFAGCTristateEnable);
1072 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);
1073 //// Firmware download //////////
1074 DBG_INTERN_DVBT(ULOGD("DEMOD","INTERN_DVBT Load DSP...\n"));
1075 //MsOS_DelayTask(100);
1076
1077 //if (HAL_DMD_RIU_ReadByte(0x101E3E) != 0x02) // DVBT = BIT1 -> 0x02
1078 {
1079 if (INTERN_DVBT_LoadDSPCode() == FALSE)
1080 {
1081 ULOGD("DEMOD","DVB-T Load DSP Code Fail\n");
1082 return FALSE;
1083 }
1084 else
1085 {
1086 DBG_INTERN_DVBT(ULOGD("DEMOD","DVB-T Load DSP Code OK\n"));
1087 }
1088 }
1089
1090
1091 //// MCU Reset //////////
1092 DBG_INTERN_DVBT(ULOGD("DEMOD","INTERN_DVBT Reset...\n"));
1093 if (INTERN_DVBT_Reset() == FALSE)
1094 {
1095 DBG_INTERN_DVBT(ULOGD("DEMOD","Fail\n"));
1096 return FALSE;
1097 }
1098 else
1099 {
1100 DBG_INTERN_DVBT(ULOGD("DEMOD","OK\n"));
1101 }
1102
1103 // reset FDP
1104 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2200, 0xFF);
1105 // SRAM setting, DVB-T use it.
1106 // 0x2204, Bit0, 0:DVB-T use, 1: VIF use
1107 MDrv_SYS_DMD_VD_MBX_ReadReg(0x2204,&cData);
1108 MDrv_SYS_DMD_VD_MBX_WriteReg(0x2204, cData&0xFE);
1109
1110 status &= INTERN_DVBT_DSPReg_Init(u8DMD_DVBT_DSPRegInitExt, u8DMD_DVBT_DSPRegInitSize);
1111 return status;
1112 }
1113
1114 /************************************************************************************************
1115 Subject: Driving control
1116 Function: INTERN_DVBT_Driving_Control
1117 Parmeter: bInversionEnable : TRUE For High
1118 Return: void
1119 Remark:
1120 *************************************************************************************************/
INTERN_DVBT_Driving_Control(MS_BOOL bEnable)1121 void INTERN_DVBT_Driving_Control(MS_BOOL bEnable)
1122 {
1123 MS_U8 u8Temp;
1124
1125 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1126
1127 if (bEnable)
1128 {
1129 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1130 }
1131 else
1132 {
1133 u8Temp = u8Temp & (~0x01);
1134 }
1135
1136 DBG_INTERN_DVBT(ULOGD("DEMOD","---> INTERN_DVBT_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1137 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1138 }
1139 /************************************************************************************************
1140 Subject: Clk Inversion control
1141 Function: INTERN_DVBT_Clk_Inversion_Control
1142 Parmeter: bInversionEnable : TRUE For Inversion Action
1143 Return: void
1144 Remark:
1145 *************************************************************************************************/
INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)1146 void INTERN_DVBT_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1147 {
1148 MS_U8 u8Temp;
1149
1150 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1151
1152 if (bInversionEnable)
1153 {
1154 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1155 }
1156 else
1157 {
1158 u8Temp = u8Temp & (~0x02);
1159 }
1160
1161 DBG_INTERN_DVBT(ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp));
1162 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1163 }
1164 /************************************************************************************************
1165 Subject: Transport stream serial/parallel control
1166 Function: INTERN_DVBT_Serial_Control
1167 Parmeter: bEnable : TRUE For serial
1168 Return: MS_BOOL :
1169 Remark:
1170 *************************************************************************************************/
INTERN_DVBT_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1171 MS_BOOL INTERN_DVBT_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1172 {
1173 MS_U8 status = true;
1174 MS_U8 temp_val;
1175 DBG_INTERN_DVBT(ULOGD("DEMOD"," @INTERN_DVBT_ts... u8TSClk=%d\n",u8TSClk));
1176
1177 return status;
1178 if (u8TSClk == 0xFF) u8TSClk=0x13;
1179 if (bEnable) //Serial mode for TS pad
1180 {
1181 // serial
1182 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
1183 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
1184
1185 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
1186 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1187 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
1188
1189 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1190 temp_val|=0x04;
1191 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1192 #else
1193 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1194 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1195 temp_val|=0x07;
1196 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1197 #endif
1198 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
1199 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
1200
1201 //// INTERN_DVBT TS Control: Serial //////////
1202 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1203
1204 gsCmdPacket.param[0] = TS_SERIAL;
1205 #if(INTERN_DVBT_TS_SERIAL_INVERSION == 0)
1206 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1207 #else
1208 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1209 #endif
1210 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1211 }
1212 else
1213 {
1214 //parallel
1215 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
1216 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
1217
1218 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
1219 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
1220 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1221 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
1222 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1223 temp_val|=0x05;
1224 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1225 #else
1226 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
1227 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
1228 temp_val|=0x07;
1229 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
1230 #endif
1231
1232 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
1233 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
1234
1235 //// INTERN_DVBT TS Control: Parallel //////////
1236 gsCmdPacket.cmd_code = CMD_TS_CTRL;
1237
1238 gsCmdPacket.param[0] = TS_PARALLEL;
1239 #if(INTERN_DVBT_TS_PARALLEL_INVERSION == 0)
1240 gsCmdPacket.param[1] = 0;//TS_CLK_NO_INV;
1241 #else
1242 gsCmdPacket.param[1] = 1;//TS_CLK_INVERSE;
1243 #endif
1244 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 2);
1245 }
1246
1247 DBG_INTERN_DVBT(ULOGD("DEMOD","---> Inversion(Bit5) = 0x%x \n",gsCmdPacket.param[1] ));
1248
1249 INTERN_DVBT_Driving_Control(INTERN_DVBT_DTV_DRIVING_LEVEL);
1250 return status;
1251 }
1252
1253 /************************************************************************************************
1254 Subject: TS1 output control
1255 Function: INTERN_DVBT_PAD_TS1_Enable
1256 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
1257 Return: void
1258 Remark:
1259 *************************************************************************************************/
INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)1260 void INTERN_DVBT_PAD_TS1_Enable(MS_BOOL flag)
1261 {
1262 DBG_INTERN_DVBT(ULOGD("DEMOD"," @INTERN_DVBT_TS1_Enable... \n"));
1263
1264 if(flag) // PAD_TS1 Enable TS CLK PAD
1265 {
1266 //ULOGD("DEMOD","=== TS1_Enable ===\n");
1267 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
1268 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
1269 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
1270 }
1271 else // PAD_TS1 Disable TS CLK PAD
1272 {
1273 //ULOGD("DEMOD","=== TS1_Disable ===\n");
1274 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
1275 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
1276 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
1277 }
1278 }
1279
1280 /************************************************************************************************
1281 Subject: channel change config
1282 Function: INTERN_DVBT_Config
1283 Parmeter: BW: bandwidth
1284 Return: MS_BOOL :
1285 Remark:
1286 *************************************************************************************************/
INTERN_DVBT_Config(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U8 u8TSClk,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)1287 MS_BOOL INTERN_DVBT_Config ( DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
1288 {
1289 MS_U8 bandwidth;
1290 MS_U8 status = true;
1291
1292 DBG_INTERN_DVBT(ULOGD("DEMOD"," @INTERN_DVBT_config %d %d %d %d %d %ld %ld %d\n", BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap));
1293 DBG_INTERN_DVBT_TIME(ULOGD("DEMOD","INTERN_DVBT_Config, t = %ld\n",MsOS_GetSystemTime()));
1294
1295 if (u8TSClk == 0xFF) u8TSClk=0x13;
1296 switch(BW)
1297 {
1298 case E_DMD_RF_CH_BAND_6MHz:
1299 bandwidth = 1;
1300 break;
1301 case E_DMD_RF_CH_BAND_7MHz:
1302 bandwidth = 2;
1303 break;
1304 case E_DMD_RF_CH_BAND_8MHz:
1305 default:
1306 bandwidth = 3;
1307 break;
1308 }
1309
1310 status &= INTERN_DVBT_Reset();
1311
1312 // BW mode
1313 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_BW, bandwidth);
1314 // TS mode
1315 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_TS_SERIAL, bSerialTS? 0x01:0x00);
1316 // For Analog CCI 0:PAL B/G (Nordig), 1:PAL I (D-Book)
1317 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_CCI, bPalBG? 0x00:0x01);
1318 // Hierarchy mode
1319 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LP_SEL, bLPSel? 0x01:0x00);
1320 // FC
1321 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_L, (abs(DVBT_FS-u32IFFreq))&0xff);
1322 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FC_H, (abs((DVBT_FS-u32IFFreq))>>8)&0xff);
1323 // FS
1324 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_L, (u32FSFreq));
1325 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FS_H, (u32FSFreq)>>8);
1326 // IQSwap
1327 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_IQ_SWAP, (u8IQSwap));
1328
1329 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_LIF, (u32IFFreq < 10000) ? 1 : 0);
1330 // Fif
1331 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_L, (u32IFFreq)&0xff);
1332 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_DVBT_N_CFG_FIF_H, (u32IFFreq>>8)&0xff);
1333
1334 return status;
1335 }
1336 /************************************************************************************************
1337 Subject: enable hw to lock channel
1338 Function: INTERN_DVBT_Active
1339 Parmeter: bEnable
1340 Return: MS_BOOL
1341 Remark:
1342 *************************************************************************************************/
INTERN_DVBT_Active(MS_BOOL bEnable)1343 MS_BOOL INTERN_DVBT_Active(MS_BOOL bEnable)
1344 {
1345 MS_U8 status = true;
1346
1347 DBG_INTERN_DVBT(ULOGD("DEMOD"," @INTERN_DVBT_active\n"));
1348
1349 //// INTERN_DVBT Finite State Machine on/off //////////
1350 #if 0
1351 gsCmdPacket.cmd_code = CMD_FSM_CTRL;
1352
1353 gsCmdPacket.param[0] = (MS_U8)bEnable;
1354 status &= INTERN_DVBT_Cmd_Packet_Send(&gsCmdPacket, 1);
1355 #else
1356 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
1357 #endif
1358
1359 /*bryan temp mark*/
1360 #if(0)
1361 INTERN_DVBT_SignalQualityReset();
1362 #endif
1363
1364 return status;
1365 }
1366 /************************************************************************************************
1367 Subject: Return lock status
1368 Function: INTERN_DVBT_Lock
1369 Parmeter: eStatus :
1370 Return: MS_BOOL
1371 Remark:
1372 *************************************************************************************************/
INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout,MS_U16 u16DMD_DVBT_FEC_Timeout)1373 DMD_LOCK_STATUS INTERN_DVBT_Lock(MS_U16 u16DMD_DVBT_TPS_Timeout, MS_U16 u16DMD_DVBT_FEC_Timeout)
1374 {
1375 /*bryan temp mark*/
1376 //float fBER=0.0f;
1377
1378
1379 if (INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK))
1380 {
1381 if (bFECLock == FALSE)
1382 {
1383 u32FecFirstLockTime = MsOS_GetSystemTime();
1384 DBG_INTERN_DVBT(ULOGD("DEMOD","++++++++[utopia]dvbt lock\n"));
1385 }
1386 /*bryan temp mark*/
1387 /*
1388 if(INTERN_DVBT_GetPostViterbiBer(&fBER) == TRUE)
1389 {
1390 if((fBER > 1.0E-8) && (fBER < 1.0E-1))
1391 {
1392 if(fViterbiBerFiltered <= 0.0)
1393 fViterbiBerFiltered = fBER;
1394 else
1395 fViterbiBerFiltered = 0.9f*fViterbiBerFiltered+0.1f*fBER;
1396 }
1397 DBG_INTERN_DVBT(ULOGD("DEMOD","[dvbt]f_ber=%8.3e, g_viter_ber=%8.3e\n",fBER,fViterbiBerFiltered));
1398 }
1399 */
1400 u32FecLastLockTime = MsOS_GetSystemTime();
1401 bFECLock = TRUE;
1402 return E_DMD_LOCK;
1403 }
1404 else
1405 {
1406 /*bryam temp mark*/
1407 #if(0)
1408 INTERN_DVBT_SignalQualityReset();
1409 #endif
1410
1411 if (bFECLock == TRUE)
1412 {
1413 if ((MsOS_GetSystemTime() - u32FecLastLockTime) < 1000)
1414 {
1415 return E_DMD_LOCK;
1416 }
1417 }
1418 bFECLock = FALSE;
1419 }
1420
1421 if (INTERN_DVBT_GetLock(E_DMD_COFDM_NO_CHANNEL))
1422 {
1423 ULOGD("DEMOD","==> INTERN_DVBT_Lock -- E_DMD_COFDM_NO_CHANNEL \n");
1424 return E_DMD_UNLOCK;
1425 }
1426
1427 if(!bTPSLock)
1428 {
1429 if (INTERN_DVBT_GetLock(E_DMD_COFDM_TPS_EVER_LOCK))
1430 {
1431 DBG_INTERN_DVBT(ULOGD("DEMOD","==> INTERN_DVBT_Lock -- TPSLock \n"););
1432 bTPSLock = TRUE;
1433 }
1434 }
1435 if(bTPSLock)
1436 {
1437 DBG_INTERN_DVBT(ULOGD("DEMOD","TPSLock %ld\n",MsOS_GetSystemTime()));
1438 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_FEC_Timeout)
1439 {
1440 return E_DMD_CHECKING;
1441 }
1442 }
1443 else
1444 {
1445 if(MsOS_Timer_DiffTimeFromNow(u32ChkScanTimeStart) < u16DMD_DVBT_TPS_Timeout)
1446 {
1447 return E_DMD_CHECKING;
1448 }
1449 }
1450 return E_DMD_UNLOCK;
1451
1452 }
1453
1454
INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)1455 MS_BOOL INTERN_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eStatus)
1456 {
1457 MS_U16 u16Address = 0;
1458 MS_U8 cData = 0;
1459 MS_U8 cBitMask = 0;
1460
1461 switch( eStatus )
1462 {
1463 case E_DMD_COFDM_FEC_LOCK:
1464 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, &cData);
1465
1466 if (cData == 0x0B)
1467 {
1468 return TRUE;
1469 }
1470 else
1471 {
1472 return FALSE; // continuously un-lock
1473 }
1474 break;
1475
1476 case E_DMD_COFDM_PSYNC_LOCK:
1477 u16Address = 0x232C; //FEC: P-sync Lock,
1478 cBitMask = BIT(1);
1479 break;
1480
1481 case E_DMD_COFDM_TPS_LOCK:
1482 u16Address = 0x2222; //TPS HW Lock,
1483 cBitMask = BIT(1);
1484 break;
1485
1486 case E_DMD_COFDM_DCR_LOCK:
1487 u16Address = 0x2737; //DCR Lock,
1488 cBitMask = BIT(0);
1489 break;
1490
1491 case E_DMD_COFDM_AGC_LOCK:
1492 u16Address = 0x271D; //AGC Lock,
1493 cBitMask = BIT(0);
1494 break;
1495
1496 case E_DMD_COFDM_MODE_DET:
1497 u16Address = 0x24CF; //Mode CP Detect,
1498 cBitMask = BIT(4);
1499 break;
1500
1501 case E_DMD_COFDM_TPS_EVER_LOCK:
1502 u16Address = 0x20C0; //TPS Ever Lock,
1503 cBitMask = BIT(3);
1504 break;
1505
1506 case E_DMD_COFDM_NO_CHANNEL:
1507 u16Address = 0x20C0; // JL or FS no channel detection flag, 1 means no channel.
1508 cBitMask = BIT(7);
1509 break;
1510
1511 default:
1512 return FALSE;
1513 }
1514
1515 if (MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address, &cData) == FALSE)
1516 return FALSE;
1517
1518 if ((cData & cBitMask) == cBitMask)
1519 {
1520 return TRUE;
1521 }
1522
1523 return FALSE;
1524
1525 }
1526
1527 /****************************************************************************
1528 Subject: To get the Post viterbi BER
1529 Function: INTERN_DVBT_GetPostViterbiBer
1530 Parmeter: Quility
1531 Return: E_RESULT_SUCCESS
1532 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1533 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1534 We will not read the Period, and have the "/256/8"
1535 *****************************************************************************/
1536 /*bryan temp mark*/
1537
INTERN_DVBT_GetPostViterbiBer(MS_U16 * BitErrPeriod_reg,MS_U32 * BitErr_reg,MS_U16 * PktErr_reg)1538 MS_BOOL INTERN_DVBT_GetPostViterbiBer(MS_U16 *BitErrPeriod_reg, MS_U32 *BitErr_reg, MS_U16 *PktErr_reg)
1539 {
1540 MS_BOOL status = true;
1541 MS_U8 reg=0, reg_frz=0;
1542 MS_U16 BitErrPeriod;
1543 MS_U32 BitErr;
1544 MS_U16 PktErr;
1545
1546 /////////// Post-Viterbi BER /////////////
1547 #if 0
1548 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1549 {
1550 *ber = (float)-1.0;
1551 return false;
1552 }
1553 #endif
1554 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1556 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1557
1558 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0
1559 // 0x47 [15:8] reg_bit_err_sblprd_15_8
1560 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x47, ®);
1561 BitErrPeriod = reg;
1562
1563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x46, ®);
1564 BitErrPeriod = (BitErrPeriod << 8)|reg;
1565
1566 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
1567 // 0x6b [15:8] reg_bit_err_num_15_8
1568 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
1569 // 0x6d [15:8] reg_bit_err_num_31_24
1570 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6d, ®);
1571 BitErr = reg;
1572
1573 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6c, ®);
1574 BitErr = (BitErr << 8)|reg;
1575
1576 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6b, ®);
1577 BitErr = (BitErr << 8)|reg;
1578
1579 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x6a, ®);
1580 BitErr = (BitErr << 8)|reg;
1581
1582 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1583 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1584 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1585 PktErr = reg;
1586
1587 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1588 PktErr = (PktErr << 8)|reg;
1589
1590 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1591 reg_frz=reg_frz&(~0x03);
1592 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1593
1594 if (BitErrPeriod == 0 ) //protect 0
1595 BitErrPeriod = 1;
1596
1597
1598 *BitErrPeriod_reg = BitErrPeriod;
1599 *BitErr_reg = BitErr;
1600 *PktErr_reg = PktErr;
1601
1602 DBG_GET_SIGNAL(ULOGD("DEMOD","INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1603
1604 return status;
1605 }
1606 #if(0)
1607 /****************************************************************************
1608 Subject: To get the Pre viterbi BER
1609 Function: INTERN_DVBT_GetPreViterbiBer
1610 Parmeter: ber
1611 Return: E_RESULT_SUCCESS
1612 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1613 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1614 We will not read the Period, and have the "/256/8"
1615 *****************************************************************************/
INTERN_DVBT_GetPreViterbiBer(float * ber)1616 MS_BOOL INTERN_DVBT_GetPreViterbiBer(float *ber)
1617 {
1618 MS_U8 status = true;
1619 MS_U8 reg=0, reg_frz=0;
1620 MS_U16 BitErrPeriod;
1621 MS_U32 BitErr;
1622 MS_BOOL BEROver;
1623
1624 // bank 7 0x10 [3] reg_rd_freezeber
1625 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x10, ®_frz);
1626 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz|0x08);
1627
1628 // bank 7 0x16 [7:0] reg_ber_timerl
1629 // [15:8] reg_ber_timerm
1630 // bank 7 0x18 [5:0] reg_ber_timerh
1631 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x18, ®);
1632 BitErrPeriod = reg&0x3f;
1633
1634 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x17, ®);
1635 BitErrPeriod = (BitErrPeriod << 8)|reg;
1636
1637 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x16, ®);
1638 BitErrPeriod = (BitErrPeriod << 8)|reg;
1639
1640 // bank 7 0x1e [7:0] reg_ber_7_0
1641 // [15:8] reg_ber_15_8
1642 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1F, ®);
1643 BitErr = reg;
1644
1645 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1E, ®);
1646 BitErr = (BitErr << 8)|reg;
1647
1648 // bank 7 0x1a [13:8] reg_cor_intstat_reg
1649 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x1B, ®);
1650 if (reg & 0x10)
1651 BEROver = true;
1652 else
1653 BEROver = false;
1654
1655 if (BitErrPeriod ==0 )//protect 0
1656 BitErrPeriod=1;
1657
1658 if (BEROver)
1659 {
1660 *ber = 1;
1661 ULOGD("DEMOD","BER is over\n");
1662 }
1663 else
1664 {
1665 if (BitErr <=0 )
1666 *ber=0.5 / (float)(BitErrPeriod * 256);
1667 else
1668 *ber=(float)(BitErr) / (float)(BitErrPeriod * 256);
1669 }
1670
1671 // bank 7 0x10 [3] reg_rd_freezeber
1672 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FEC_REG_BASE + 0x10, reg_frz);
1673
1674 return status;
1675 }
1676 #endif
1677
1678 /****************************************************************************
1679 Subject: To get the Packet error
1680 Function: INTERN_DVBT_GetPacketErr
1681 Parmeter: pktErr
1682 Return: E_RESULT_SUCCESS
1683 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
1684 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
1685 We will not read the Period, and have the "/256/8"
1686 *****************************************************************************/
INTERN_DVBT_GetPacketErr(MS_U16 * u16PktErr)1687 MS_BOOL INTERN_DVBT_GetPacketErr(MS_U16 *u16PktErr)
1688 {
1689 MS_BOOL status = true;
1690 MS_U8 reg = 0, reg_frz = 0;
1691 MS_U16 PktErr;
1692
1693 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1694 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x03, ®_frz);
1695 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz|0x03);
1696
1697 // bank 1f 0x66 [7:0] reg_uncrt_pkt_num_7_0
1698 // 0x67 [15:8] reg_uncrt_pkt_num_15_8
1699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x67, ®);
1700 PktErr = reg;
1701
1702 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(BACKEND_REG_BASE+0x66, ®);
1703 PktErr = (PktErr << 8)|reg;
1704
1705 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
1706 reg_frz=reg_frz&(~0x03);
1707 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(BACKEND_REG_BASE+0x03, reg_frz);
1708
1709 DBG_GET_SIGNAL(ULOGD("DEMOD","INTERN_DVBT PktErr = %d \n ", (int)PktErr));
1710
1711 *u16PktErr = PktErr;
1712
1713 return status;
1714 }
1715
1716 /****************************************************************************
1717 Subject: To get the DVBT parameter
1718 Function: INTERN_DVBT_Get_TPS_Info
1719 Parmeter: point to return parameter
1720 Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
1721 Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
1722 LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1723 HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
1724 GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
1725 FFT ( b14) : 0~1 => 2K, 8K
1726 Priority(bit 15) : 0~1=> HP,LP
1727 Return: TRUE
1728 FALSE
1729 Remark: The TPS parameters will be available after TPS lock
1730 *****************************************************************************/
INTERN_DVBT_Get_TPS_Info(MS_U16 * TPS_parameter)1731 MS_BOOL INTERN_DVBT_Get_TPS_Info( MS_U16 * TPS_parameter)
1732 {
1733 MS_U8 u8Temp;
1734
1735 if (MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x22, &u8Temp) == FALSE)
1736 return FALSE;
1737
1738 if ((u8Temp& 0x02) != 0x02)
1739 {
1740 return FALSE; //TPS unlock
1741 }
1742 else
1743 {
1744 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &u8Temp) == FALSE )
1745 return FALSE;
1746
1747 *TPS_parameter = u8Temp & 0x03; //Constellation (b2 ~ b0)
1748 *TPS_parameter |= (u8Temp & 0x70) >> 1; //Hierarchy (b5 ~ b3)
1749
1750 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &u8Temp) == FALSE )
1751 return FALSE;
1752
1753 *TPS_parameter |= (MS_U16)(u8Temp & 0x07) << 6; //LP Code Rate (b8 ~ b6)
1754 *TPS_parameter |= (MS_U16)(u8Temp & 0x70) << 5; //HP Code Rate (b11 ~ b9)
1755
1756 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &u8Temp) == FALSE )
1757 return FALSE;
1758
1759 *TPS_parameter |= (MS_U16)(u8Temp & 0x03) << 12; //GI (b13 ~ b12)
1760 *TPS_parameter |= (MS_U16)(u8Temp & 0x30) << 10; //FFT ( b14)
1761
1762 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FEC_REG_BASE + 0x0C, &u8Temp) == FALSE )
1763 return FALSE;
1764
1765 *TPS_parameter |=(MS_U16)(u8Temp&0x08)<<12;//Priority(bit 15)
1766
1767 }
1768 return TRUE;
1769 }
1770
1771
1772 /****************************************************************************
1773 Subject: Read the signal to noise ratio (SNR)
1774 Function: INTERN_DVBT_GetSNR
1775 Parmeter: None
1776 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
1777 Remark:
1778 *****************************************************************************/
1779
INTERN_DVBT_GetSNR(MS_U32 * noise_power_reg)1780 void INTERN_DVBT_GetSNR (MS_U32 *noise_power_reg)
1781 {
1782 MS_U8 status = true;
1783 MS_U8 reg=0, reg_frz=0;
1784 MS_U32 noise_power;
1785
1786
1787 // bank 6 0xfe [0] reg_fdp_freeze
1788 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
1789 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
1790
1791 // bank 6 0xff [0] reg_fdp_load
1792 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
1793
1794 // bank 6 0x4a [26:0] reg_snr_accu <27,1>
1795 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5B, ®);
1796 noise_power = reg & 0x07;
1797
1798 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x5A, ®);
1799 noise_power = (noise_power << 8)|reg;
1800
1801 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x59, ®);
1802 noise_power = (noise_power << 8)|reg;
1803
1804 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(ISDBT_FDPE_REG_BASE + 0x58, ®);
1805 noise_power = (noise_power << 8)|reg;
1806
1807
1808 // bank 6 0xfe [0] reg_fdp_freeze
1809 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz);
1810
1811 // bank 6 0xff [0] reg_fdp_load
1812 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
1813
1814 *noise_power_reg = noise_power;
1815 }
1816
1817 /****************************************************************************
1818 Subject: To check if Hierarchy on
1819 Function: INTERN_DVBT_Is_HierarchyOn
1820 Parmeter:
1821 Return: BOOLEAN
1822 *****************************************************************************/
INTERN_DVBT_Is_HierarchyOn(void)1823 MS_BOOL INTERN_DVBT_Is_HierarchyOn( void)
1824 {
1825 MS_U16 u16_tmp;
1826
1827 if(INTERN_DVBT_Get_TPS_Info(&u16_tmp) == FALSE)
1828 return FALSE;
1829 //ULOGD("DEMOD","u16_tmp........%x %x\n",u16_tmp,u16_tmp&0x38);
1830 if(u16_tmp&0x38)
1831 {
1832 return TRUE;
1833 }
1834 return FALSE;
1835 }
1836
1837 // arthur
INTERN_DVBT_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)1838 MS_BOOL INTERN_DVBT_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
1839 {
1840 MS_BOOL status = true;
1841
1842 status = HAL_DMD_IFAGC_RegRead(ifagc_reg, ifagc_reg_lsb, ifagc_err);
1843
1844 return status;
1845 }
1846
1847 /*bryan temp mark*/
1848 #if(0)
INTERN_DVBT_GetSignalStrength(MS_U16 * strength,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1849 MS_BOOL INTERN_DVBT_GetSignalStrength(MS_U16 *strength,const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1850 {
1851 MS_U8 status = true;
1852 float ch_power_db = 0.0f;
1853 float ch_power_ref = 11.0f;
1854 float ch_power_rel = 0.0f;
1855 MS_U8 u8_index = 0;
1856 MS_U16 tps_info_qam,tps_info_cr;
1857
1858 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
1859 {
1860 *strength = 0;
1861 return TRUE;
1862 }
1863 DBG_INTERN_DVBT_TIME(ULOGD("DEMOD","INTERN_DVBT_GetSignalStrength, t=%ld\n",MsOS_GetSystemTime()));
1864
1865 // if (INTERN_DVBT_Lock(COFDM_TPS_LOCK))
1866 //if (INTERN_DVBT_Lock(COFDM_AGC_LOCK))
1867 /* Actually, it's more reasonable, that signal level depended on cable input power level
1868 * thougth the signal isn't dvb-t signal.
1869 */
1870
1871 // use pointer of IFAGC table to identify
1872 // case 1: RFAGC from SAR, IFAGC controlled by demod
1873 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
1874 status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
1875 sDMD_DVBT_InitData->pTuner_RfagcSsi, sDMD_DVBT_InitData->u16Tuner_RfagcSsi_Size,
1876 sDMD_DVBT_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_HiRef_Size,
1877 sDMD_DVBT_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcSsi_LoRef_Size,
1878 sDMD_DVBT_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_HiRef_Size,
1879 sDMD_DVBT_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT_InitData->u16Tuner_IfagcErr_LoRef_Size);
1880
1881
1882 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_qam, TS_MODUL_MODE) == FALSE)
1883 ULOGD("DEMOD","[dvbt]TPS qam parameter retrieve failure\n");
1884
1885 if(INTERN_DVBT_Get_TPS_Parameter_Const(&tps_info_cr, TS_CODE_RATE) == FALSE)
1886 ULOGD("DEMOD","[dvbt]TPS cr parameter retrieve failure\n");
1887
1888
1889 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
1890 {
1891 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)tps_info_qam)
1892 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)tps_info_cr))
1893 {
1894 ch_power_ref = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
1895 break;
1896 }
1897 else
1898 {
1899 u8_index++;
1900 }
1901 }
1902
1903 if (ch_power_ref > 10.0f)
1904 *strength = 0;
1905 else
1906 {
1907 ch_power_rel = ch_power_db - ch_power_ref;
1908
1909 if ( ch_power_rel < -15.0f )
1910 {
1911 *strength = 0;
1912 }
1913 else if ( ch_power_rel < 0.0f )
1914 {
1915 *strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
1916 }
1917 else if ( ch_power_rel < 20 )
1918 {
1919 *strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
1920 }
1921 else if ( ch_power_rel < 35.0f )
1922 {
1923 *strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
1924 }
1925 else
1926 {
1927 *strength = 100;
1928 }
1929 }
1930
1931 if (FALSE == INTERN_DVBT_GetLock(E_DMD_COFDM_FEC_LOCK) )
1932 {
1933 *strength = 0;
1934 return TRUE;
1935 }
1936
1937 DBG_GET_SIGNAL(ULOGD("DEMOD",">>> SSI_CH_PWR(dB) = %f , Score = %d<<<\n", ch_power_db, *strength));
1938 DBG_GET_SIGNAL(ULOGD("DEMOD",">>> SSI = %d <<<\n", (int)*strength));
1939
1940 return status;
1941 }
1942
1943
1944 /****************************************************************************
1945 Subject: To get the DVT Signal quility
1946 Function: INTERN_DVBT_GetSignalQuality
1947 Parmeter: Quility
1948 Return: E_RESULT_SUCCESS
1949 E_RESULT_FAILURE
1950 Remark: Here we have 4 level range
1951 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
1952 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
1953 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
1954 <4>.4th Range => Quality <10
1955 *****************************************************************************/
INTERN_DVBT_GetSignalQuality(MS_U16 * quality,const DMD_DVBT_InitData * sDMD_DVBT_InitData,MS_U8 u8SarValue,float fRFPowerDbm)1956 MS_BOOL INTERN_DVBT_GetSignalQuality(MS_U16 *quality, const DMD_DVBT_InitData *sDMD_DVBT_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1957 {
1958 float ber_sqi;
1959 float fber;
1960 float cn_rec = 0;
1961 float cn_nordig_p1 = 0;
1962 float cn_rel = 0;
1963
1964 MS_U8 status = true;
1965 MS_U8 tps_cnstl = 0, tps_cr = 0, i = 0;
1966 MS_U16 u16_tmp;
1967
1968 DBG_INTERN_DVBT_TIME(ULOGD("DEMOD","INTERN_DVBT_GetSignalQuality, t=%ld\n",MsOS_GetSystemTime()));
1969
1970 if (TRUE == INTERN_DVBT_GetLock(E_DMD_COFDM_PSYNC_LOCK) )
1971 {
1972
1973 if ( MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime) < 300)
1974 {
1975 MsOS_DelayTask(300 - MsOS_Timer_DiffTimeFromNow(u32FecFirstLockTime));
1976 }
1977 ///////// Get Pre-RS (Post-Viterbi) BER to determine BER_SQI //////////
1978 if(fViterbiBerFiltered<= 0.0)
1979 {
1980 if (INTERN_DVBT_GetPostViterbiBer(&fber) == FALSE)
1981 {
1982 DBG_INTERN_DVBT(ULOGD("DEMOD","GetPostViterbiBer Fail!\n"));
1983 return FALSE;
1984 }
1985 fViterbiBerFiltered = fber;
1986 }
1987 else
1988 {
1989 fber = fViterbiBerFiltered;
1990 }
1991
1992 if (fber > 1.0E-3)
1993 ber_sqi = 0.0;
1994 else if (fber > 8.5E-7)
1995 #ifdef MSOS_TYPE_LINUX
1996 ber_sqi = (log10f(1.0f/fber))*20.0f - 22.0f;
1997 #else
1998 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 22.0f;
1999 #endif
2000 else
2001 ber_sqi = 100.0;
2002
2003 cn_rec = INTERN_DVBT_GetSNR();
2004
2005 if (cn_rec == -1) //get SNR return fail
2006 status = false;
2007
2008 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
2009 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
2010 tps_cnstl = 0xff;
2011 tps_cr = 0xff;
2012 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_MODUL_MODE) == TRUE)
2013 tps_cnstl = (MS_U8)u16_tmp&0x07;
2014 if(INTERN_DVBT_Get_TPS_Parameter_Const( &u16_tmp, TS_CODE_RATE) == TRUE)
2015 tps_cr = (MS_U8)u16_tmp&0x07;
2016
2017 for(i = 0; i < sDMD_DVBT_InitData->u16SqiCnNordigP1_Size; i++)
2018 {
2019 if ( (tps_cnstl == sDMD_DVBT_InitData->pSqiCnNordigP1[i].constel)
2020 && (tps_cr == sDMD_DVBT_InitData->pSqiCnNordigP1[i].code_rate) )
2021 {
2022 cn_nordig_p1 = sDMD_DVBT_InitData->pSqiCnNordigP1[i].cn_ref;
2023 break;
2024 }
2025 }
2026
2027 // 0,5, snr offset
2028 cn_rel = cn_rec - cn_nordig_p1 + 0.5f;
2029
2030 // patch....
2031 // Noridg SQI,
2032 // 64QAM, CR34, GI14, SNR 22dB.
2033 if ( (tps_cnstl == _64QAM) && (tps_cr == _CR3Y4)
2034 && (cn_rel < 2.5f) && (cn_rel > 1.5f))
2035 {
2036 cn_rel += 1.5f;
2037 }
2038
2039 if (cn_rel < -7.0f)
2040 {
2041 *quality = 0;
2042 }
2043 else if (cn_rel < 3.0)
2044 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
2045 else
2046 *quality = (MS_U16)ber_sqi;
2047 }
2048 else
2049 {
2050 *quality = 0;
2051 }
2052
2053 DBG_GET_SIGNAL(ULOGD("DEMOD","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, tps_cnstl, tps_cr));
2054 DBG_GET_SIGNAL(ULOGD("DEMOD","BER = %8.3e\n", fber));
2055 DBG_GET_SIGNAL(ULOGD("DEMOD","Signal Quility = %d\n", *quality));
2056 return status;
2057 }
2058 #endif
2059
2060 /****************************************************************************
2061 Subject: To get the Cell ID
2062 Function: INTERN_DVBT_Get_CELL_ID
2063 Parmeter: point to return parameter cell_id
2064
2065 Return: TRUE
2066 FALSE
2067 Remark:
2068 *****************************************************************************/
INTERN_DVBT_Get_CELL_ID(MS_U16 * cell_id)2069 MS_BOOL INTERN_DVBT_Get_CELL_ID(MS_U16 *cell_id)
2070 {
2071 MS_U8 status = true;
2072 MS_U8 value1=0;
2073 MS_U8 value2=0;
2074
2075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [15:8]
2076 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [7:0]
2077
2078 *cell_id = ((MS_U16)value1<<8)|value2;
2079 return status;
2080 }
2081 /*
2082 FUNCTION_RESULT INTERN_DVBT_GetSignalQuality_Average(WORD *quality)
2083 {
2084 #define SQI_LOOP_NUM 50
2085 U8 inn = 0;
2086 WORD sqi = 0;
2087 WORD ave_sqi = 0;
2088 WORD ave_num = 0;
2089 while(inn++<SQI_LOOP_NUM)
2090 {
2091 if(INTERN_DVBT_GetSignalQuality(&sqi) == E_RESULT_SUCCESS)
2092 {
2093 ULOGD("DEMOD","[%d][t=%d],sqi=%d\n",inn,INTERN_DVBT_GET_TIME,sqi);
2094 ave_sqi+=sqi;
2095 ave_num++;
2096 }
2097 MsOS_DelayTask(50);
2098 }
2099
2100 if(ave_num != 0 )
2101 *quality = ave_sqi/ave_num;
2102
2103 return ave_num==0?E_RESULT_FAILURE:E_RESULT_SUCCESS;
2104 }
2105 */
2106 /****************************************************************************
2107 Subject: To get the DVBT Carrier Freq Offset
2108 Function: INTERN_DVBT_Get_FreqOffset
2109 Parmeter: Frequency offset (in KHz), bandwidth
2110 Return: E_RESULT_SUCCESS
2111 E_RESULT_FAILURE
2112 Remark:
2113 *****************************************************************************/
2114 /*bryan temp mark*/
2115 #if(0)
INTERN_DVBT_Get_FreqOffset(float * pFreqOff,MS_U8 u8BW)2116 MS_BOOL INTERN_DVBT_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW)
2117 {
2118 float N, FreqB;
2119 float FreqCfoTd, FreqCfoFd, FreqIcfo;
2120 MS_U32 RegCfoTd, RegCfoFd, RegIcfo;
2121 MS_U8 reg_frz=0, reg=0;
2122 MS_U8 status;
2123
2124 FreqB = (float)u8BW * 8 / 7;
2125
2126 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2127
2128 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2129
2130 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2131 RegCfoTd = reg;
2132
2133 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2134 RegCfoTd = (RegCfoTd << 8)|reg;
2135
2136 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2137 RegCfoTd = (RegCfoTd << 8)|reg;
2138
2139 FreqCfoTd = (float)RegCfoTd;
2140
2141 if (RegCfoTd & 0x800000)
2142 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2143
2144 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2145
2146 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2147
2148 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2149 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2150
2151 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2152
2153 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2154 RegCfoFd = reg;
2155
2156 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2157 RegCfoFd = (RegCfoFd << 8)|reg;
2158
2159 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2160 RegCfoFd = (RegCfoFd << 8)|reg;
2161
2162 FreqCfoFd = (float)RegCfoFd;
2163
2164 if (RegCfoFd & 0x800000)
2165 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2166
2167 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2168
2169 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2170 RegIcfo = reg & 0x07;
2171
2172 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2173 RegIcfo = (RegIcfo << 8)|reg;
2174
2175 FreqIcfo = (float)RegIcfo;
2176
2177 if (RegIcfo & 0x400)
2178 FreqIcfo = FreqIcfo - (float)0x800;
2179
2180 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2181 reg = reg & 0x30;
2182
2183 switch (reg)
2184 {
2185 case 0x00: N = 2048; break;
2186 case 0x20: N = 4096; break;
2187 case 0x10:
2188 default: N = 8192; break;
2189 }
2190
2191 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2192 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2193 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2194 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2195 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2196 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
2197 // DBG_GET_SIGNAL(ULOGD("DEMOD","FCFO = %f\n", FreqCfoFd));
2198 // DBG_GET_SIGNAL(ULOGD("DEMOD","TCFO = %f\n", FreqCfoTd));
2199 // DBG_GET_SIGNAL(ULOGD("DEMOD","ICFO = %f\n", FreqIcfo));
2200 DBG_GET_SIGNAL(ULOGD("DEMOD","CFOE = %f\n", *pFreqOff));
2201
2202 if (status == TRUE)
2203 return TRUE;
2204 else
2205 return FALSE;
2206 }
2207 #endif
2208
INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)2209 void INTERN_DVBT_Power_ON_OFF(MS_U8 bPowerOn)
2210 {
2211
2212 bPowerOn = bPowerOn;
2213 }
2214
INTERN_DVBT_Power_Save(void)2215 MS_BOOL INTERN_DVBT_Power_Save(void)
2216 {
2217
2218 return TRUE;
2219 }
2220
2221 /****************************************************************************
2222 Subject: To get the DVBT constellation parameter
2223 Function: INTERN_DVBT_Get_TPS_Parameter_Const
2224 Parmeter: point to return parameter(0: QPSK, 1:16QAM, 2:64QAM)
2225 Return: TRUE
2226 FALSE
2227 Remark: The TPS parameters will be available after TPS lock
2228 *****************************************************************************/
INTERN_DVBT_Get_TPS_Parameter_Const(MS_U16 * TPS_parameter,E_SIGNAL_TYPE eSignalType)2229 MS_BOOL INTERN_DVBT_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType)
2230 {
2231 MS_U8 tps_param;
2232
2233 //@@++ Arki 20100125
2234 if (eSignalType == TS_MODUL_MODE)
2235 {
2236 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x24, &tps_param) == FALSE ) return FALSE;
2237 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2238 }
2239
2240 if (eSignalType == TS_CODE_RATE)
2241 {
2242 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x25, &tps_param) == FALSE ) return FALSE;
2243 *TPS_parameter = (tps_param & (BIT(6)|BIT(5)|BIT(4)))>>4 ;
2244 }
2245
2246 if (eSignalType == TS_GUARD_INTERVAL)
2247 {
2248 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2249 *TPS_parameter = tps_param & (BIT(0)|BIT(1)) ;
2250 }
2251
2252 if (eSignalType == TS_FFX_VALUE)
2253 {
2254 if ( MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, &tps_param) == FALSE ) return FALSE;
2255 *TPS_parameter = (tps_param & (BIT(5)|BIT(4)))>>4 ;
2256 }
2257 //@@-- Arki 20100125
2258 return TRUE;
2259 }
2260
INTERN_DVBT_Version(MS_U16 * ver)2261 MS_BOOL INTERN_DVBT_Version(MS_U16 *ver)
2262 {
2263
2264 MS_U8 status = true;
2265 MS_U8 tmp = 0;
2266 MS_U16 u16_INTERN_DVBT_Version;
2267
2268 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC1, &tmp);
2269 u16_INTERN_DVBT_Version = tmp;
2270 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC2, &tmp);
2271 u16_INTERN_DVBT_Version = u16_INTERN_DVBT_Version<<8|tmp;
2272 *ver = u16_INTERN_DVBT_Version;
2273
2274 return status;
2275 }
2276
INTERN_DVBT_Version_minor(MS_U8 * ver2)2277 MS_BOOL INTERN_DVBT_Version_minor(MS_U8 *ver2)
2278 {
2279
2280 MS_U8 status = true;
2281
2282 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0xC3, ver2);
2283
2284 return status;
2285 }
2286
2287
INTERN_DVBT_Show_Demod_Version(void)2288 MS_BOOL INTERN_DVBT_Show_Demod_Version(void)
2289 {
2290
2291 MS_BOOL status = true;
2292 MS_U16 u16_INTERN_DVBT_Version;
2293 MS_U8 u8_minor_ver = 0;
2294
2295 status &= INTERN_DVBT_Version(&u16_INTERN_DVBT_Version);
2296 status &= INTERN_DVBT_Version_minor(&u8_minor_ver);
2297 ULOGD("DEMOD","[DVBT]Version = 0x%x,0x%x\n",u16_INTERN_DVBT_Version,u8_minor_ver);
2298
2299 return status;
2300 }
2301
2302 /*bryan temp mark*/
2303 #if(0)
INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)2304 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
2305 {
2306 MS_U8 u8_index = 0;
2307 MS_BOOL bRet = false;
2308
2309 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2310 {
2311 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2312 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2313 {
2314 dvbt_ssi_dbm_nordigp1[u8_index].p_ref = write_value;
2315 bRet = true;
2316 break;
2317 }
2318 else
2319 {
2320 u8_index++;
2321 }
2322 }
2323 return bRet;
2324 }
2325
INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)2326 MS_BOOL INTERN_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
2327 {
2328 MS_U8 u8_index = 0;
2329 MS_BOOL bRet = false;
2330
2331 while(dvbt_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
2332 {
2333 if ( (dvbt_ssi_dbm_nordigp1[u8_index].constel == (DMD_CONSTEL)constel)
2334 && (dvbt_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_CODERATE)code_rate))
2335 {
2336 *read_value = dvbt_ssi_dbm_nordigp1[u8_index].p_ref;
2337 bRet = true;
2338 break;
2339 }
2340 else
2341 {
2342 u8_index++;
2343 }
2344 }
2345 return bRet;
2346 }
2347 #endif
2348
2349 #if (INTERN_DVBT_INTERNAL_DEBUG == 1)
INTERN_DVBT_get_demod_state(MS_U8 * state)2350 void INTERN_DVBT_get_demod_state(MS_U8* state)
2351 {
2352 MDrv_SYS_DMD_VD_MBX_ReadReg(0x23E0, state);
2353 return;
2354 }
2355
INTERN_DVBT_Show_ChannelLength(void)2356 MS_BOOL INTERN_DVBT_Show_ChannelLength(void)
2357 {
2358 MS_U8 status = true;
2359 MS_U8 tmp = 0;
2360 MS_U16 len = 0;
2361 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71,&tmp);
2362 len = tmp;
2363 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70,&tmp);
2364 len = (len<<8)|tmp;
2365 ULOGD("DEMOD","[dvbt]Hw_channel=%d\n",len);
2366 return status;
2367 }
2368
INTERN_DVBT_Show_SW_ChannelLength(void)2369 MS_BOOL INTERN_DVBT_Show_SW_ChannelLength(void)
2370 {
2371 MS_U8 status = true;
2372 MS_U8 tmp = 0,peak_num = 0,insideGI = 0,stoptracking = 0,flag_short_echo = 0,fsa_mode = 0;
2373 MS_U16 sw_len = 0;
2374 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C4,&tmp);
2375 sw_len = tmp;
2376 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C3,&tmp);
2377 sw_len = (sw_len<<8)|tmp;
2378 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C2,&tmp);
2379 peak_num = tmp;
2380 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C5,&tmp);
2381 insideGI = tmp&0x01;
2382 stoptracking = (tmp&0x02)>>1;
2383 flag_short_echo = (tmp&0x0C)>>2;
2384 fsa_mode = (tmp&0x30)>>4;
2385
2386 ULOGD("DEMOD","[dvbt]SW_len=%d, peak_num=%d, insideGI=%d, stoptrack=%d, short_echo=%d, fsa_mode=%d\n",
2387 sw_len,peak_num,insideGI,stoptracking,flag_short_echo,fsa_mode);
2388
2389 return status;
2390 }
2391
INTERN_DVBT_Show_ACI_CI(void)2392 MS_BOOL INTERN_DVBT_Show_ACI_CI(void)
2393 {
2394
2395 #define BIT4 0x10
2396 MS_U8 status = true;
2397 MS_U8 digACI =0 ,flag_CI = 0,td_coef = 0,tmp = 0;
2398
2399 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2357,&tmp);
2400 digACI = (tmp&BIT4)>>4;
2401
2402 // get flag_CI
2403 // 0: No interference
2404 // 1: CCI
2405 // 2: in-band ACI
2406 // 3: N+1 ACI
2407 // flag_ci = (tmp&0xc0)>>6;
2408 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2356,&tmp);
2409 flag_CI = (tmp&0xC0)>>6;
2410 td_coef = (tmp&0x0C)>>2;
2411
2412 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20E8,&tmp);
2413
2414 ULOGD("DEMOD","[dvbt]DigACI=%d, Flag_CI=%d, td_coef=%d\n",digACI,flag_CI,td_coef);
2415
2416 return status;
2417 }
2418
INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)2419 MS_BOOL INTERN_DVBT_Show_FD_CH_LEN_S_SEL(void)
2420 {
2421 MS_U8 status = true;
2422 MS_U8 tmp = 0,fd = 0,ch_len = 0,snr_sel = 0,pertone_num = 0;
2423 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2355, &tmp);
2424 fd = tmp;
2425 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2354, &tmp);
2426 ch_len = tmp;
2427 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x46, &tmp);
2428 snr_sel = (tmp>>4)&0x03;
2429 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x22AC, &tmp);
2430 pertone_num = tmp;
2431
2432 ULOGD("DEMOD","[dvbt]fd=0x%x, ch_len=0x%x, snr_sel=0x%x, pertone_num=0x%x\n",fd,ch_len,snr_sel,pertone_num);
2433
2434 return status;
2435 }
2436
INTERN_DVBT_Get_CFO(void)2437 MS_BOOL INTERN_DVBT_Get_CFO(void)
2438 {
2439
2440 float N = 0, FreqB = 0;
2441 float FreqCfoTd = 0, FreqCfoFd = 0, FreqIcfo = 0, total_cfo = 0;
2442 MS_U32 RegCfoTd = 0, RegCfoFd = 0, RegIcfo = 0;
2443 MS_U8 reg_frz = 0, reg = 0;
2444 MS_U8 status = 0;
2445 MS_U8 u8BW = 8;
2446
2447 FreqB = (float)u8BW * 8 / 7;
2448
2449 status = MDrv_SYS_DMD_VD_MBX_ReadReg(TDP_REG_BASE + 0x05, ®_frz);
2450
2451 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz|0x80);
2452
2453 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c8, ®);
2454 RegCfoTd = reg;
2455
2456 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c7, ®);
2457 RegCfoTd = (RegCfoTd << 8)|reg;
2458
2459 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x24c6, ®);
2460 RegCfoTd = (RegCfoTd << 8)|reg;
2461
2462 FreqCfoTd = (float)RegCfoTd;
2463
2464 if (RegCfoTd & 0x800000)
2465 FreqCfoTd = FreqCfoTd - (float)0x1000000;
2466
2467 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
2468
2469 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(TDP_REG_BASE + 0x05, reg_frz&(~0x80));
2470
2471 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0xfe, ®_frz);
2472 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz|0x01);
2473
2474 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2475
2476 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x33, ®);
2477 RegCfoFd = reg;
2478
2479 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x32, ®);
2480 RegCfoFd = (RegCfoFd << 8)|reg;
2481
2482 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x31, ®);
2483 RegCfoFd = (RegCfoFd << 8)|reg;
2484
2485 FreqCfoFd = (float)RegCfoFd;
2486
2487 if (RegCfoFd & 0x800000)
2488 FreqCfoFd = FreqCfoFd - (float)0x1000000;
2489
2490 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
2491
2492 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x19, ®);
2493 RegIcfo = reg & 0x07;
2494
2495 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x18, ®);
2496 RegIcfo = (RegIcfo << 8)|reg;
2497
2498 FreqIcfo = (float)RegIcfo;
2499
2500 if (RegIcfo & 0x400)
2501 FreqIcfo = FreqIcfo - (float)0x800;
2502
2503 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x26, ®);
2504 reg = reg & 0x30;
2505
2506 switch (reg)
2507 {
2508 case 0x00: N = 2048; break;
2509 case 0x20: N = 4096; break;
2510 case 0x10:
2511 default: N = 8192; break;
2512 }
2513
2514 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
2515 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe, reg_frz&(~0x01));
2516 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xfe+1, 0x01);
2517 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FDP_REG_BASE + 0xff, 0x01);
2518 total_cfo = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
2519
2520 ULOGD("DEMOD","[CFO]t_cfo=%f Hz, f_cfo=%f Hz, icfo=%f KHz, cfo=%f KHz\n", FreqCfoTd,FreqCfoFd,FreqIcfo,total_cfo);
2521
2522 return status;
2523
2524 }
INTERN_DVBT_Get_SFO(void)2525 MS_BOOL INTERN_DVBT_Get_SFO(void)
2526 {
2527 MS_U32 Reg_TDP_SFO = 0, Reg_FDP_SFO = 0, Reg_FSA_SFO = 0, Reg_FSA_IN = 0;
2528 MS_BOOL status = true;
2529 MS_U8 reg = 0;
2530 float FreqB = 9.143, FreqS = 45.473; //20.48
2531 float Float_TDP_SFO = 0, Float_FDP_SFO = 0, Float_FSA_SFO = 0, Float_FSA_IN = 0;
2532 float sfo_value = 0;
2533
2534 // get Reg_TDP_SFO,
2535 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCC, ®);
2536 Reg_TDP_SFO = reg;
2537 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCB, ®);
2538 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2539 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0xCA, ®);
2540 Reg_TDP_SFO = (Reg_TDP_SFO<<8)|reg;
2541
2542 Float_TDP_SFO = (float)((MS_S32)(Reg_TDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2543
2544 // get Reg_FDP_SFO,
2545 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x30, ®);
2546 Reg_FDP_SFO = reg;
2547 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2F, ®);
2548 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2549 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x2E, ®);
2550 Reg_FDP_SFO = (Reg_FDP_SFO<<8)|reg;
2551
2552 Float_FDP_SFO = (float)((MS_S32)(Reg_FDP_SFO<<8))/256*FreqB/FreqS*0.0018626;
2553
2554 // get Reg_FSA_SFO,
2555 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8C, ®);
2556 Reg_FSA_SFO = reg;
2557 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8B, ®);
2558 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2559 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8A, ®);
2560 Reg_FSA_SFO = (Reg_FSA_SFO<<8)|reg;
2561
2562 // get Reg_FSA_IN,
2563 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8F, ®);
2564 Reg_FSA_IN = reg;
2565 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x8E, ®);
2566 Reg_FSA_IN = (Reg_FSA_IN<<8)|reg;
2567 Float_FSA_IN = (float)((MS_S32)(Reg_FSA_IN<<19))/512/2048;
2568
2569 //Float_FSA_SFO = (float)((MS_S16)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0037253;
2570 Float_FSA_SFO = (float)((MS_S32)(Reg_FSA_SFO<<8))/256*FreqB/FreqS*0.0018626;
2571
2572 sfo_value = Float_TDP_SFO + Float_FDP_SFO + Float_FSA_SFO;
2573 // ULOGD("DEMOD","\nReg_FSA_SFO = 0x%x\n",Reg_FSA_SFO);
2574 ULOGD("DEMOD","[SFO]tdp_sfo=%f, fdp_sfo=%f, fsa_sfo=%f, Tot_sfo=%f, fsa_sfo_in=%f\n",Float_TDP_SFO,Float_FDP_SFO,Float_FSA_SFO,sfo_value,Float_FSA_IN);
2575
2576
2577 return status;
2578 }
2579
INTERN_DVBT_Get_SYA_status(void)2580 void INTERN_DVBT_Get_SYA_status(void)
2581 {
2582 MS_U8 status = true;
2583 MS_U8 sya_k = 0,reg = 0;
2584 MS_U16 sya_th = 0,len_a = 0,len_b = 0,len_m = 0,sya_offset = 0,tracking_reg = 0;
2585
2586 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x6F, ®);
2587 sya_k = reg;
2588
2589 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x69, ®);
2590 sya_th = reg;
2591 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x68, ®);
2592 sya_th = (sya_th<<8)|reg;
2593
2594 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x95, ®);
2595 sya_offset = reg;
2596 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x94, ®);
2597 sya_offset = (sya_offset<<8)|reg;
2598
2599 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x71, ®);
2600 len_m = reg;
2601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x70, ®);
2602 len_m = (len_m<<8)|reg;
2603
2604 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x87, ®);
2605 len_b = reg;
2606 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x86, ®);
2607 len_b = (len_b<<8)|reg;
2608
2609
2610 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x89, ®);
2611 len_a = reg;
2612 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x88, ®);
2613 len_a = (len_a<<8)|reg;
2614
2615
2616 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x66, ®);
2617 tracking_reg = reg;
2618
2619
2620 ULOGD("DEMOD","[SYA][1]sya_k = 0x%x, sya_th = 0x%x, sya_offset=0x%x\n",sya_k,sya_th,sya_offset);
2621 ULOGD("DEMOD","[SYA][2]track_reg=0x%x, len_m = %d, len_e = %d [%d,%d]\n",tracking_reg,len_m,len_b-len_a,len_a,len_b);
2622
2623 return;
2624 }
2625
INTERN_DVBT_Get_cci_status(void)2626 void INTERN_DVBT_Get_cci_status(void)
2627 {
2628 MS_U8 status = true;
2629 MS_U8 cci_fsweep = 0,cci_kp = 0,reg = 0;
2630
2631 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x08, ®);
2632 cci_fsweep = reg;
2633
2634 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TDE_REG_BASE + 0x0A, ®);
2635 cci_kp = reg;
2636
2637 ULOGD("DEMOD","[CCI]fsweep=0x%x, k=0x%x\n",cci_fsweep,cci_kp);
2638
2639 return;
2640 }
2641
INTERN_DVBT_Show_PRESFO_Info(void)2642 MS_BOOL INTERN_DVBT_Show_PRESFO_Info(void)
2643 {
2644 MS_U8 tmp = 0;
2645 MS_BOOL status = TRUE;
2646 ULOGD("DEMOD","\n[SFO]");
2647 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D0,&tmp);
2648 ULOGD("DEMOD","[%x]",tmp);
2649 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D1,&tmp);
2650 ULOGD("DEMOD","[%x]",tmp);
2651 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D2,&tmp);
2652 ULOGD("DEMOD","[%x]",tmp);
2653 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D3,&tmp);
2654 ULOGD("DEMOD","[%x]",tmp);
2655 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D4,&tmp);
2656 ULOGD("DEMOD","[%x]",tmp);
2657 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D5,&tmp);
2658 ULOGD("DEMOD","[%x]",tmp);
2659 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D6,&tmp);
2660 ULOGD("DEMOD","[%x]",tmp);
2661 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20D7,&tmp);
2662 ULOGD("DEMOD","[%x][End]",tmp);
2663
2664 return status;
2665 }
2666
INTERN_DVBT_Get_Lock_Time_Info(MS_U16 * locktime)2667 MS_BOOL INTERN_DVBT_Get_Lock_Time_Info(MS_U16 *locktime)
2668 {
2669 MS_BOOL status = true;
2670
2671 *locktime = 0xffff;
2672 ULOGD("DEMOD","[dvbt]INTERN_DVBT_Get_Lock_Time_Info not implement\n");
2673
2674 status = false;
2675 return status;
2676 }
2677
2678
INTERN_DVBT_Show_Lock_Time_Info(void)2679 MS_BOOL INTERN_DVBT_Show_Lock_Time_Info(void)
2680 {
2681 MS_U16 locktime = 0;
2682 MS_BOOL status = TRUE;
2683 status &= INTERN_DVBT_Get_Lock_Time_Info(&locktime);
2684 ULOGD("DEMOD","[DVBT]lock_time = %d ms\n",locktime);
2685 return status;
2686 }
2687
INTERN_DVBT_Show_BER_Info(void)2688 MS_BOOL INTERN_DVBT_Show_BER_Info(void)
2689 {
2690 MS_U8 tmp = 0;
2691 MS_BOOL status = TRUE;
2692 ULOGD("DEMOD","\n[BER]");
2693 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C6,&tmp);
2694 ULOGD("DEMOD","[%x,",tmp);
2695 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C7,&tmp);
2696 ULOGD("DEMOD","%x]",tmp);
2697 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C8,&tmp);
2698 ULOGD("DEMOD","[%x,",tmp);
2699 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20C9,&tmp);
2700 ULOGD("DEMOD","%x]",tmp);
2701 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CA,&tmp);
2702 ULOGD("DEMOD","[%x,",tmp);
2703 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x20CB,&tmp);
2704 ULOGD("DEMOD","%x][End]",tmp);
2705
2706 return status;
2707
2708 }
2709
2710
INTERN_DVBT_Show_AGC_Info(void)2711 MS_BOOL INTERN_DVBT_Show_AGC_Info(void)
2712 {
2713 MS_U8 tmp = 0;
2714 MS_U8 agc_k = 0,agc_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0;
2715 MS_U16 if_agc_gain = 0,d1_gain = 0,d2_gain = 0;
2716 MS_U16 if_agc_err = 0;
2717 MS_BOOL status = TRUE;
2718 MS_U8 agc_lock = 0, d1_lock = 0, d2_lock = 0;
2719
2720 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x05,&agc_k);
2721 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x07,&agc_ref);
2722 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x82,&d1_k);
2723 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x84,&d1_ref);
2724 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x00,&d2_k);
2725 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x01,&d2_ref);
2726
2727
2728 // select IF gain to read
2729 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2730 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x03);
2731
2732 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2733 if_agc_gain = tmp;
2734 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2735 if_agc_gain = (if_agc_gain<<8)|tmp;
2736
2737
2738 // select d1 gain to read.
2739 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x8c, &tmp);
2740 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x8c, (tmp&0xF0)|0x02);
2741
2742 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x89, &tmp);
2743 d1_gain = tmp;
2744 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x88, &tmp);
2745 d1_gain = (d1_gain<<8)|tmp;
2746
2747 // select d2 gain to read.
2748 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x06, &tmp);
2749 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTNEXT_REG_BASE + 0x06, (tmp&0xF0)|0x02);
2750
2751 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x09, &tmp);
2752 d2_gain = tmp;
2753 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x08, &tmp);
2754 d2_gain = (d2_gain<<8)|tmp;
2755
2756 // select IF gain err to read
2757 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x16, &tmp);
2758 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FTN_REG_BASE + 0x16, (tmp&0xF0)|0x00);
2759
2760 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x19, &tmp);
2761 if_agc_err = tmp;
2762 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x18, &tmp);
2763 if_agc_err = (if_agc_err<<8)|tmp;
2764
2765 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x1d, &agc_lock);
2766 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTN_REG_BASE + 0x99, &d1_lock);
2767 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FTNEXT_REG_BASE + 0x05, &d2_lock);
2768
2769
2770
2771 ULOGD("DEMOD","[dvbt]agc_k=0x%x, agc_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x\n",
2772 agc_k,agc_ref,d1_k,d1_ref,d2_k,d2_ref);
2773
2774 ULOGD("DEMOD","[dvbt]agc_g=0x%x, d1_g=0x%x, d2_g=0x%x, agc_err=0x%x\n",if_agc_gain,d1_gain,d2_gain,if_agc_err);
2775 ULOGD("DEMOD","[dvbt]agc_lock=0x%x, d1_lock=0x%x, d2_lock=0x%x\n",agc_lock,d1_lock,d2_lock);
2776
2777 return status;
2778
2779 }
2780
INTERN_DVBT_Show_WIN_Info(void)2781 MS_BOOL INTERN_DVBT_Show_WIN_Info(void)
2782 {
2783 MS_U8 tmp = 0;
2784 MS_U8 trigger = 0;
2785 MS_U16 win_len = 0;
2786
2787 MS_BOOL status = TRUE;
2788
2789 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0B,&tmp);
2790 win_len = tmp;
2791 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x0A,&tmp);
2792 win_len = (win_len<<8)|tmp;
2793
2794 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE + 0x08,&trigger);
2795
2796 ULOGD("DEMOD","[dvbt]win_len = %d, trigger=0x%x\n",win_len,trigger);
2797
2798 return status;
2799 }
2800
INTERN_DVBT_Show_td_coeff(void)2801 void INTERN_DVBT_Show_td_coeff(void)
2802 {
2803 MS_U8 status = true;
2804 MS_U8 w1 = 0,w2 = 0,reg = 0;
2805
2806 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2561, ®);
2807 w1 = reg;
2808
2809 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2562, ®);
2810 w2 = reg;
2811
2812 ULOGD("DEMOD","[td]w1=0x%x, w2=0x%x\n",w1,w2);
2813
2814 return;
2815 }
2816
2817 /********************************************************
2818 * Constellation (b2 ~ b0) : 0~2 => QPSK, 16QAM, 64QAM
2819 * Hierarchy (b5 ~ b3)) : 0~3 => None, Aplha1, Aplha2, Aplha4
2820 * LP Code Rate (b8 ~ b6) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
2821 * HP Code Rate (b11 ~ b9) : 0~4 => 1/2, 2/3, 3/4, 5/6, 7/8
2822 * GI (b13 ~ b12) : 0~3 => 1/32, 1/16, 1/8, 1/4
2823 * FFT ( b14) : 0~1 => 2K, 8K
2824 ********************************/
INTERN_DVBT_Show_Modulation_info(void)2825 MS_BOOL INTERN_DVBT_Show_Modulation_info(void)
2826 {
2827 MS_U16 tps_info;
2828
2829 // ULOGD("DEMOD","[DVBT]TPS info, freq=%ld ",CurRFParam.RfFreqInKHz);
2830
2831 if(INTERN_DVBT_Get_TPS_Info( &tps_info))
2832 {
2833 MS_U8 fft = (MS_U8)((tps_info&0x4000)>>14);
2834 MS_U8 constel = tps_info&0x0007;
2835 MS_U8 gi = (MS_U8)((tps_info&0x3000)>>12);
2836 MS_U8 hp_cr = (MS_U8)((tps_info&0x0E00)>>9);
2837 MS_U8 lp_cr = (MS_U8)((tps_info&0x01C0)>>6);
2838 MS_U8 hiearchy = (MS_U8)((tps_info&0x0038)>>3);
2839
2840 ULOGD("DEMOD","tps=0x%x ",tps_info);
2841
2842 switch(fft)
2843 {
2844 case 0:
2845 ULOGD("DEMOD","mode = 2K,");
2846 break;
2847 case 1:
2848 ULOGD("DEMOD","mode = 8K,");
2849 break;
2850 default:
2851 ULOGD("DEMOD","mode = unknow,");
2852 break;
2853 }
2854 switch(constel)
2855 {
2856 case 0:
2857 ULOGD("DEMOD"," QPSK, ");
2858 break;
2859 case 1:
2860 ULOGD("DEMOD","16QAM, ");
2861 break;
2862 case 2:
2863 ULOGD("DEMOD","64QAM, ");
2864 break;
2865 default:
2866 ULOGD("DEMOD","unknow QAM, ");
2867 break;
2868 }
2869 switch(gi)
2870 {
2871 case 0:
2872 ULOGD("DEMOD","GI=1/32, ");
2873 break;
2874 case 1:
2875 ULOGD("DEMOD","GI=1/16, ");
2876 break;
2877 case 2:
2878 ULOGD("DEMOD","GI= 1/8, ");
2879 break;
2880 case 3:
2881 ULOGD("DEMOD","GI= 1/4, ");
2882 break;
2883 default:
2884 ULOGD("DEMOD","unknow GI, ");
2885 break;
2886 }
2887
2888 switch(hp_cr)
2889 {
2890 case 0:
2891 ULOGD("DEMOD","HP_CR=1/2, ");
2892 break;
2893 case 1:
2894 ULOGD("DEMOD","HP_CR=2/3, ");
2895 break;
2896 case 2:
2897 ULOGD("DEMOD","HP_CR=3/4, ");
2898 break;
2899 case 3:
2900 ULOGD("DEMOD","HP_CR=5/6, ");
2901 break;
2902 case 4:
2903 ULOGD("DEMOD","HP_CR=7/8, ");
2904 break;
2905 default:
2906 ULOGD("DEMOD","unknow hp_cr, ");
2907 break;
2908 }
2909
2910 switch(lp_cr)
2911 {
2912 case 0:
2913 ULOGD("DEMOD","LP_CR=1/2, ");
2914 break;
2915 case 1:
2916 ULOGD("DEMOD","LP_CR=2/3, ");
2917 break;
2918 case 2:
2919 ULOGD("DEMOD","LP_CR=3/4, ");
2920 break;
2921 case 3:
2922 ULOGD("DEMOD","LP_CR=5/6, ");
2923 break;
2924 case 4:
2925 ULOGD("DEMOD","LP_CR=7/8, ");
2926 break;
2927 default:
2928 ULOGD("DEMOD","unknow lp_cr, ");
2929 break;
2930 }
2931
2932 ULOGD("DEMOD"," Hiearchy=0x%x\n",hiearchy);
2933
2934 // ULOGD("DEMOD","\n");
2935 return TRUE;
2936 }
2937 else
2938 {
2939 ULOGD("DEMOD","INVALID\n");
2940 return FALSE;
2941 }
2942 }
2943
2944
2945
2946
INTERN_DVBT_Show_BER_PacketErr(void)2947 void INTERN_DVBT_Show_BER_PacketErr(void)
2948 {
2949 float f_ber = 0;
2950 MS_U16 packetErr = 0;
2951 INTERN_DVBT_GetPostViterbiBer(&f_ber);
2952 INTERN_DVBT_GetPacketErr(&packetErr);
2953
2954 ULOGD("DEMOD","[dvbt]ber=%f, Err=%d\n",f_ber, packetErr);
2955 return;
2956 }
2957
INTERN_DVBT_Show_Lock_Info(void)2958 MS_BOOL INTERN_DVBT_Show_Lock_Info(void)
2959 {
2960
2961 ULOGD("DEMOD","[dvbt]INTERN_DVBT_Show_Lock_Info not implement!!!\n");
2962 return false;
2963 }
2964
2965
INTERN_DVBT_Show_Demod_Info(void)2966 MS_BOOL INTERN_DVBT_Show_Demod_Info(void)
2967 {
2968 MS_U8 demod_state = 0;
2969 MS_BOOL status = true;
2970 static MS_U8 counter = 0;
2971
2972 INTERN_DVBT_get_demod_state(&demod_state);
2973
2974 ULOGD("DEMOD","==========[dvbt]state=%d\n",demod_state);
2975 if (demod_state < 5)
2976 {
2977 INTERN_DVBT_Show_Demod_Version();
2978 INTERN_DVBT_Show_AGC_Info();
2979 INTERN_DVBT_Show_ACI_CI();
2980 }
2981 else if(demod_state < 8)
2982 {
2983 INTERN_DVBT_Show_Demod_Version();
2984 INTERN_DVBT_Show_AGC_Info();
2985 INTERN_DVBT_Show_ACI_CI();
2986 INTERN_DVBT_Show_ChannelLength();
2987 INTERN_DVBT_Get_CFO();
2988 INTERN_DVBT_Get_SFO();
2989 INTERN_DVBT_Show_td_coeff();
2990 }
2991 else if(demod_state < 11)
2992 {
2993 INTERN_DVBT_Show_Demod_Version();
2994 INTERN_DVBT_Show_AGC_Info();
2995 INTERN_DVBT_Show_ACI_CI();
2996 INTERN_DVBT_Show_ChannelLength();
2997 INTERN_DVBT_Get_CFO();
2998 INTERN_DVBT_Get_SFO();
2999 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3000 INTERN_DVBT_Get_SYA_status();
3001 INTERN_DVBT_Show_td_coeff();
3002 }
3003 else if((demod_state == 11) && ((counter%4) == 0))
3004 {
3005 INTERN_DVBT_Show_Demod_Version();
3006 INTERN_DVBT_Show_AGC_Info();
3007 INTERN_DVBT_Show_ACI_CI();
3008 INTERN_DVBT_Show_ChannelLength();
3009 INTERN_DVBT_Get_CFO();
3010 INTERN_DVBT_Get_SFO();
3011 INTERN_DVBT_Show_FD_CH_LEN_S_SEL();
3012 INTERN_DVBT_Get_SYA_status();
3013 INTERN_DVBT_Show_td_coeff();
3014 INTERN_DVBT_Show_Modulation_info();
3015 INTERN_DVBT_Show_BER_PacketErr();
3016 }
3017 else
3018 status = false;
3019
3020 ULOGD("DEMOD","===========================\n");
3021 counter++;
3022
3023 return status;
3024 }
3025 #endif
3026
3027