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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////
96 //
97 /// @file INTERN_DVBT.c
98 /// @brief INTERN_DVBT DVBT
99 /// @author MStar Semiconductor, Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////
102 //0312
103
104 #define _INTERN_DVBS_C_
105 #ifdef MSOS_TYPE_LINUX
106 #include <math.h>
107 #endif
108 #include "ULog.h"
109 #include "MsCommon.h"
110 #include "MsIRQ.h"
111 #include "MsOS.h"
112 //#include "apiPWS.h"
113
114 #include "MsTypes.h"
115 #include "drvBDMA.h"
116 //#include "drvIIC.h"
117 //#include "msAPI_Tuner.h"
118 //#include "msAPI_MIU.h"
119 //#include "BinInfo.h"
120 //#include "halVif.h"
121 #include "drvDMD_INTERN_DVBS.h"
122 #include "halDMD_INTERN_DVBS.h"
123 #include "halDMD_INTERN_common.h"
124
125 #include "drvMMIO.h"
126 //#include "TDAG4D01A_SSI_DVBT.c"
127 #include "drvDMD_VD_MBX.h"
128 //-----------------------------------------------------------------------
129 #define BIN_ID_INTERN_DVBS_DEMOD BIN_ID_INTERN_DVBS
130
131 //For DVBS
132 //#define DVBT2FEC_REG_BASE 0x3300
133 #define DVBS2OPPRO_REG_BASE 0x3E00
134 #define TOP_REG_BASE 0x2000 //DMDTOP
135 #define REG_BACKEND 0x1F00//_REG_BACKEND
136 #define DVBSFEC_REG_BASE 0x3F00
137 #define DVBS2FEC_REG_BASE 0x3300
138 #define DVBS2_REG_BASE 0x3A00
139 #define DVBS2_INNER_REG_BASE 0x3B00
140 #define DVBS2_INNER_EXT_REG_BASE 0x3C00
141 #define DVBS2_INNER_EXT2_REG_BASE 0x3D00
142 //#define DVBSTFEC_REG_BASE 0x2300 //DVBTFEC
143 #define FRONTEND_REG_BASE 0x2800
144 #define FRONTENDEXT_REG_BASE 0x2900
145 #define FRONTENDEXT2_REG_BASE 0x2A00
146 #define DMDANA_REG_BASE 0x2E00 //DMDDTOP//reg_dmdana.xls
147 #define DVBTM_REG_BASE 0x3400
148
149 #define SAMPLING_RATE_FS (144000)//(108000)//(96000)
150 #define INTERN_DVBS_DEMOD_WAIT_TIMEOUT (6000)
151 #define INTERN_DVBS_TUNER_WAIT_TIMEOUT (50)
152
153 //#define DVBS2_Function (1)
154 //#define MSB131X_ADCPLL_IQ_SWAP 0
155 //#define INTERN_DVBS_TS_DATA_SWAP 0
156
157 //#define MS_DEBUG //enable debug dump
158
159 #ifdef MS_DEBUG
160 #define DBG_INTERN_DVBS(x) x
161 #define DBG_GET_SIGNAL_DVBS(x) x
162 #define DBG_INTERN_DVBS_TIME(x) x
163 #define DBG_INTERN_DVBS_LOCK(x) x
164 #define INTERN_DVBS_INTERNAL_DEBUG 1
165 #else
166 #define DBG_INTERN_DVBS(x) //x
167 #define DBG_GET_SIGNAL_DVBS(x) //x
168 #define DBG_INTERN_DVBS_TIME(x) //x
169 #define DBG_INTERN_DVBS_LOCK(x) //x
170 #define INTERN_DVBS_INTERNAL_DEBUG 0
171 #endif
172 //----------------------------------------------------------
173 #define DBG_DUMP_LOAD_DSP_TIME 0
174
175
176 #define SIGNAL_LEVEL_OFFSET 0.00f
177 #define TAKEOVERPOINT -60.0f
178 #define TAKEOVERRANGE 0.5f
179 #define LOG10_OFFSET -0.21f
180 #define INTERN_DVBS_USE_SAR_3_ENABLE 0
181 //extern MS_U32 msAPI_Timer_GetTime0(void);
182 //#define INTERN_DVBS_GET_TIME msAPI_Timer_GetTime0()
183
184
185 //Debug Info
186 //Lock/Done Flag
187 #define AGC_LOCK 0x28170100
188 #define DAGC0_LOCK 0x283B0001
189 #define DAGC1_LOCK 0x285B0001
190 #define DAGC2_LOCK 0x28620001 //ACIDAGC 1 2
191 #define DAGC3_LOCK 0x286E0001
192 #define DCR_LOCK 0x28220100
193 #define COARSE_SYMBOL_RATE_DONE 0x2A200001 //CSRD 1 2
194 #define FINE_SYMBOL_RATE_DONE 0x2A200008 //FSRD 1 2
195 #define POWER4CFO_DONE 0x29280100 //POWER4CFO 1 2
196 //#define CLOSE_COARSE_CFO_LOCK 0x244E0001
197 #define TR_LOCK 0x3B0E0100 //TR 1 2
198 #define PR_LOCK 0x3B401000
199 #define FRAME_SYNC_ACQUIRE 0x3B300001
200 #define EQ_LOCK 0x3B5A1000
201 #define P_SYNC_LOCK 0x22160002
202 #define IN_SYNC_LOCK 0x3F0D8000
203
204 //AGC / DAGC
205 #define DEBUG_SEL_IF_AGC_GAIN 0x28260003
206 #define DEBUG_SEL_AGC_ERR 0x28260004
207 #define DEBUG_OUT_AGC 0x2828
208
209 #define DEBUG_SEL_DAGC0_GAIN 0x28E80003
210 #define DEBUG_SEL_DAGC0_ERR 0x28E80001
211 #define DEBUG_SEL_DAGC0_PEAK_MEAN 0x28E80005
212 #define DEBUG_OUT_DAGC0 0x2878
213
214 #define DEBUG_SEL_DAGC1_GAIN 0x28E80003//???
215 #define DEBUG_SEL_DAGC1_ERR 0x28E80001
216 #define DEBUG_SEL_DAGC1_PEAK_MEAN 0x28E80005
217 #define DEBUG_OUT_DAGC1 0x28B8
218
219 #define DEBUG_SEL_DAGC2_GAIN 0x28E80003
220 #define DEBUG_SEL_DAGC2_ERR 0x28E80001
221 #define DEBUG_SEL_DAGC2_PEAK_MEAN 0x28E80005
222 #define DEBUG_OUT_DAGC2 0x28C4
223
224 #define DEBUG_SEL_DAGC3_GAIN 0x29DA0003
225 #define DEBUG_SEL_DAGC3_ERR 0x29DA0001
226 #define DEBUG_SEL_DAGC3_PEAK_MEAN 0x29DA0005
227 #define DEBUG_OUT_DAGC3 0x29DC
228
229 #define INNER_DEBUG_SEL_TR 0x24080D00 //TR
230 #define DEBUG_SEL_TR_SFO_CONVERGE 0x24080B00
231 #define DEBUG_SEL_TR_INPUT 0x24080F00
232
233 #define FRONTEND_FREEZE_DUMP 0x27028000
234 #define INNER_FREEZE_DUMP 0x24080010
235
236 #define DCR_OFFSET 0x2740
237 #define INNER_DEBUG_SEL 0x2408
238 #define INNEREXT_FINEFE_DBG_OUT0 0x2550
239 #define INNEREXT_FINEFE_DBG_OUT2 0x2552
240 #define INNEREXT_FINEFE_KI_FF0 0x2556
241 #define INNEREXT_FINEFE_KI_FF2 0x2558
242 #define INNEREXT_FINEFE_KI_FF4 0x255A
243 #define INNER_PR_DEBUG_OUT0 0x2486
244 #define INNER_PR_DEBUG_OUT2 0x2488
245
246 #define IIS_COUNT0 0x2746
247 #define IIS_COUNT2 0x2748
248 #define IQB_PHASE 0x2766
249 #define IQB_GAIN 0x2768
250 #define TR_INDICATOR_FF0 0x2454
251 #define TR_INDICATOR_FF2 0x2456
252 #define INNER_TR_LOPF_VALUE_DEBUG0 0x2444
253 #define INNER_TR_LOPF_VALUE_DEBUG2 0x2446
254 #define INNER_TR_LOPF_VALUE_DEBUG4 0x2448
255 //------------------------------------------------------------
256 //Init Mailbox parameter.
257 #define INTERN_DVBS_TS_SERIAL_INVERSION 0
258 //For Parameter Init Setting
259 #define A_S2_ZIF_EN 0x01 //[0]
260 #define A_S2_RF_AGC_EN 0x00 //[0]
261 #define A_S2_DCR_EN 0x00 //[0] 0=Auto :1=Force
262 #define A_S2_IQB_EN 0x01 //[2]
263 #define A_S2_IIS_EN 0x00 //[0]
264 #define A_S2_CCI_EN 0x00 //[0] 0:1=Enable
265 #define A_S2_FORCE_ACI_SELECT 0xFF //[3:0] 0xFF=OFF(internal default)
266 #define A_S2_IQ_SWAP 0x01 //[0]
267 #define A_S2_AGC_REF_EXT_0 0x00 //[7:0] //0x00 0x90
268 #define A_S2_AGC_REF_EXT_1 0x02 //[11:8] //0x02 0x07
269 #define A_S2_AGC_K 0x07 //[15:12]
270 #define A_S2_ADCI_GAIN 0x0F //[4:0]
271 #define A_S2_ADCQ_GAIN 0x0F //[12:8]
272 #define A_S2_SRD_SIG_SRCH_RNG 0x6A //[7:0]
273 #define A_S2_SRD_DC_EXC_RNG 0x16 //[7:0]
274 //FRONTENDEXT_SRD_FRC_CFO
275 #define A_S2_FORCE_CFO_0 0x00 //[7:0]
276 #define A_S2_FORCE_CFO_1 0x00 //[11:8]
277 #define A_S2_DECIMATION_NUM 0x00 //[3:0] 00=(Internal Default)
278 #define A_S2_PSD_SMTH_TAP 0x29 //[6:0] Bit7 no define.
279 //CCI Parameter
280 //Set_Tuner_BW=(((U16)REG_BASE[DIG_SWUSE1FH]<<8)|REG_BASE[DIG_SWUSE1FL]);
281 #define A_S2_CCI_FREQN_0_L 0x00 //[7:0]
282 #define A_S2_CCI_FREQN_0_H 0x00 //[11:8]
283 #define A_S2_CCI_FREQN_1_L 0x00 //[7:0]
284 #define A_S2_CCI_FREQN_1_H 0x00 //[11:8]
285 #define A_S2_CCI_FREQN_2_L 0x00 //[7:0]
286 #define A_S2_CCI_FREQN_2_H 0x00 //[11:8]
287 //Inner TR Parameter
288 #define A_S2_TR_LOPF_KP 0x00 //[4:0] 00=(Internal Default)
289 #define A_S2_TR_LOPF_KI 0x00 //[4:0] 00=(Internal Default)
290 //Inner FineFE Parameter
291 #define A_S2_FINEFE_KI_SWITCH_0 0x00 //[15:12] 00=(Internal Default)
292 #define A_S2_FINEFE_KI_SWITCH_1 0x00 //[3:0] 00=(Internal Default)
293 #define A_S2_FINEFE_KI_SWITCH_2 0x00 //[7:4] 00=(Internal Default)
294 #define A_S2_FINEFE_KI_SWITCH_3 0x00 //[11:8] 00=(Internal Default)
295 #define A_S2_FINEFE_KI_SWITCH_4 0x00 //[15:12] 00=(Internal Default)
296 //Inner PR KP Parameter
297 #define A_S2_PR_KP_SWITCH_0 0x00 //[11:8] 00=(Internal Default)
298 #define A_S2_PR_KP_SWITCH_1 0x00 //[15:12] 00=(Internal Default)
299 #define A_S2_PR_KP_SWITCH_2 0x00 //[3:0] 00=(Internal Default)
300 #define A_S2_PR_KP_SWITCH_3 0x00 //[7:4] 00=(Internal Default)
301 #define A_S2_PR_KP_SWITCH_4 0x00 //[11:8] 00=(Internal Default)
302 //Inner FS Parameter
303 #define A_S2_FS_GAMMA 0x10 //[7:0]
304 #define A_S2_FS_ALPHA0 0x10 //[7:0]
305 #define A_S2_FS_ALPHA1 0x10 //[7:0]
306 #define A_S2_FS_ALPHA2 0x10 //[7:0]
307 #define A_S2_FS_ALPHA3 0x10 //[7:0]
308
309 #define A_S2_FS_H_MODE_SEL 0x01 //[0]
310 #define A_S2_FS_OBSWIN 0x08 //[12:8]
311 #define A_S2_FS_PEAK_DET_TH_L 0x00 //[7:0]
312 #define A_S2_FS_PEAK_DET_TH_H 0x01 //[15:8]
313 #define A_S2_FS_CONFIRM_NUM 0x01 //[3:0]
314 //Inner EQ Parameter
315 #define A_S2_EQ_MU_FFE_DA 0x00 //[3:0] 00=(Internal Default)
316 #define A_S2_EQ_MU_FFE_DD 0x00 //[7:4] 00=(Internal Default)
317 #define A_S2_EQ_ALPHA_SNR_DA 0x00 //[7:4] 00=(Internal Default)
318 #define A_S2_EQ_ALPHA_SNR_DD 0x00 //[11:8] 00=(Internal Default)
319 //Outer FEC Parameter
320 #define A_S2_FEC_ALFA 0x00 //[12:8]
321 #define A_S2_FEC_BETA 0x01 //[7:4]
322 #define A_S2_FEC_SCALING_LLR 0x00 //[7:0] 00=(Internal Default)
323 //TS Parameter
324 #if INTERN_DVBS_TS_SERIAL_INVERSION
325 #define A_S2_TS_SERIAL 0x01 //[0]
326 #else
327 #define A_S2_TS_SERIAL 0x00 //[0]
328 #endif
329 #define A_S2_TS_CLK_RATE 0x00
330 #define A_S2_TS_OUT_INV 0x00 //[5]
331 #define A_S2_TS_DATA_SWAP 0x00 //[5]
332 //Rev Parameter
333
334 #define A_S2_FW_VERSION_L 0x00 //From FW
335 #define A_S2_FW_VERSION_H 0x00 //From FW
336 #define A_S2_CHIP_VERSION 0x01
337 #define A_S2_FS_L 0x00
338 #define A_S2_FS_H 0x00
339 #define A_S2_MANUAL_TUNE_SYMBOLRATE_L 0x20
340 #define A_S2_MANUAL_TUNE_SYMBOLRATE_H 0x4E
341
342 MS_U8 INTERN_DVBS_DSPREG[] =
343 {
344 A_S2_ZIF_EN, A_S2_RF_AGC_EN, A_S2_DCR_EN, A_S2_IQB_EN, A_S2_IIS_EN, A_S2_CCI_EN, A_S2_FORCE_ACI_SELECT, A_S2_IQ_SWAP, // 00H ~ 07H
345 A_S2_AGC_REF_EXT_0, A_S2_AGC_REF_EXT_1, A_S2_AGC_K, A_S2_ADCI_GAIN, A_S2_ADCQ_GAIN, A_S2_SRD_SIG_SRCH_RNG, A_S2_SRD_DC_EXC_RNG, A_S2_FORCE_CFO_0, // 08H ~ 0FH
346 A_S2_FORCE_CFO_1, A_S2_DECIMATION_NUM, A_S2_PSD_SMTH_TAP, A_S2_CCI_FREQN_0_L, A_S2_CCI_FREQN_0_H, A_S2_CCI_FREQN_1_L, A_S2_CCI_FREQN_1_H, A_S2_CCI_FREQN_2_L, // 10H ~ 17H
347 A_S2_CCI_FREQN_2_H, A_S2_TR_LOPF_KP, A_S2_TR_LOPF_KI, A_S2_FINEFE_KI_SWITCH_0, A_S2_FINEFE_KI_SWITCH_1, A_S2_FINEFE_KI_SWITCH_2, A_S2_FINEFE_KI_SWITCH_3, A_S2_FINEFE_KI_SWITCH_4, // 18H ~ 1FH
348 A_S2_PR_KP_SWITCH_0, A_S2_PR_KP_SWITCH_1, A_S2_PR_KP_SWITCH_2, A_S2_PR_KP_SWITCH_3, A_S2_PR_KP_SWITCH_4, A_S2_FS_GAMMA, A_S2_FS_ALPHA0, A_S2_FS_ALPHA1, // 20H ~ 27H
349 A_S2_FS_ALPHA2, A_S2_FS_ALPHA3, A_S2_FS_H_MODE_SEL, A_S2_FS_OBSWIN, A_S2_FS_PEAK_DET_TH_L, A_S2_FS_PEAK_DET_TH_H, A_S2_FS_CONFIRM_NUM, A_S2_EQ_MU_FFE_DA, // 28h ~ 2FH
350 A_S2_EQ_MU_FFE_DD, A_S2_EQ_ALPHA_SNR_DA, A_S2_EQ_ALPHA_SNR_DD, A_S2_FEC_ALFA, A_S2_FEC_BETA, A_S2_FEC_SCALING_LLR, A_S2_TS_SERIAL, A_S2_TS_CLK_RATE, // 30H ~ 37H
351 A_S2_TS_OUT_INV, A_S2_TS_DATA_SWAP, A_S2_FW_VERSION_L, A_S2_FW_VERSION_H, A_S2_CHIP_VERSION, A_S2_FS_L, A_S2_FS_H, A_S2_MANUAL_TUNE_SYMBOLRATE_L, // 38H ~ 3CH
352 A_S2_MANUAL_TUNE_SYMBOLRATE_H,
353 };
354
355 /****************************************************************
356 *Local Variables *
357 ****************************************************************/
358
359 /*
360 static MS_U16 _u16SignalLevel[185][2]=
361 {//AV2028 SR=22M, 2/3 CN=5.9
362 {32100, 920},{32200, 915},{32350, 910},{32390, 905},{32480, 900},{32550, 895},{32620, 890},{32680, 885},{32750, 880},{32830, 875},
363 {32930, 870},{33010, 865},{33100, 860},{33200, 855},{33310, 850},{33410, 845},{33520, 840},{33640, 835},{33770, 830},{33900, 825},
364 {34030, 820},{34150, 815},{34290, 810},{34390, 805},{34490, 800},{34580, 795},{34700, 790},{34800, 785},{34880, 780},{34940, 775},
365 {35030, 770},{35130, 765},{35180, 760},{35260, 755},{35310, 750},{35340, 745},{35380, 740},{35400, 735},{35450, 730},{35550, 725},
366 {35620, 720},{35700, 715},{35800, 710},{35890, 705},{36000, 700},{36120, 695},{36180, 690},{36280, 685},{36400, 680},{36570, 675},
367 {36730, 670},{36910, 665},{37060, 660},{37100, 655},{37260, 650},{37340, 645},{37410, 640},{37580, 635},{37670, 630},{37700, 625},
368 {37750, 620},{37800, 615},{37860, 610},{37980, 605},{38050, 600},{38170, 595},{38370, 590},{38540, 585},{38710, 580},{38870, 575},
369 {39020, 570},{39070, 565},{39100, 560},{39180, 555},{39280, 550},{39460, 545},{39510, 540},{39600, 535},{39620, 530},{39680, 525},
370 {39720, 520},{39830, 515},{39880, 510},{39930, 505},{39960, 500},{40000, 495},{40200, 490},{40360, 485},{40540, 480},{40730, 475},
371 {40880, 470},{41020, 465},{41150, 460},{41280, 455},{41410, 450},{41520, 445},{41620, 440},{41730, 435},{41840, 430},{41930, 425},
372 {42010, 420},{42100, 415},{42180, 410},{42260, 405},{42350, 400},{42440, 395},{42520, 390},{42580, 385},{42660, 380},{42730, 375},
373 {42800, 370},{42870, 365},{42940, 360},{43000, 355},{43060, 350},{43130, 345},{43180, 340},{43250, 335},{43310, 330},{43370, 325},
374 {43420, 320},{43460, 315},{43520, 310},{43570, 305},{43620, 300},{43660, 295},{43710, 290},{43750, 285},{43810, 280},{43860, 275},
375 {43910, 270},{43940, 265},{43990, 260},{44020, 255},{44060, 250},{44110, 245},{44140, 240},{44190, 235},{44230, 230},{44270, 225},
376 {44320, 220},{44370, 215},{44400, 210},{44450, 205},{44490, 200},{44530, 195},{44590, 190},{44630, 185},{44660, 180},{44720, 175},
377 {44750, 170},{44790, 165},{44830, 160},{44880, 155},{44910, 150},{44960, 145},{45000, 140},{45030, 135},{45070, 130},{45100, 125},
378 {45130, 120},{45160, 115},{45200, 110},{45240, 105},{45270, 100},{45300, 95},{45330, 90},{45360, 85},{45400, 80},{45430, 75},
379 {45460, 70},{45490, 65},{45530, 60},{45560, 55},{45590, 50},{45630, 45},{45670, 40},{45690, 35},{45740, 30},{45760, 25},
380 {45800, 20},{45830, 15},{45860, 10},{45880, 5},{45920, 0}
381 };
382 */
383 MS_U8 u8DemodLockFlag;
384 MS_U8 modulation_order;
385 MS_BOOL _bDemodType=FALSE;//DVBS:FALSE ; S2:TRUE
386 //static MS_BOOL TPSLock = 0;
387 static MS_U32 u32ChkScanTimeStartDVBS = 0;
388 MS_U8 g_dvbs_lock = 0;
389 //static float intern_dvb_s_qam_ref[] = {3.0, 0.0, 0.0, 0.0, 0.0, 80.0}; //16q,32q,64q,128q,256q, and others
390 static MS_U8 _u8_DVBS2_CurrentCodeRate;
391 static MS_U8 _u8ToneBurstFlag=0;
392
393 //static float _fPostBer=0;
394 //static float _f_DVBS_CurrentSNR=0;
395 static MS_U16 _u16BlindScanStartFreq=0;
396 static MS_U16 _u16BlindScanEndFreq=0;
397 static MS_U16 _u16TunerCenterFreq=0;
398 MS_U16 _u16ChannelInfoIndex=0;
399 //Debug Only+
400 static MS_U16 _u16NextCenterFreq=0;
401 MS_U16 _u16LockedSymbolRate=0;
402 MS_U16 _u16LockedCenterFreq=0;
403 static MS_U16 _u16PreLockedHB=0;
404 static MS_U16 _u16PreLockedLB=0;
405 static MS_U16 _u16CurrentSymbolRate=0;
406 MS_S16 _s16CurrentCFO=0;
407 static MS_U16 _u16CurrentStepSize=0;
408 //Debug Only-
409 MS_U16 _u16ChannelInfoArray[2][1000];
410
411 //static MS_U32 _u32CurrentSR=0;
412 static MS_BOOL _bSerialTS=FALSE;
413 static MS_BOOL _bTSDataSwap=FALSE;
414
415 //Global Variables
416 S_CMDPKTREG gsCmdPacketDVBS;
417 //MS_U8 gCalIdacCh0, gCalIdacCh1;
418 static MS_BOOL bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
419 static MS_U32 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
420 extern MS_U32 u32DMD_DVBS2_DJB_START_ADDR;
421 #ifdef INTERN_DVBS_LOAD_FW_FROM_CODE_MEMORY
422 MS_U8 INTERN_DVBS_table[] =
423 {
424 #include "fwDMD_INTERN_DVBS.dat"
425 };
426
427 #endif
428
429 MS_BOOL INTERN_DVBS_Show_Demod_Version(void);
430 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode);
431 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType);
432 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate);
433 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate);
434 MS_BOOL INTERN_DVBS_GetCurrentSymbolRateOffset(MS_U16 *pData);
435
436 #if (INTERN_DVBS_INTERNAL_DEBUG)
437 void INTERN_DVBS_info(void);
438 MS_BOOL INTERN_DVBS_Show_AGC_Info(void);
439 #endif
440
441 //------------------------------------------------------------------
442 // System Info Function
443 //------------------------------------------------------------------
444 //=====================================================================================
INTERN_DVBS_DSPReg_Init(const MS_U8 * u8DVBS_DSPReg,MS_U8 u8Size)445 MS_U16 INTERN_DVBS_DSPReg_Init(const MS_U8 *u8DVBS_DSPReg, MS_U8 u8Size)
446 {
447 #if 0
448 MS_U8 idx = 0, u8RegRead = 0, u8RegWrite = 0, u8Mask = 0;
449 #endif
450 MS_U8 status = true;
451 #if 0
452 MS_U16 u16DspAddr = 0;
453 #endif
454 DBG_INTERN_DVBS(printf("INTERN_DVBS_DSPReg_Init\n"));
455
456 #if 0//def MS_DEBUG
457 {
458 MS_U8 u8buffer[256];
459 printf("INTERN_DVBS_DSPReg_Init Reset\n");
460 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
461 MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, 0);
462
463 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
464 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
465 printf("INTERN_DVBS_DSPReg_Init ReadBack, should be all 0\n");
466 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
467 printf("%x ", u8buffer[idx]);
468 printf("\n");
469
470 printf("INTERN_DVBS_DSPReg_Init Value\n");
471 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
472 printf("%x ", INTERN_DVBS_DSPREG[idx]);
473 printf("\n");
474 }
475 #endif
476
477 //for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
478 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(idx, INTERN_DVBS_DSPREG[idx]);
479
480 // readback to confirm.
481 // ~read this to check mailbox initial values
482 #if 0
483 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
484 {
485 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &u8RegRead);
486 if (u8RegRead != INTERN_DVBS_DSPREG[idx])
487 {
488 DBG_INTERN_DVBS(printf("[Error]INTERN_DVBS_DSPReg_Init, idx=%d, drv_val=0x%x, firmware_val=0x%x\n",idx,INTERN_DVBS_DSPREG[idx],u8RegRead));
489 }
490 }
491 #endif
492 #if 0
493 if (u8DVBS_DSPReg != NULL)
494 {
495 if (1 == u8DVBS_DSPReg[0])
496 {
497 u8DVBS_DSPReg+=2;
498 for (idx = 0; idx<u8Size; idx++)
499 {
500 u16DspAddr = *u8DVBS_DSPReg;
501 u8DVBS_DSPReg++;
502 u16DspAddr = (u16DspAddr) + ((*u8DVBS_DSPReg)<<8);
503 u8DVBS_DSPReg++;
504 u8Mask = *u8DVBS_DSPReg;
505 u8DVBS_DSPReg++;
506 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(u16DspAddr, &u8RegRead);
507 u8RegWrite = (u8RegRead & (~u8Mask)) | ((*u8DVBS_DSPReg) & (u8Mask));
508 u8DVBS_DSPReg++;
509 DBG_INTERN_DVBS(printf("DSP addr:%x mask:%x read:%x write:%x\n", u16DspAddr, u8Mask, u8RegRead, u8RegWrite));
510 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(u16DspAddr, u8RegWrite);
511 }
512 }
513 else
514 {
515 DBG_INTERN_DVBS(printf("FATAL: parameter version incorrect\n"));
516 }
517 }
518 #endif
519 #if 0//def MS_DEBUG
520 {
521 MS_U8 u8buffer[256];
522 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
523 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(idx, &(u8buffer[idx]));
524 printf("INTERN_DVBC_DSPReg_Init ReadBack\n");
525 for (idx = 0; idx<sizeof(INTERN_DVBS_DSPREG); idx++)
526 printf("%x ", u8buffer[idx]);
527 printf("\n");
528 }
529 #endif
530
531 #if 0//def MS_DEBUG
532 {
533 MS_U8 u8buffer[256];
534 for (idx = 0; idx<128; idx++)
535 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(0x2380+idx, &(u8buffer[idx]));
536 printf("INTERN_DVBS_DSPReg_Init ReadReg 0x2000~0x207F\n");
537 for (idx = 0; idx<128; idx++)
538 {
539 printf("%x ", u8buffer[idx]);
540 if ((idx & 0xF) == 0xF) printf("\n");
541 }
542 printf("\n");
543 }
544 #endif
545 return status;
546 }
547
548 /***********************************************************************************
549 Subject: Command Packet Interface
550 Function: INTERN_DVBS_Cmd_Packet_Send
551 Parmeter:
552 Return: MS_BOOL
553 Remark:
554 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG * pCmdPacket,MS_U8 param_cnt)555 MS_BOOL INTERN_DVBS_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt)
556 {
557 MS_U8 status = true, indx;
558 MS_U8 reg_val, timeout = 0;
559 return true;
560
561 // ==== Command Phase ===================
562 DBG_INTERN_DVBS(ULOGD("DEMOD","--->INTERN_DVBS (cmd=0x%x)(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,) \n",pCmdPacket->cmd_code,
563 pCmdPacket->param[0],pCmdPacket->param[1],
564 pCmdPacket->param[2],pCmdPacket->param[3],
565 pCmdPacket->param[4],pCmdPacket->param[5] ));
566
567 // wait _BIT_END clear
568 do
569 {
570 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
571 if((reg_val & _BIT_END) != _BIT_END)
572 {
573 break;
574 }
575 MsOS_DelayTask(5);
576 if (timeout > 200)
577 {
578 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_END clear' \n"));
579 return false;
580 }
581 timeout++;
582 } while (1);
583
584 // set cmd_3:0 and _BIT_START
585 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
586 reg_val = (reg_val & 0x0f)|(pCmdPacket->cmd_code << 4)|_BIT_START;
587 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val);
588
589
590 //DBG_INTERN_DVBS(printf("demod_config: cmd_code = %bx\n", pCmdPacket->cmd_code));
591 // wait _BIT_START clear
592 do
593 {
594 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
595 if((reg_val & _BIT_START) != _BIT_START)
596 {
597 break;
598 }
599 MsOS_DelayTask(10);
600 if (timeout > 200)
601 {
602 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_START clear' \n"));
603 return false;
604 }
605 timeout++;
606 } while (1);
607
608 // ==== Data Phase ======================
609
610 HAL_DMD_RIU_WriteByte(REG_CMD_ADDR, 0x00);
611
612 for (indx = 0; indx < param_cnt; indx++)
613 {
614 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_ADDR);
615 //DBG_INTERN_DVBS(printf("demod_config: param[%bd] = %bx\n", reg_val, pCmdPacket->param[indx]));
616
617 // set param[indx] and _BIT_DRQ
618 HAL_DMD_RIU_WriteByte(REG_CMD_DATA, pCmdPacket->param[indx]);
619 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
620 HAL_DMD_RIU_WriteByte(REG_DTA_CTRL, reg_val|_BIT_DRQ);
621
622 // wait _BIT_DRQ clear
623 do
624 {
625 reg_val = HAL_DMD_RIU_ReadByte(REG_DTA_CTRL);
626 if ((reg_val & _BIT_DRQ) != _BIT_DRQ)
627 {
628 break;
629 }
630 MsOS_DelayTask(5);
631 if (timeout > 200)
632 {
633 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Cmd_Packet_Send fail on 'wait _BIT_DRQ clear' \n"));
634 return false;
635 }
636 timeout++;
637 } while (1);
638 }
639
640 // ==== End Phase =======================
641
642 // set _BIT_END to finish command
643 reg_val = HAL_DMD_RIU_ReadByte(REG_CMD_CTRL);
644 HAL_DMD_RIU_WriteByte(REG_CMD_CTRL, reg_val|_BIT_END);
645
646 return status;
647 }
648
649 /***********************************************************************************
650 Subject: Command Packet Interface
651 Function: INTERN_DVBS_Cmd_Packet_Exe_Check
652 Parmeter:
653 Return: MS_BOOL
654 Remark:
655 ************************************************************************************/
INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL * cmd_done)656 MS_BOOL INTERN_DVBS_Cmd_Packet_Exe_Check(MS_BOOL* cmd_done)
657 {
658 return TRUE;
659 }
660
661 /***********************************************************************************
662 Subject: SoftStop
663 Function: INTERN_DVBS_SoftStop
664 Parmeter:
665 Return: MS_BOOL
666 Remark:
667 ************************************************************************************/
INTERN_DVBS_SoftStop(void)668 MS_BOOL INTERN_DVBS_SoftStop ( void )
669 {
670 #if 1
671 MS_U16 u16WaitCnt=0;
672
673 if (HAL_DMD_RIU_ReadByte(MBRegBase + 0x00))
674 {
675 DBG_INTERN_DVBS(ULOGD("DEMOD",">> MB Busy!\n"));
676 return FALSE;
677 }
678
679 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0xA5); // MB_CNTL set read mode
680
681 HAL_DMD_RIU_WriteByte(0x103483, 0x02); // assert interrupt to VD MCU51
682 HAL_DMD_RIU_WriteByte(0x103483, 0x00); // de-assert interrupt to VD MCU51
683
684 while(HAL_DMD_RIU_ReadByte(MBRegBase + 0x00)!= 0x5A) // wait MB_CNTL set done
685 {
686 if (u16WaitCnt++ >= 0xFFF)// 0xFF)
687 {
688 DBG_INTERN_DVBS(ULOGD("DEMOD",">> DVBT SoftStop Fail!\n"));
689 return FALSE;
690 }
691 }
692
693 //HAL_DMD_RIU_WriteByte(0x103460, 0x01); // reset VD_MCU
694 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00, 0x00); // MB_CNTL clear
695 #endif
696 return TRUE;
697 }
698
699 /***********************************************************************************
700 Subject: Reset
701 Function: INTERN_DVBC_Reset
702 Parmeter:
703 Return: MS_BOOL
704 Remark:
705 ************************************************************************************/
706 extern void HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake(void);
707
INTERN_DVBS_Reset(void)708 MS_BOOL INTERN_DVBS_Reset ( void )// no midify
709 {
710 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_reset\n"));
711
712 DBG_INTERN_DVBS_TIME(ULOGD("DEMOD","INTERN_DVBS_Reset, t = %d\n",MsOS_GetSystemTime()));
713
714 //INTERN_DVBS_SoftStop();
715
716
717 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset DMD_MCU
718
719 MsOS_DelayTask(1);
720 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00); // clear MB_CNTL
721
722 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00);
723 MsOS_DelayTask(5);
724
725 HAL_SYS_DMD_VD_MBX_DVB_WaitHandShake();
726 HAL_DMD_RIU_WriteByte(MBRegBase + 0x00 , 0x00);
727
728 u32ChkScanTimeStartDVBS = MsOS_GetSystemTime();
729 g_dvbs_lock = 0;
730
731 return TRUE;
732 }
733
734 /***********************************************************************************
735 Subject: Exit
736 Function: INTERN_DVBC_Exit
737 Parmeter:
738 Return: MS_BOOL
739 Remark:
740 ************************************************************************************/
INTERN_DVBS_Exit(void)741 MS_BOOL INTERN_DVBS_Exit ( void )
742 {
743 MS_U8 u8Data=0;
744 MS_U8 u8Data_temp=0;
745
746 u8Data_temp=HAL_DMD_RIU_ReadByte(0x101E39);
747 HAL_DMD_RIU_WriteByte(0x101E39, 0);
748
749 u8Data=HAL_DMD_RIU_ReadByte(0x1128C0);
750 u8Data&=~(0x02);
751 HAL_DMD_RIU_WriteByte(0x1128C0, u8Data);//revert IQ Swap status
752
753 HAL_DMD_RIU_WriteByte(0x101E39, u8Data_temp);
754 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_Exit\n"));
755 INTERN_DVBS_SoftStop();
756
757 return TRUE;
758 }
759
760 /***********************************************************************************
761 Subject: Load DSP code to chip
762 Function: INTERN_DVBS_LoadDSPCode
763 Parmeter:
764 Return: MS_BOOL
765 Remark:
766 ************************************************************************************/
INTERN_DVBS_LoadDSPCode(void)767 static MS_BOOL INTERN_DVBS_LoadDSPCode(void)
768 {
769 MS_U8 udata = 0x00;
770 MS_U16 i;
771 MS_U16 fail_cnt=0;
772
773 #if (DBG_DUMP_LOAD_DSP_TIME==1)
774 MS_U32 u32Time;
775 #endif
776
777 //MDrv_Sys_DisableWatchDog();
778 /*
779 HAL_DMD_RIU_WriteByte(0x103480, 0x01);//reference GUI//reset
780 HAL_DMD_RIU_WriteByte(0x103481, 0x00);
781 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
782 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
783 HAL_DMD_RIU_WriteByte(0x103483, 0x51);
784 HAL_DMD_RIU_WriteByte(0x103484, 0x00);
785 HAL_DMD_RIU_WriteByte(0x103485, 0x00);
786 */
787 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x01); // reset VD_MCU
788 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x00); // disable SRAM
789 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // enable "vdmcu51_if"
790 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x51); // enable auto-increase
791 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
792 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
793
794 //// Load code thru VDMCU_IF ////
795 DBG_INTERN_DVBS(printf(">Load Code.....\n"));
796 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
797 {
798 HAL_DMD_RIU_WriteByte(0x10348C, INTERN_DVBS_table[i]);
799 //HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x0C, INTERN_DVBS_table[i]); // write data to VD MCU 51 code sram
800 }
801
802 //// Content verification ////
803 DBG_INTERN_DVBS(ULOGD("DEMOD",">Verify Code...\n"));
804
805 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x00); // sram address low byte
806 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
807
808 for ( i = 0; i < sizeof(INTERN_DVBS_table); i++)
809 {
810 udata = HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x10); // read sram data
811 if (udata != INTERN_DVBS_table[i])
812 {
813 ULOGD("DEMOD",">fail add = 0x%x\n", i);
814 ULOGD("DEMOD",">code = 0x%x\n", INTERN_DVBS_table[i]);
815 ULOGD("DEMOD",">data = 0x%x\n", udata);
816
817 if (fail_cnt > 10)
818 {
819 ULOGD("DEMOD",">DVB-S DSP Loadcode fail!");
820 return false;
821 }
822 fail_cnt++;
823 }
824 }
825
826 #if 0 //use for Kris DJB with VCM
827 //====================================================================
828 // add S2 DRAM bufer start address into fixed location
829 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x04, 0x30); // sram address low byte; 0x30 is defined in FW
830 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x05, 0x00); // sram address high byte
831
832 //0x30~0x33
833 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)u32DMD_DVBS2_DJB_START_ADDR);
834 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 8));
835 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 16));
836 HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, (MS_U8)(u32DMD_DVBS2_DJB_START_ADDR >> 24));
837
838 printf("@@@@@ share dram address = 0x %x \n ",u32DMD_DVBS2_DJB_START_ADDR);
839 //=====================================================================
840 #endif
841
842 /*
843 HAL_DMD_RIU_WriteByte(0x103483, 0x50);
844 HAL_DMD_RIU_WriteByte(0x103483, 0x00);
845 HAL_DMD_RIU_WriteByte(0x103480, 0x01);
846 HAL_DMD_RIU_WriteByte(0x103481, 0x01);
847 HAL_DMD_RIU_WriteByte(0x103480, 0x00);
848 */
849
850 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x50); // diable auto-increase
851 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, 0x00); // disable "vdmcu51_if"
852 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x01, 0x01); // enable SRAM
853 HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x00, 0x00); // release VD_MCU
854
855
856 DBG_INTERN_DVBS(ULOGD("DEMOD",">DSP Loadcode done."));
857 #if 0
858 INTERN_DVBS_Config(6875, 128, 36125, 0,1);
859 INTERN_DVBS_Active(ENABLE);
860 while(1);
861 #endif
862 //HAL_DMD_RIU_WriteByte(0x101E3E, 0x04); // DVBT = BIT1 -> 0x02
863
864 return TRUE;
865 }
866
867 /***********************************************************************************
868 Subject: DVB-S CLKGEN initialized function
869 Function: INTERN_DVBS_Power_On_Initialization
870 Parmeter:
871 Return: MS_BOOL
872 Remark:
873 ************************************************************************************/
INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)874 void INTERN_DVBS_InitClkgen(MS_BOOL bRFAGCTristateEnable)
875 {
876 MS_U8 u8Temp=0;
877 // This file is translated by Steven Hung's riu2script.pl
878
879 // ==============================================================
880 // Start demod top initial setting by HK MCU ......
881 // ==============================================================
882 // [8] : reg_chiptop_dummy_0 (reg_dmdtop_dmd_sel)
883 // 1'b0->reg_DMDTOP control by HK_MCU.
884 // 1'b1->reg_DMDTOP control by DMD_MCU.
885 // [9] : reg_chiptop_dummy_0 (reg_dmd_ana_regsel)
886 // 1'b0->reg_DMDANA control by HK_MCU.
887 // 1'b1->reg_DMDANA control by DMD_MCU.
888 // select HK MCU ......
889 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
890 // `RIU_W((`RIUBASE_CHIP>>1)+7'h1c, 2'b10, 16'h0000);
891 HAL_DMD_RIU_WriteByte(0x101e39,0x00);
892
893
894 // ==============================================================
895 // Start TOP CLKGEN initial setting ......
896 // ==============================================================
897 // CLK_DMDMCU clock setting
898 // reg_ckg_dmdmcu@0x0f[4:0]
899 // [0] : disable clock
900 // [1] : invert clock
901 // [4:2]:
902 // 000:170 MHz(MPLL_DIV_BUF)
903 // 001:160MHz
904 // 010:144MHz
905 // 011:123MHz
906 // 100:108MHz (Kriti:DVBT2)
907 // 101:mem_clcok
908 // 110:mem_clock div 2
909 // 111:select XTAL
910 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
911 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0f, 2'b11, 16'h001c);
912 HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
913 HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
914
915
916 // set parallel ts clock
917 // [11] : reg_ckg_demod_test_in_en = 0
918 // 0: select internal ADC CLK
919 // 1: select external test-in clock
920 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
921 // 0: select gated clock
922 // 1: select free-run clock
923 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
924 // 0: normal phase to pad
925 // 1: invert phase to pad
926 // [8] : reg_ckg_atsc_dvb_div_sel = 1
927 // 0: select clk_dmplldiv5
928 // 1: select clk_dmplldiv3
929 // [4:0]: reg_ckg_dvbtm_ts_divnum = 11
930 // Demod TS output clock phase tuning number
931 // If (reg_ckg_tsout_ph_tun_num == reg_ckg_dvbtm_ts_divnum),
932 // Demod TS output clock is equal Demod TS internal working clock.
933 // => TS clock = (864/3)/(2*(5+1)) = 24MHz
934 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
935 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
936 HAL_DMD_RIU_WriteByte(0x103301, 0x05);
937 HAL_DMD_RIU_WriteByte(0x103300, 0x05);
938
939
940 // enable DVBTC ts clock
941 // [11:8]: reg_ckg_dvbtc_ts
942 // [8] : disable clock
943 // [9] : invert clock
944 // [11:10]: Select clock source
945 // 00:clk_atsc_dvb_div
946 // 01:62 MHz
947 // 10:54 MHz
948 // 11:reserved
949 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
950 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h04, 2'b11, 16'h0000);
951 HAL_DMD_RIU_WriteByte(0x103309, 0x00);
952 HAL_DMD_RIU_WriteByte(0x103308, 0x00);
953
954
955 // enable dvbc adc clock
956 // [3:0]: reg_ckg_dvbtc_adc
957 // [0] : disable clock
958 // [1] : invert clock
959 // [3:2]: Select clock source => for demod clkgen clk_dvbtc_adc
960 // 00: clk_dmdadc
961 // 01: clk_dmdadc_div2
962 // 10: clk_dmdadc_div4
963 // 11: DFT_CLK
964 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
965 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h0a, 2'b11, 16'h0000);
966 HAL_DMD_RIU_WriteByte(0x103315, 0x00);
967 HAL_DMD_RIU_WriteByte(0x103314, 0x00);
968
969
970 // ==============================================================
971 // Start demod_0 CLKGEN setting ......
972 // ==============================================================
973 // enable atsc_adcd_sync clock
974 // [3:0] : reg_ckg_atsc_adcd_sync
975 // [0] : disable clock
976 // [1] : invert clock
977 // [3:2]: Select clock source
978 // 00: clk_dmdadc_sync
979 // 01: 1'b0
980 // 10: 1'b0
981 // 11: DFT_CLK
982 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
983 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0000);
984 HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
985 HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
986
987 // DVBS2
988 // @0x350c
989 // [3:0] : reg_ckg_dvbs_outer1x
990 // [0] : disable clock
991 // [1] : invert clock
992 // [3:2]: Select clock source
993 // 00: adc_clk_buf
994 // 01: dvb_clk86_buf
995 // 10: dvb_clk43_buf
996 // 11: 1'b0
997 // [6:4] : reg_ckg_dvbs_outer2x
998 // [4] : disable clock
999 // [5] : invert clock
1000 // [6] : Select clock source
1001 // 00: adc_clk_buf
1002 // 01: 1'b0
1003 // 10: 1'b0
1004 // 11: DFT_CLK
1005 // [10:8]: reg_ckg_dvbs2_inner
1006 // [8] : disable clock
1007 // [9] : invert clock
1008 // [10]: Select clock source
1009 // 00: adc_clk_buf
1010 // 01: 1'b0
1011 // 10: 1'b0
1012 // 11: DFT_CLK
1013 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1014 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0c, 2'b11, 16'h0000);
1015 HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1016 HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1017
1018
1019 // DVBS2
1020 // @0x350d
1021 // [11:8]: reg_ckg_dvbs2_oppro
1022 // [8] : disable clock
1023 // [9] : invert clock
1024 // [11:10]: Select clock source
1025 // 00: mpll_clk144_buf
1026 // 01: mpll_clk96_buf
1027 // 10: mpll_clk72_buf
1028 // 11: mpll_clk48_buf
1029 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1030 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h0d, 2'b11, 16'h0000);
1031 HAL_DMD_RIU_WriteByte(0x111f1b, 0x00);
1032 HAL_DMD_RIU_WriteByte(0x111f1a, 0x00);
1033
1034
1035 // @0x3510
1036 // [3:0] : reg_ckg_dvbtm_adc
1037 // N/A
1038 // [6:4] : reg_ckg_dvbt_inner1x
1039 // [4] : disable clock
1040 // [5] : invert clock
1041 // [6] : Select clock source
1042 // 00: dvb_clk24_buf
1043 // 01: dvb_clk21p5_buf
1044 // 10: 1'b0
1045 // 11: DFT_CLK
1046 // [10:8] reg_ckg_dvbt_inner2x
1047 // [8] : disable clock
1048 // [9] : invert clock
1049 // [10]: Select clock source
1050 // 00: dvb_clk48_buf
1051 // 01: dvb_clk43_buf
1052 // 10: 1'b0
1053 // 11: DFT_CLK
1054 // [14:12] reg_ckg_dvbt_inner4x
1055 // [12]: disable clock
1056 // [13]: invert clock
1057 // [14]: Select clock source
1058 // 00: dvb_clk96_buf
1059 // 01: dvb_clk86_buf
1060 // 10: 1'b0
1061 // 11: DFT_CLK
1062 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1063 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h10, 2'b11, 16'h1110);
1064 HAL_DMD_RIU_WriteByte(0x111f21, 0x11);
1065 HAL_DMD_RIU_WriteByte(0x111f20, 0x10);
1066
1067 // @0x3511
1068 // [2:0] : reg_ckg_dvbt_outer1x
1069 // [0] : disable clock
1070 // [1] : invert clock
1071 // [2] : Select clock source
1072 // 00: dvb_clk48_buf
1073 // 01: dvb_clk43_buf
1074 // 10: 1'b0
1075 // 11: DFT_CLK
1076 // [6:4] : reg_ckg_dvbt_outer2x
1077 // [4] : disable clock
1078 // [5] : invert clock
1079 // [6] : Select clock source
1080 // 00: dvb_clk96_buf
1081 // 01: dvb_clk86_buf
1082 // 10: 1'b0
1083 // 11: DFT_CLK
1084 // [11:8]: reg_ckg_dvbtc_outer2x
1085 // [8] : disable clock
1086 // [9] : invert clock
1087 // [11:10]: Select clock source
1088 // 00: mpll_clk57p6_buf
1089 // 01: dvb_clk43_buf
1090 // 10: dvb_clk86_buf
1091 // 11: dvb_clk96_buf
1092 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1093 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h11, 2'b11, 16'h0c11);
1094 HAL_DMD_RIU_WriteByte(0x111f23, 0x0c);
1095 HAL_DMD_RIU_WriteByte(0x111f22, 0x11);
1096
1097
1098 // @0x3512
1099 // [11:8]: reg_ckg_acifir
1100 // [8] : disable clock
1101 // [9] : invert clock
1102 // [11:10]: Select clock source
1103 // 000: 1'b0
1104 // 001: clk_dmdadc
1105 // 010: clk_vif_ssc_mux
1106 // 011: 1'b0
1107 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1108 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h12, 2'b10, 16'h0400);
1109 HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1110
1111
1112 // @0x3514
1113 // [12:8]: reg_ckg_dvbtm_sram_t1o2x_t22x
1114 // [8] : disable clock
1115 // [9] : invert clock
1116 // [12:10]: Select clock source
1117 // 000: dvb_clk48_buf
1118 // 001: dvb_clk43_buf
1119 // 010: 1'b0
1120 // 011: 1'b0
1121 // 100: 1'b0
1122 // 101: 1'b0
1123 // 110: 1'b0
1124 // 111: 1'b0
1125 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1126 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h14, 2'b11, 16'h0000);
1127 HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1128 HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1129
1130
1131 // @0x3516
1132 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x
1133 // [4] : disable clock
1134 // [5] : invert clock
1135 // [8:6]: Select clock source
1136 // 000: dvb_clk48_buf
1137 // 001: dvb_clk43_buf
1138 // 010: 1'b0
1139 // 011: 1'b0
1140 // 100: adc_clk_buf
1141 // 101: 1'b0
1142 // 110: 1'b0
1143 // 111: 1'b0
1144 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1145 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h16, 2'b11, 16'h0001);
1146 HAL_DMD_RIU_WriteByte(0x111f2d, 0x00);
1147 HAL_DMD_RIU_WriteByte(0x111f2c, 0x01);
1148
1149
1150 // @0x3517
1151 // [4:0] : reg_ckg_dvbtm_sram_t12x_t22x
1152 // [0] : disable clock
1153 // [1] : invert clock
1154 // [4:2]: Select clock source
1155 // 000: dvb_clk48_buf
1156 // 001: dvb_clk43_buf
1157 // 010: 1'b0
1158 // 011: 1'b0
1159 // 100: 1'b0
1160 // 101: 1'b0
1161 // 110: 1'b0
1162 // 111: 1'b0
1163 // [12:8] reg_ckg_dvbtm_sram_t12x_t24x
1164 // [8] : disable clock
1165 // [9] : invert clock
1166 // [12:10]: Select clock source
1167 // 000: dvb_clk96_buf
1168 // 001: dvb_clk86_buf
1169 // 010: dvb_clk48_buf
1170 // 011: dvb_clk43_buf
1171 // 100: 1'b0
1172 // 101: 1'b0
1173 // 110: 1'b0
1174 // 111: 1'b0
1175 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1176 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h17, 2'b11, 16'h0000);
1177 HAL_DMD_RIU_WriteByte(0x111f2f, 0x00);
1178 HAL_DMD_RIU_WriteByte(0x111f2e, 0x00);
1179
1180
1181 // @0x3518
1182 // [4:0] : reg_ckg_dvbtm_sram_t14x_t24x
1183 // [0] : disable clock
1184 // [1] : invert clock
1185 // [4:2]: Select clock source
1186 // 000: dvb_clk96_buf
1187 // 001: dvb_clk96_buf
1188 // 010: 1'b0
1189 // 011: 1'b0
1190 // 100: 1'b0
1191 // 101: 1'b0
1192 // 110: 1'b0
1193 // 111: 1'b0
1194 // [12:8]: reg_ckg_dvbtm_ts_in
1195 // [8] : disable clock
1196 // [9] : invert clock
1197 // [12:10]: Select clock source
1198 // 000: clk_dvbtc_rs_p
1199 // 001: dvb_clk48_buf
1200 // 010: dvb_clk43_buf
1201 // 011: clk_dvbs_outer1x_pre_mux4
1202 // 100: clk_dvbs2_oppro_pre_mux4
1203 // 101: 1'b0
1204 // 110: 1'b0
1205 // 111: 1'b0
1206 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1207 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h18, 2'b11, 16'h0001);
1208 HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1209 HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1210
1211
1212 // @0x3519
1213 // [2:0] : reg_ckg_tdp_jl_inner1x
1214 // [0] : disable clock
1215 // [1] : invert clock
1216 // [2] : Select clock source
1217 // 00: dvb_clk24_buf
1218 // 01: dvb_clk21p5_buf
1219 // 10: 1'b0
1220 // 11: DFT_CLK
1221 // [6:4] : reg_ckg_tdp_jl_inner4x
1222 // [4] : disable clock
1223 // [5] : invert clock
1224 // [6] : Select clock source
1225 // 00: dvb_clk96_buf
1226 // 01: dvb_clk86_buf
1227 // 10: 1'b0
1228 // 11: DFT_CLK
1229 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1230 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h19, 2'b11, 16'h3c00);
1231 HAL_DMD_RIU_WriteByte(0x111f33, 0x3c);
1232 HAL_DMD_RIU_WriteByte(0x111f32, 0x00);
1233
1234
1235 // @0x351a
1236 // [6:4] : reg_ckg_dvbt2_inner1x
1237 // [4] : disable clock
1238 // [5] : invert clock
1239 // [6] : Select clock source
1240 // 00: dvb_clk96_buf
1241 // 01: dvb_clk86_buf
1242 // 10: 1'b0
1243 // 11: DFT_CLK
1244 // [10:8]: reg_ckg_dvbt2_inner2x
1245 // [8] : disable clock
1246 // [9] : invert clock
1247 // [10]: Select clock source
1248 // 00: dvb_clk48_buf
1249 // 01: dvb_clk43_buf
1250 // 10: 1'b0
1251 // 11: DFT_CLK
1252 // [14:12]:reg_ckg_dvbt2_inner4x
1253 // [12] : disable clock
1254 // [13] : invert clock
1255 // [14] : Select clock source
1256 // 00: dvb_clk96_buf
1257 // 01: dvb_clk86_buf
1258 // 10: 1'b0
1259 // 11: DFT_CLK
1260 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1261 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1a, 2'b11, 16'h0000);
1262 HAL_DMD_RIU_WriteByte(0x111f35, 0x00);
1263 HAL_DMD_RIU_WriteByte(0x111f34, 0x00);
1264
1265
1266 // @0x351b
1267 // [1:0] : reg_ckg_dvbt2_ldpc
1268 // DVBT2 LDPC gated clock control register
1269 // [0] = 1:clock enable.
1270 // [1] = 1:manual mode.
1271 // [3:2] : reg_ckg_dvbt2_bch
1272 // DVBT2 BCH gated clock control register;
1273 // [0] = 1:clock enable
1274 // [1] = 1:manual mode.
1275 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1276 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1b, 2'b11, 16'h0011);
1277 HAL_DMD_RIU_WriteByte(0x111f37, 0x00);
1278 HAL_DMD_RIU_WriteByte(0x111f36, 0x11);
1279
1280
1281 // @0x351d
1282 // [4:0] : reg_ckg_dvbtm_adc_eq_1x
1283 // [0] : disable clock
1284 // [1] : invert clock
1285 // [2] : Select clock source
1286 // 00: adc_clk_buf
1287 // 01: 1'b0
1288 // 10: 1'b0
1289 // 11: DFT_CLK
1290 // [12:8]: reg_ckg_dvbtm_adc_eq_0p5x
1291 // [4] : disable clock
1292 // [5] : invert clock
1293 // [6]: Select clock source
1294 // 00: clk_adc_div2_buf
1295 // 01: 1'b0
1296 // 10: 1'b0
1297 // 11: DFT_CLK
1298 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1299 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1d, 2'b11, 16'h0000);
1300 HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1301 HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1302
1303
1304 // @0x351e
1305 // [4:0] : reg_ckg_dvbtm_sram_t11x_t22x
1306 // [0] : disable clock
1307 // [1] : invert clock
1308 // [4:2]: Select clock source
1309 // 000: dvb_clk48_buf
1310 // 001: dvb_clk43_buf
1311 // 010: dvb_clk24_buf
1312 // 011: dvb_clk21p5_buf
1313 // 100: 1'b0
1314 // 101: 1'b0
1315 // 110: 1'b0
1316 // 111: 1'b0
1317 // [12:8]: reg_ckg_dvbtm_sram_t11x_t24x
1318 // [8] : disable clock
1319 // [9] : invert clock
1320 // [:2]: Select clock source
1321 // 000: dvb_clk48_buf
1322 // 001: dvb_clk43_buf
1323 // 010: dvb_clk24_buf
1324 // 011: dvb_clk21p5_buf
1325 // 100: 1'b0
1326 // 101: 1'b0
1327 // 110: 1'b0
1328 // 111: 1'b0
1329 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0c04);
1330 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1331 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h1e, 2'b11, 16'h0000);
1332 HAL_DMD_RIU_WriteByte(0x111f3d, 0x00);
1333 HAL_DMD_RIU_WriteByte(0x111f3c, 0x00);
1334
1335
1336 // @0x3522
1337 // [3:0] : reg_ckg_dvbt_t2_inner0p5x_dvbc_eq1x
1338 // [0] : disable clock
1339 // [1] : invert clock
1340 // [2] : Select clock source
1341 // 00: dvb_clk12_buf
1342 // 01: dvb_clk10p75_buf
1343 // 10: 1'b0
1344 // 11: DFT_CLK
1345 // [7:4] : reg_ckg_dvbt_t2_inner2x_dvbc_eq4x
1346 // [4] : disable clock
1347 // [5] : invert clock
1348 // [6] : Select clock source
1349 // 00: dvb_clk48_buf
1350 // 01: dvb_clk43_buf
1351 // 10: 1'b0
1352 // 11: DFT_CLK
1353 // [11:8]: reg_ckg_dvbt_t2_inner1x
1354 // [8] : disable clock
1355 // [9] : invert clock
1356 // [11:10]: Select clock source
1357 // 00: dvb_clk24_buf
1358 // 01: dvb_clk21p5_buf
1359 // 10: 1'b0
1360 // 11: DFT_CLK
1361 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1362 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h22, 2'b11, 16'h0111);
1363 HAL_DMD_RIU_WriteByte(0x111f45, 0x01);
1364 HAL_DMD_RIU_WriteByte(0x111f44, 0x11);
1365
1366 // @0x353a
1367 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner2x
1368 // [0] : disable clock
1369 // [1] : invert clock
1370 // [2] : Select clock source
1371 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1372 // 01: clk_isdbt_inner2x_p
1373 // 10: 1'b0
1374 // 11: DFT_CLK
1375 // [6:4] : reg_ckg_dvbtm_sram_t12x_t24x_isdbt_inner2x
1376 // [4] : disable clock
1377 // [5] : invert clock
1378 // [6] : Select clock source
1379 // 00: clk_dvbtm_sram_t12x_t24x_p
1380 // 01: clk_isdbt_inner2x_p
1381 // 10: 1'b0
1382 // 11: DFT_CLK
1383 // [10:8]: reg_ckg_dvbtm_sram_t24x_isdbt_inner2x
1384 // [8] : disable clock
1385 // [9] : invert clock
1386 // [10]: Select clock source
1387 // 00: clk_dvbtm_sram_t14x_t24x_p
1388 // 01: clk_isdbt_inner2x_p
1389 // 10: 1'b0
1390 // 11: DFT_CLK
1391 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner4x
1392 // [12] : disable clock
1393 // [13] : invert clock
1394 // [14] : Select clock source
1395 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1396 // 01: clk_isdbt_inner4x_p
1397 // 10: 1'b0
1398 // 11: DFT_CLK
1399 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1400 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3a, 2'b11, 16'h0110);
1401 HAL_DMD_RIU_WriteByte(0x111f75, 0x01);
1402 HAL_DMD_RIU_WriteByte(0x111f74, 0x10);
1403
1404 // @0x353b
1405 // [2:0] : reg_ckg_dvbtm_sram_t12x_t24x_s2inner_isdbt_inner2x
1406 // [0] : disable clock
1407 // [1] : invert clock
1408 // [2] : Select clock source
1409 // 00: clk_dvbtm_sram_t12x_t24x_s2inner_p
1410 // 01: clk_isdbt_inner2x_p
1411 // 10: 1'b0
1412 // 11: DFT_CLK
1413 // [6:4] : reg_ckg_dvbtm_sram_t22x_isdbt_inner2x
1414 // [4] : disable clock
1415 // [5] : invert clock
1416 // [6] : Select clock source
1417 // 00: clk_dvbtm_sram_t12x_t22x_p
1418 // 01: clk_isdbt_inner2x_p
1419 // 10: 1'b0
1420 // 11: DFT_CLK
1421 // [10:8]: reg_ckg_dvbtm_sram_t14x_t24x_s2inner_isdbt_inner2x
1422 // [8] : disable clock
1423 // [9] : invert clock
1424 // [10]: Select clock source
1425 // 00: clk_dvbtm_sram_t14x_t24x_s2inner_p
1426 // 01: clk_isdbt_inner2x_p
1427 // 10: 1'b0
1428 // 11: DFT_CLK
1429 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_srd1x_isdbt_inner4x
1430 // [12] : disable clock
1431 // [13] : invert clock
1432 // [14]: Select clock source
1433 // 00: clk_dvbtm_sram_t12x_t24x_srd1x_p
1434 // 01: clk_isdbt_inner4x_p
1435 // 10: 1'b0
1436 // 11: DFT_CLK
1437 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1438 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0010);
1439 HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
1440 HAL_DMD_RIU_WriteByte(0x111f76, 0x10);
1441
1442 // @0x353c
1443 // [2:0] : reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x
1444 // [0] : disable clock
1445 // [1] : invert clock
1446 // [2] : Select clock source
1447 // 00: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1448 // 01: clk_isdbt_inner4x_p
1449 // 10: 1'b0
1450 // 11: DFT_CLK
1451 // [6:4] : reg_ckg_dvbtm_sram_t12x_t22x_isdbt_inner2x
1452 // [4] : disable clock
1453 // [5] : invert clock
1454 // [6] : Select clock source
1455 // 00: clk_dvbtm_sram_t12x_t22x_p
1456 // 01: clk_isdbt_inner2x_p
1457 // 10: 1'b0
1458 // 11: DFT_CLK
1459 // [10:8]: reg_ckg_dvbtm_sram_t11x_t22x_isdbt_inner2x
1460 // [8] : disable clock
1461 // [9] : invert clock
1462 // [10]: Select clock source
1463 // 00: clk_dvbtm_sram_t11x_t22x_p
1464 // 01: clk_isdbt_inner2x_p
1465 // 10: 1'b0
1466 // 11: DFT_CLK
1467 // [14:12]: reg_ckg_dvbtm_sram_t12x_t24x_isdbt_outer6x
1468 // [12] : disable clock
1469 // [13] : invert clock
1470 // [14]: Select clock source
1471 // 00: clk_dvbtm_sram_t12x_t24x_p
1472 // 01: clk_isdbt_outer6x_dvbt_outer2x_c_mux
1473 // 10: 1'b0
1474 // 11: DFT_CLK
1475 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1476 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3c, 2'b11, 16'h0110);
1477 HAL_DMD_RIU_WriteByte(0x111f79, 0x01);
1478 HAL_DMD_RIU_WriteByte(0x111f78, 0x10);
1479
1480 // @0x353e
1481 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_isdbt_outer6x
1482 // [0] : disable clock
1483 // [1] : invert clock
1484 // [2] : Select clock source
1485 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1486 // 01: clk_isdbt_outer6x_p
1487 // 10: 1'b0
1488 // 11: DFT_CLK
1489 // [6:4] : reg_ckg_dvbtm_sram_t22x_miu
1490 // [4] : disable clock
1491 // [5] : invert clock
1492 // [6] : Select clock source
1493 // 00: clk_dvbt2_inner2x_p
1494 // 01: clk_miu_p
1495 // 10: 1'b0
1496 // 11: DFT_CLK
1497 // [10:8]: reg_ckg_dvbtm_sram_adc_t22x_isdbt_inner2x
1498 // [8] : disable clock
1499 // [9] : invert clock
1500 // [10]: Select clock source
1501 // 00: clk_dvbtm_sram_adc_t22x_p
1502 // 01: clk_isdbt_inner2x_p
1503 // 10: 1'b0
1504 // 11: DFT_CLK
1505 // [14:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_miu
1506 // [12] : disable clock
1507 // [13] : invert clock
1508 // [14]: Select clock source
1509 // 00: clk_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x_mux8
1510 // 01: clk_miu_p
1511 // 10: 1'b0
1512 // 11: DFT_CLK
1513 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1514 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3e, 2'b11, 16'h1111);
1515 HAL_DMD_RIU_WriteByte(0x111f7d, 0x11);
1516 HAL_DMD_RIU_WriteByte(0x111f7c, 0x11);
1517
1518 // @0x353f
1519 // [2:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_miu_isdbt_outer6x
1520 // [0] : disable clock
1521 // [1] : invert clock
1522 // [2] : Select clock source
1523 // 00: clk_dvbs_outer2x_dvbt_outer2x_miu_mux8
1524 // 01: clk_isdbt_outer6x_p
1525 // 10: 1'b0
1526 // 11: DFT_CLK
1527 // [6:4] : reg_ckg_dvbtm_sram_t22x_dvbtc_rs
1528 // [4] : disable clock
1529 // [5] : invert clock
1530 // [6] : Select clock source
1531 // 00: clk_dvbt2_inner2x_p
1532 // 01: clk_dvbtc_rs_p
1533 // 10: 1'b0
1534 // 11: DFT_CLK
1535 // [10:8]: reg_ckg_dvbtc_outer2x_isdbt_outer_rs
1536 // [8] : disable clock
1537 // [9] : invert clock
1538 // [10]: Select clock source
1539 // 00: clk_dvbtc_outer2x_p
1540 // 01: clk_isdbt_outer_rs_p
1541 // 10: 1'b0
1542 // 11: DFT_CLK
1543 // [14:12]: reg_ckg_dvbtm_sram_t22x_isdbt_outer6x_dvbt_outer2x
1544 // [12] : disable clock
1545 // [13] : invert clock
1546 // [14]: Select clock source
1547 // 00: clk_dvbtm_sram_t12x_t22x_p
1548 // 01: clk_isdbt_outer6x_dvbt_outer2x_mux
1549 // 10: 1'b0
1550 // 11: DFT_CLK
1551 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1552 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3f, 2'b11, 16'h1041);
1553 HAL_DMD_RIU_WriteByte(0x111f7f, 0x10);
1554 HAL_DMD_RIU_WriteByte(0x111f7e, 0x41);
1555
1556
1557 // @0x3570
1558 // [4:0] : reg_ckg_dvbt_inner2x_srd0p5x
1559 // [0] : disable clock
1560 // [1] : invert clock
1561 // [3:2]: Select clock source
1562 // 00: dvb_clk48_buf
1563 // 01: dvb_clk43_buf
1564 // 10: clk_adc_div2_buf
1565 // 11: 1'b0
1566 // 11: 1'b0
1567 // [13:8]: reg_ckg_dvbtm_sram_t1outer1x_t24x
1568 // [8] : disable clock
1569 // [9] : invert clock
1570 // [12:10]: Select clock source
1571 // 000: dvb_clk96_buf
1572 // 001: dvb_clk86_buf
1573 // 010: dvb_clk48_buf
1574 // 011: dvb_clk43_buf
1575 // 100: 1'b0
1576 // 101: 1'b0
1577 // 110: 1'b0
1578 // 111: 1'b0
1579 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1580 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h70, 2'b11, 16'h0008);
1581 HAL_DMD_RIU_WriteByte(0x111fe1, 0x00);
1582 HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1583
1584
1585 // @0x3571
1586 // [4:0] : reg_ckg_dvbtm_sram_t12x_t24x_srd1x
1587 // [0] : disable clock
1588 // [1] : invert clock
1589 // [3:2]: Select clock source
1590 // 000: dvb_clk96_buf
1591 // 001: dvb_clk86_buf
1592 // 010: dvb_clk48_buf
1593 // 011: dvb_clk43_buf
1594 // 100: adc_clk_buf
1595 // 101: 1'b0
1596 // 110: 1'b0
1597 // 111: 1'b0
1598 // [12:8]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x
1599 // [8] : disable clock
1600 // [9] : invert clock
1601 // [12:10]: Select clock source
1602 // 000: dvb_clk96_buf
1603 // 001: dvb_clk86_buf
1604 // 010: adc_clk_buf
1605 // 011: 1'b0
1606 // 100: 1'b0
1607 // 101: 1'b0
1608 // 110: 1'b0
1609 // 111: 1'b0
1610 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1611 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h71, 2'b11, 16'h0810);
1612 HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1613 HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1614
1615
1616 // @0x3572
1617 // [6:0] : reg_ckg_dvbt2_s2_bch_out
1618 // [0] : disable clock
1619 // [1] : invert clock
1620 // [2] : Select clock source
1621 // 00: dvb_clk48_buf
1622 // 01: dvb_clk43_buf
1623 // 10: 1'b0
1624 // 11: DFT_CLK
1625 // [12:8]: reg_ckg_dvbt2_outer2x
1626 // [8] : disable clock
1627 // [9] : invert clock
1628 // [12:10]: Select clock source
1629 // 000: mpll_clk144_buf
1630 // 001: mpll_clk108_buf
1631 // 010: mpll_clk96_buf
1632 // 011: mpll_clk72_buf
1633 // 100: mpll_clk54_buf
1634 // 101: mpll_clk48_buf
1635 // 110: mpll_clk36_buf
1636 // 111: mpll_clk24_buf
1637 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1638 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h72, 2'b11, 16'h0008);
1639 HAL_DMD_RIU_WriteByte(0x111fe5, 0x00);
1640 HAL_DMD_RIU_WriteByte(0x111fe4, 0x08);
1641
1642
1643 // @0x3573
1644 // [3:0] : reg_ckg_dvbt2_inner4x_s2_inner
1645 // [0] : disable clock
1646 // [1] : invert clock
1647 // [2] : Select clock source
1648 // 00: dvb_clk96_buf
1649 // 01: dvb_clk86_buf
1650 // 10: 1'b0
1651 // 11: DFT_CLK
1652 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1653 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h73, 2'b11, 16'h0008);
1654 HAL_DMD_RIU_WriteByte(0x111fe7, 0x00);
1655 HAL_DMD_RIU_WriteByte(0x111fe6, 0x08);
1656
1657
1658 // @0x3574
1659 // [4:0] reg_ckg_dvbtm_sram_t12x_t24x_s2inner
1660 // [0] : disable clock
1661 // [1] : invert clock
1662 // [4:2]:Select clock source
1663 // 000: dvb_clk96_buf
1664 // 001: dvb_clk86_buf
1665 // 010: dvb_clk48_buf
1666 // 011: dvb_clk43_buf
1667 // 100: adc_clk_buf
1668 // 101: 1'b0
1669 // 110: 1'b0
1670 // 111: 1'b0
1671 // [12:8] reg_ckg_dvbtm_sram_t14x_t24x_s2inner
1672 // [8] : disable clock
1673 // [9] : invert clock
1674 // [12:10]: Select clock source
1675 // 000: dvb_clk96_buf
1676 // 001: dvb_clk86_buf
1677 // 010: adc_clk_buf
1678 // 011: dvb_clk24_buf //JL SRAM Share (Windermere U02 ECO)
1679 // 100: dvb_clk21p5_buf //JL SRAM Share (Windermere U02 ECO)
1680 // 101: 1'b0
1681 // 110: 1'b0
1682 // 111: 1'b0
1683 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1684 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h74, 2'b11, 16'h0810);
1685 HAL_DMD_RIU_WriteByte(0x111fe9, 0x08);
1686 HAL_DMD_RIU_WriteByte(0x111fe8, 0x10);
1687
1688
1689 // @0x3575
1690 // [4:0] : reg_ckg_dvbtc_rs
1691 // [0] : disable clock
1692 // [1] : invert clock
1693 // [4:2]:Select clock source
1694 // 000: mpll_clk216_buf
1695 // 001: mpll_clk172p8_buf
1696 // 010: mpll_clk144_buf
1697 // 011: mpll_clk288_buf
1698 // 100: dvb_clk96_buf
1699 // 101: dvb_clk86_buf
1700 // 110: mpll_clk57p6_buf
1701 // 111: dvb_clk43_buf
1702 // [11:8] : reg_ckg_dvbs_outer2x_dvbt_outer2x (N/A)
1703 // [15:12]: reg_ckg_dvbs_outer2x_dvbt_outer2x_miu
1704 // [12] : disable clock
1705 // [13] : invert clock
1706 // [15:14]:Select clock source
1707 // 000: 1'b0
1708 // 001: dvb_clk96_buf
1709 // 010: dvb_clk86_buf
1710 // 011: clk_miu
1711 // 100: 1'b0
1712 // 101: 1'b0
1713 // 110: 1'b0
1714 // 111: 1'b0
1715 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1716 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h75, 2'b11, 16'h0000);
1717 HAL_DMD_RIU_WriteByte(0x111feb, 0x00);
1718 HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1719
1720
1721 // @0x3576
1722 // [4:0] : reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x
1723 // [0] : disable clock
1724 // [1] : invert clock
1725 // [4:2]:Select clock source
1726 // 000: 1'b0
1727 // 001: dvb_clk96_buf
1728 // 010: dvb_clk86_buf
1729 // 011: dvb_clk48_buf
1730 // 100: dvb_clk43_buf
1731 // 101: 1'b0
1732 // 110: 1'b0
1733 // 111: 1'b0
1734 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1735 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h76, 2'b11, 16'h0000);
1736 HAL_DMD_RIU_WriteByte(0x111fed, 0x00);
1737 HAL_DMD_RIU_WriteByte(0x111fec, 0x00);
1738
1739
1740 // @0x3577
1741 // [3:0] : reg_ckg_dvbt2_inner4x_dvbtc_rs
1742 // [0] : disable clock
1743 // [1] : invert clock
1744 // [3:2]: Select clock source
1745 // 00: dvb_clk96_buf
1746 // 01: dvb_clk86_buf
1747 // 10: clk_dvbtc_rs_p
1748 // 11: 1'b0
1749 // [8:4] : reg_ckg_dvbtm_sram_adc_t22x_dvbtc_rs
1750 // [4] : disable clock
1751 // [5] : invert clock
1752 // [6] : Select clock source
1753 // 000: dvb_clk48_buf
1754 // 001: dvb_clk43_buf
1755 // 010: 1'b0
1756 // 011: adc_clk_buf
1757 // 100: 1'b0
1758 // 101: 1'b0
1759 // 110: 1'b0
1760 // 111: 1'b0
1761 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1762 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h77, 2'b11, 16'h0088);
1763 HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1764 HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1765
1766
1767 // Maserati
1768 // @0x3578
1769 // [4:0] : reg_ckg_dvbt2_inner2x_srd0p5x
1770 // [0] : disable clock
1771 // [1] : invert clock
1772 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1773 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h78, 2'b01, 16'h0008);
1774 HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1775
1776 // [3:0] : reg_ckg_sram_t22x_isdbt_inn2x_dtmb_inn2x
1777 // [0] : disable clock
1778 // [1] : invert clock
1779 // [3:2]:Select clock source
1780 // 000: clk_dvbtm_sram_t12x_t22x_p
1781 // 001: clk_isdbt_inner2x_p
1782 // 010: clk_share_dtmb_inner2x_isdbt_sram4_mux
1783 // 011:
1784 // [7:4] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_inn6x
1785 // [4] : disable clock
1786 // [5] : invert clock
1787 // [7:6]:Select clock source
1788 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1789 // 001: clk_isdbt_inner2x_p
1790 // 010: clk_share_dtmb_inner6x_isdbt_sram3_mux
1791 // 011:
1792 // [11:8] : reg_ckg_sram_t14x_t24x_s2inn_isdbt_inn2x_dtmb_eq2x
1793 // [4] : disable clock
1794 // [5] : invert clock
1795 // [7:6]:Select clock source
1796 // 000: clk_dvbtm_sram_t14x_t24x_s2inner_p
1797 // 001: clk_isdbt_inner2x_p
1798 // 010: clk_share_dtmb_eq2x_isdbt_sram3_mux
1799 // 011:
1800 // [15:12]: reg_ckg_dvbtm_sram_t14x_t24x_srd1x_vifssc_isdbt_inner4x_dtmb_inner12x
1801 // [12] : disable clock
1802 // [13] : invert clock
1803 // [15:14]:Select clock source
1804 // 000: clk_dvbtm_sram_t14x_t24x_srd1x_vifssc_p
1805 // 001: clk_isdbt_inner4x_p
1806 // 010: clk_dvbtc_sram2_p
1807 // 011: clk_dtmb_eq2x_inner2x_12x_mux
1808 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1809 // `RIU_W((`RIUBASE_DEMOD_8>>1)+7'h48, 2'b11, 16'h0001);
1810 HAL_DMD_RIU_WriteByte(0x152991, 0x00);
1811 HAL_DMD_RIU_WriteByte(0x152990, 0x01);
1812 // ==============================================================
1813 // End demod top initial setting by HK MCU ......
1814 // ==============================================================
1815 //wriu 0x101e39 0x03
1816 HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
1817
1818 //==========================================================
1819 //diseqc_out : PAD_GPIO15_I
1820 //swich to Diseqc out pin from GPIO
1821 //==========================================================
1822 //Bank: Reg_CHIP_TOP(0x101e)
1823 //reg_test_out_mode : addr h¡¦12, [6:4] = 3¡¦h0
1824 //reg_ts4config : addr h¡¦40, [11:10] = 2¡¦h0
1825 //reg_ts5config : addr h¡¦40, [13:12] = 2¡¦h0
1826 //reg_i2smutemode : addr h¡¦2, [15:14] = 2¡¦h0
1827 //reg_fifthuartmode : h¡¦4, [3:2] = 2¡¦h0
1828 //reg_od5thuart : h¡¦55, [5:4] = 2¡¦h0
1829 //reg_diseqc_out_config : ¡¥h68, [5] = 1¡¦b1
1830 u8Temp = HAL_DMD_RIU_ReadByte(0x101ED0);
1831 u8Temp|=0x10;
1832 HAL_DMD_RIU_WriteByte(0x101ED0, u8Temp);
1833
1834 HAL_DMD_RIU_WriteByte(0x103c0e,0x01);
1835
1836 // SRAM allocation 64K avoid change souce from T2 failed.
1837 HAL_DMD_RIU_WriteByte(0x111701,0x00);
1838 HAL_DMD_RIU_WriteByte(0x111700,0x00);
1839
1840 HAL_DMD_RIU_WriteByte(0x111705,0x00);
1841 HAL_DMD_RIU_WriteByte(0x111704,0x00);
1842
1843 HAL_DMD_RIU_WriteByte(0x111703,0xff);
1844 HAL_DMD_RIU_WriteByte(0x111702,0xff);
1845
1846 HAL_DMD_RIU_WriteByte(0x111707,0xff);
1847 HAL_DMD_RIU_WriteByte(0x111706,0xff);
1848
1849 //Diff from TV tool
1850 HAL_DMD_RIU_WriteByte(0x111708,0x01);
1851 HAL_DMD_RIU_WriteByte(0x111709,0x00);
1852
1853 HAL_DMD_RIU_WriteByte(0x11170a,0x0f);
1854 HAL_DMD_RIU_WriteByte(0x11170b,0x00);
1855
1856 HAL_DMD_RIU_WriteByte(0x111718,0x02);
1857 HAL_DMD_RIU_WriteByte(0x111719,0x00);
1858
1859 HAL_DMD_RIU_WriteByte(0x11171a,0x00);
1860 HAL_DMD_RIU_WriteByte(0x11171b,0x00);
1861
1862 HAL_DMD_RIU_WriteByte(0x1117e0,0x14);
1863 HAL_DMD_RIU_WriteByte(0x1117e1,0x14);
1864
1865 HAL_DMD_RIU_WriteByte(0x1117e4,0x00);
1866 HAL_DMD_RIU_WriteByte(0x1117e5,0x00);
1867
1868 HAL_DMD_RIU_WriteByte(0x1117e6,0x00);
1869 HAL_DMD_RIU_WriteByte(0x1117e7,0x00);
1870
1871 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_InitClkgen\n"));
1872 }
1873
1874 /***********************************************************************************
1875 Subject: Power on initialized function
1876 Function: INTERN_DVBS_Power_On_Initialization
1877 Parmeter:
1878 Return: MS_BOOL
1879 Remark:
1880 ************************************************************************************/
INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable,MS_U8 u8ADCIQMode,MS_U8 u8PadSel,MS_BOOL bPGAEnable,MS_U8 u8PGAGain,const MS_U8 * u8DMD_DVBS_DSPRegInitExt,MS_U8 u8DMD_DVBS_DSPRegInitSize)1881 MS_BOOL INTERN_DVBS_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBS_DSPRegInitExt, MS_U8 u8DMD_DVBS_DSPRegInitSize)
1882 {
1883 MS_U8 status = true;
1884 //MS_U8 u8ChipVersion;
1885
1886 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_Power_On_Initialization\n"));
1887
1888 #if defined(PWS_ENABLE)
1889 Mapi_PWS_Stop_VDMCU();
1890 #endif
1891 INTERN_DVBS_InitClkgen(bRFAGCTristateEnable);//~~ no modify
1892 HAL_DMD_ADC_IQ_Switch(u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain);//~~ no modify
1893
1894 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization1:bRFAGCTristateEnable=%d ;u8ADCIQMode=%d \n",bRFAGCTristateEnable,u8ADCIQMode));
1895 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization2:u8PadSel=%d ;bPGAEnable=%d \n",u8PadSel,bPGAEnable));
1896 DBG_INTERN_DVBS(ULOGD("DEMOD","@@@@@INTERN_DVBS_Power_On_Initialization2:u8PGAGain=%d \n",u8PGAGain));
1897
1898 //// Firmware download //////////
1899 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Load DSP...\n"));
1900 //MsOS_DelayTask(100);
1901
1902 {
1903 if (INTERN_DVBS_LoadDSPCode() == FALSE)
1904 {
1905 DBG_INTERN_DVBS(ULOGD("DEMOD","DVB-S Load DSP Code Fail\n"));
1906 return FALSE;
1907 }
1908 else
1909 {
1910 DBG_INTERN_DVBS(ULOGD("DEMOD","DVB-S Load DSP Code OK\n"));
1911 }
1912 }
1913
1914 //// MCU Reset //////////
1915 if (INTERN_DVBS_Reset() == FALSE)
1916 {
1917 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Reset...Fail\n"));
1918 return FALSE;
1919 }
1920 else
1921 {
1922 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS Reset...OK\n"));
1923 }
1924
1925
1926 status &= INTERN_DVBS_DSPReg_Init(u8DMD_DVBS_DSPRegInitExt, u8DMD_DVBS_DSPRegInitSize);
1927 //status &= INTERN_DVBS_Active(ENABLE);//enable this
1928
1929 //Read Demod FW Version.
1930 INTERN_DVBS_Show_Demod_Version();
1931
1932 return status;
1933 }
1934 /************************************************************************************************
1935 Subject: Driving control
1936 Function: INTERN_DVBC_Driving_Control
1937 Parmeter: bInversionEnable : TRUE For High
1938 Return: void
1939 Remark:
1940 *************************************************************************************************/
INTERN_DVBS_Driving_Control(MS_BOOL bEnable)1941 void INTERN_DVBS_Driving_Control(MS_BOOL bEnable)
1942 {
1943 MS_U8 u8Temp;
1944
1945 u8Temp = HAL_DMD_RIU_ReadByte(0x101E10);
1946
1947 if (bEnable)
1948 {
1949 u8Temp = u8Temp | 0x01; //bit0: clk, bit1~8:data , bit9: sync, bit10:valid
1950 }
1951 else
1952 {
1953 u8Temp = u8Temp & (~0x01);
1954 }
1955
1956 DBG_INTERN_DVBS(ULOGD("DEMOD","---> INTERN_DVBS_Driving_Control(Bit0) = 0x%x \n",u8Temp));
1957 HAL_DMD_RIU_WriteByte(0x101E10, u8Temp);
1958 }
1959
1960 /************************************************************************************************
1961 Subject: Clk Inversion control
1962 Function: INTERN_DVBS_Clk_Inversion_Control
1963 Parmeter: bInversionEnable : TRUE For Inversion Action
1964 Return: void
1965 Remark:
1966 *************************************************************************************************/
INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)1967 void INTERN_DVBS_Clk_Inversion_Control(MS_BOOL bInversionEnable)
1968 {
1969 MS_U8 u8Temp;
1970
1971 u8Temp = HAL_DMD_RIU_ReadByte(0x103301);
1972
1973 if (bInversionEnable)
1974 {
1975 u8Temp = u8Temp | 0x02; //bit 9: clk inv
1976 }
1977 else
1978 {
1979 u8Temp = u8Temp & (~0x02);
1980 }
1981
1982 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit9) = 0x%x \n",u8Temp));
1983 HAL_DMD_RIU_WriteByte(0x103301, u8Temp);
1984 }
1985
1986 /************************************************************************************************
1987 Subject: Transport stream serial/parallel control
1988 Function: INTERN_DVBS_Serial_Control
1989 Parmeter: bEnable : TRUE For serial
1990 Return: MS_BOOL :
1991 Remark:
1992 *************************************************************************************************/
INTERN_DVBS_Serial_Control(MS_BOOL bEnable,MS_U8 u8TSClk)1993 MS_BOOL INTERN_DVBS_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk)
1994 {
1995 MS_U8 status = true;
1996 MS_U8 temp_val;
1997 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_ts... u8TSClk=%d\n", u8TSClk));
1998
1999 if (u8TSClk == 0xFF) u8TSClk=0x13;
2000 if (bEnable) //Serial mode for TS pad
2001 {
2002 // serial
2003 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // serial mode: 0x0401
2004 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2005
2006 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // serial mode 0x0400
2007 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2008 //HAL_DMD_RIU_WriteByte(0x103301, 0x04); // reg_ckg_dvbtmk_ts_out_mode@0x00
2009 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2010 temp_val|=0x04;
2011 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2012 #else
2013 // HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2014 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2015 temp_val|=0x07;
2016 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2017 #endif
2018 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); // PAD_TS1 is used as output
2019 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); // PAD_TS1 Disable TS CLK PAD
2020
2021 //// INTERN_DVBS TS Control: Serial //////////
2022
2023 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_SERIAL);
2024
2025 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2026 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2027 #else
2028 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2029 #endif
2030 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2031
2032 gsCmdPacketDVBS.param[0] = TS_SERIAL;
2033 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2034 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2035 #else
2036 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2037 #endif
2038 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2039 }
2040 else
2041 {
2042 //parallel
2043 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001
2044 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2045
2046 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2047 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2048 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2049 //HAL_DMD_RIU_WriteByte(0x103301, 0x05); // reg_ckg_dvbtmk_ts_out_mode@0x00
2050 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2051 temp_val|=0x05;
2052 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2053 #else
2054 //HAL_DMD_RIU_WriteByte(0x103301, 0x07); // reg_ckg_dvbtmk_ts_out_mode@0x00
2055 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2056 temp_val|=0x07;
2057 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2058 #endif
2059
2060 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); // PAD_TS1 is used as output
2061 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, (HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0)|0x11); // PAD_TS1 enable TS clk pad
2062
2063 //// INTERN_DVBS TS Control: Parallel //////////
2064
2065 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, TS_PARALLEL);
2066
2067 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2068 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 0);
2069 #else
2070 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_OUT_INV, 1);
2071 #endif
2072 //// INTERN_DVBC TS Control: Parallel //////////
2073 gsCmdPacketDVBS.cmd_code = CMD_TS_CTRL;
2074
2075 gsCmdPacketDVBS.param[0] = TS_PARALLEL;
2076 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2077 gsCmdPacketDVBS.param[1] = 0;//TS_CLK_NO_INV;
2078 #else
2079 gsCmdPacketDVBS.param[1] = 1;//TS_CLK_INVERSE;
2080 #endif
2081 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 2);
2082 }
2083
2084 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2085 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",0 ));
2086 #else
2087 DBG_INTERN_DVBS(ULOGD("DEMOD","---> Inversion(Bit5) = %d \n",1 ));
2088 #endif
2089
2090 INTERN_DVBS_Driving_Control(INTERN_DVBS_DTV_DRIVING_LEVEL);
2091 return status;
2092 }
2093
2094 /************************************************************************************************
2095 Subject: TS1 output control
2096 Function: INTERN_DVBS_PAD_TS1_Enable
2097 Parmeter: flag : TRUE For Turn on TS1, FALSE For Turn off TS1
2098 Return: void
2099 Remark:
2100 *************************************************************************************************/
INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)2101 void INTERN_DVBS_PAD_TS1_Enable(MS_BOOL flag)
2102 {
2103 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_TS1_Enable... \n"));
2104
2105 if(flag) // PAD_TS1 Enable TS CLK PAD
2106 {
2107 //printf("=== TS1_Enable ===\n");
2108 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)|0x10); //For T3
2109 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x18); //For T4
2110 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)|0x11); //For T8
2111 }
2112 else // PAD_TS1 Disable TS CLK PAD
2113 {
2114 //printf("=== TS1_Disable ===\n");
2115 //HAL_DMD_RIU_WriteByte(0x101EA5, HAL_DMD_RIU_ReadByte(0x101EA5)&0xEF); //For T3
2116 //HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xE3); //For T4
2117 //move to drvSYS HAL_DMD_RIU_WriteByte(0x101EAF, HAL_DMD_RIU_ReadByte(0x101EAF)&0xC0); //For T8
2118 }
2119 }
2120
2121 /************************************************************************************************
2122 Subject: channel change config
2123 Function: INTERN_DVBC_Config
2124 Parmeter: BW: bandwidth
2125 Return: MS_BOOL :
2126 Remark:
2127 *************************************************************************************************/
INTERN_DVBS_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2128 MS_BOOL INTERN_DVBS_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2129 {
2130
2131 MS_BOOL status= true;
2132 MS_U16 u16CenterFreq;
2133 // MS_U16 u16Fc = 0;
2134 MS_U8 temp_val;
2135 MS_U8 u8Data =0;
2136 MS_U8 u8counter = 0;
2137 //MS_U32 u32CurrentSR;
2138
2139 //u32CurrentSR = u32SymbolRate/1000; //KHz
2140
2141 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2142 u16CenterFreq =u32IFFreq;
2143 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_config+, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2144 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_Config, t = %d\n",MsOS_GetSystemTime()));
2145
2146 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2147 status &= INTERN_DVBS_Reset();
2148
2149 u8DemodLockFlag=0;
2150 /*
2151 // Symbol Rate
2152 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2153 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2154 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2155 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2156 */
2157 #if 0
2158 //======== check SR is right or not ===========
2159 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2160 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2161 u32SR =u8Data;
2162 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2163 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2164 u32SR =((U32)u8Data<<8)|u32SR ;
2165 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2166 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2167 u32SR =((U32)u8Data<<16)|u32SR;
2168 //=================================================
2169 #endif
2170
2171 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2172 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2173 if(bSpecInv)
2174 {
2175 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2176 u8Data|=(0x02);
2177 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2178 }
2179
2180 // TS mode
2181 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2182 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2183 _bSerialTS = bSerialTS;
2184
2185 if (bSerialTS)
2186 {
2187 // serial
2188 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2189 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2190
2191 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2192 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2193 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2194 temp_val|=0x04;
2195 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2196 #else
2197 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2198 temp_val|=0x07;
2199 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2200 #endif
2201 }
2202 else
2203 {
2204 //parallel
2205 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2206 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2207
2208 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2209 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2210 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2211 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2212 temp_val|=0x05;
2213 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2214 #else
2215 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2216 temp_val|=0x07;
2217 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2218 #endif
2219 }
2220 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2221 INTERN_DVBS_Show_Demod_Version();
2222 #endif
2223
2224 //-----------------------------------------------------------
2225 //From INTERN_DVBS_Demod_Restart function.
2226
2227 //FW sw reset
2228 //[0]: 0: SW Reset, 1: Start state machine
2229 //[1]: 1: Blind scan enable, 0: manual scan
2230 //[2]: 1: Code flow track enable
2231 //[3]: 1: go to AGC state
2232 //[4]: 1: set DiSEqC
2233 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2234 u8Data = (u8Data&0xF0)|0x01;
2235 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2236 //DBG_INTERN_DVBS(printf(">>>REG write check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2237 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2238 //DBG_INTERN_DVBS(printf(">>>REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2239
2240 u8counter = 20;
2241 while( ((u8Data&0x01) == 0x00) && (u8counter != 0) )
2242 {
2243 MsOS_DelayTask(1);
2244 ULOGD("DEMOD","TOP_WR_DBG_90=0x%x, status=%d, u8counter=%d\n", u8Data, status, u8counter);
2245 u8Data|=0x01;
2246 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
2247 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
2248 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>(while)REG read check: addr=%d value=%d<<<\n",(TOP_REG_BASE + 0x60*2), u8Data));
2249 u8counter--;
2250 }
2251
2252 if((u8Data & 0x01)==0x00)
2253 {
2254 status = FALSE;
2255 }
2256
2257 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_config done\n"));
2258 return status;
2259 }
2260 /************************************************************************************************
2261 Subject: channel change config
2262 Function: INTERN_DVBS_Blind_Scan_Config
2263 Parmeter: BW: bandwidth
2264 Return: MS_BOOL :
2265 Remark:
2266 *************************************************************************************************/
INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate,DMD_DVBS_MODULATION_TYPE eQamMode,MS_U32 u32IFFreq,MS_BOOL bSpecInv,MS_BOOL bSerialTS,MS_U8 u8TSClk,MS_U16 * pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)2267 MS_BOOL INTERN_DVBS_BlindScan_Config(MS_U32 u32SymbolRate, DMD_DVBS_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num)
2268 {
2269
2270 MS_BOOL status= true;
2271 MS_U16 u16CenterFreq;
2272 // MS_U16 u16Fc = 0;
2273 MS_U8 temp_val;
2274 MS_U8 u8Data=0;
2275 MS_U16 u16WaitCount = 0;
2276
2277 //MS_U32 u32CurrentSR;
2278
2279 //u32CurrentSR = u32SymbolRate/1000; //KHz
2280
2281 //u32SymbolRate= u32SymbolRate/1000;//to match fw format
2282 u16CenterFreq =u32IFFreq;
2283
2284 //DBG_INTERN_DVBS(printf(" @INTERN_DVBS_blindScan_Config+, SR=%d, QAM=%d, u32IFFreq=%d, bSpecInv=%d, bSerialTS=%d, u8TSClk=%d\n", u32CurrentSR, eQamMode, u32IFFreq, bSpecInv, bSerialTS, u8TSClk));
2285 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_blindScan_Config, t = %d\n",MsOS_GetSystemTime()));
2286
2287 //status &= INTERN_DVBS_Reset();
2288 /*
2289 g_dvbs_lock = 0;
2290 u8DemodLockFlag=0;
2291 // Symbol Rate
2292 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, u32CurrentSR&0xff);
2293 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, (u32CurrentSR>>8)&0xff);
2294 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, (u32CurrentSR>>16)&0xff);
2295 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_Config u32SymbolRate %d<<<\n", u32CurrentSR));
2296 */
2297 #if 0
2298 //======== check SR is right or not ===========
2299 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &u8Data);
2300 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L,u8Data));
2301 u32SR =u8Data;
2302 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &u8Data);
2303 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H addr=%d mailbox value=%d<<<\n", E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H,u8Data));
2304 u32SR =((U32)u8Data<<8)|u32SR ;
2305 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &u8Data);
2306 DBG_INTERN_DVBS(printf(">>>Mailbox read: E_DMD_S2_MB_DMDTOP_DBG_5 addr=%d mailbox value=%d<<<\n", E_DMD_S2_MB_DMDTOP_DBG_5,u8Data));
2307 u32SR =((U32)u8Data<<16)|u32SR;
2308 //=================================================
2309 #endif
2310
2311 // IQ Swap ,ADCPLL IQ swap / DMDANA_IQ_SWAP
2312 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_IQ_SWAP, bSpecInv? 0x01:0x00);
2313 if(bSpecInv)
2314 {
2315 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DMDANA_REG_BASE+0xC0, &u8Data);//Demod\reg_dmdana.xls
2316 u8Data|=(0x02);
2317 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DMDANA_REG_BASE+0xC0, u8Data);
2318 }
2319
2320 // TS mode
2321 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_TS_SERIAL, bSerialTS? 0x01:0x00);
2322 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Config TS Serial %d<<<\n", bSerialTS));
2323 _bSerialTS = bSerialTS;
2324 u8TSClk=0x05;//if (u8TSClk == 0xFF) u8TSClk=0x13;//set a fater speed for initial condition
2325
2326 if (bSerialTS)
2327 {
2328 // serial
2329 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2330 HAL_DMD_RIU_WriteByte(0x103309, 0x04); // reg_ckg_dvbtc_ts@0x04
2331
2332 HAL_DMD_RIU_WriteByte(0x103300, 0x00); // parallel mode: 0x0511 /serial mode 0x0400
2333 #if(INTERN_DVBS_TS_SERIAL_INVERSION == 0)
2334 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2335 temp_val|=0x04;
2336 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2337 #else
2338 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2339 temp_val|=0x07;
2340 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2341 #endif
2342 }
2343 else
2344 {
2345 //parallel
2346 HAL_DMD_RIU_WriteByte(0x103308, 0x01); // parallel mode:0x0001 / serial mode: 0x0401
2347 HAL_DMD_RIU_WriteByte(0x103309, 0x00); // reg_ckg_dvbtc_ts@0x04
2348
2349 //HAL_DMD_RIU_WriteByte(0x103300, 0x11); // parallel mode: 0x0511 => ts_clk=288/(2*(0x11+1))=8MHz
2350 HAL_DMD_RIU_WriteByte(0x103300, u8TSClk); // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
2351 #if(INTERN_DVBS_TS_PARALLEL_INVERSION == 0)
2352 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2353 temp_val|=0x05;
2354 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2355 #else
2356 temp_val=HAL_DMD_RIU_ReadByte(0x103301);
2357 temp_val|=0x07;
2358 HAL_DMD_RIU_WriteByte(0x103301,temp_val);
2359 #endif
2360 }
2361 #if (INTERN_DVBS_INTERNAL_DEBUG == 1)
2362 INTERN_DVBS_Show_Demod_Version();
2363 #endif
2364
2365 //-----------------------------------------------------------
2366 //From INTERN_DVBS_Demod_Restart function.
2367
2368 //enable send DiSEqC
2369 //[0]: 0: SW Reset, 1: Start state machine
2370 //[1]: 1: Blind scan enable, 0: manual scan
2371 //[2]: 1: Code flow track enable
2372 //[3]: 1: go to AGC state
2373 //[4]: 1: set DiSEqC
2374 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2375 u8Data |= 0x08;
2376 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2377
2378 u16WaitCount=0;
2379 do
2380 {
2381 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
2382 u16WaitCount++;
2383 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
2384 MsOS_DelayTask(1);
2385 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
2386
2387 // disable blind scan
2388 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2389 u8Data&=~(0x02);
2390 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2391
2392 //disble send DiSEqC
2393 MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2394 u8Data&=~(0x08);
2395 MDrv_SYS_DMD_VD_MBX_WriteReg((TOP_REG_BASE + 0x60*2), u8Data);
2396
2397
2398 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_blindScan_Config done\n"));
2399 return status;
2400 }
2401
INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)2402 void INTERN_DVBS_Power_ON_OFF(MS_U8 bPowerOn)
2403 {
2404 bPowerOn = bPowerOn;
2405 }
2406
INTERN_DVBS_Power_Save(void)2407 MS_BOOL INTERN_DVBS_Power_Save(void)
2408 {
2409 return TRUE;
2410 }
2411 //------------------------------------------------------------------
2412 // END System Info Function
2413 //------------------------------------------------------------------
2414
2415 //------------------------------------------------------------------
2416 // Get And Show Info Function
2417 //------------------------------------------------------------------
2418 /************************************************************************************************
2419 Subject: enable hw to lock channel
2420 Function: INTERN_DVBS_Active
2421 Parmeter: bEnable
2422 Return: MS_BOOL
2423 Remark:
2424 *************************************************************************************************/
INTERN_DVBS_Active(MS_BOOL bEnable)2425 MS_BOOL INTERN_DVBS_Active(MS_BOOL bEnable)
2426 {
2427 MS_U8 status = TRUE;
2428 //MS_U8 u8Data;
2429
2430 DBG_INTERN_DVBS(ULOGD("DEMOD"," @INTERN_DVBS_Active\n"));
2431
2432 //// INTERN_DVBS Finite State Machine on/off //////////
2433 #if 0
2434 gsCmdPacketDVBC.cmd_code = CMD_FSM_CTRL;
2435
2436 gsCmdPacketDVBS.param[0] = (MS_U8)bEnable;
2437 status &= INTERN_DVBS_Cmd_Packet_Send(&gsCmdPacketDVBS, 1);
2438 #else
2439
2440 HAL_DMD_RIU_WriteByte(MBRegBase + (0x0e)*2, 0x01); // FSM_EN
2441 #endif
2442
2443 bDMD_DVBS_NoChannelDetectedWithRFPower = FALSE;
2444 u32DMD_DVBS_NoChannelTimeAccWithRFPower = 0;
2445 return status;
2446 }
2447
INTERN_DVBS_GetTsDivNum(MS_U32 * u32SymbolRate,MS_U8 * system_type_reg,MS_U8 * code_rate_idx,MS_U8 * fec_type_idx,MS_U8 * pilot_flag,MS_U32 * u32temp,MS_U8 * code_rate_reg)2448 MS_BOOL INTERN_DVBS_GetTsDivNum(MS_U32 *u32SymbolRate, MS_U8* system_type_reg, MS_U8 *code_rate_idx, MS_U8 *fec_type_idx, MS_U8 *pilot_flag, MS_U32 *u32temp, MS_U8 *code_rate_reg)
2449 {
2450 MS_U8 u8Data = 0;
2451 MS_BOOL status = true;
2452 //MS_U32 u32SymbolRate=0;
2453 //float fSymbolRate;
2454 //MS_U8 ISSY_EN = 0;
2455 //MS_U8 code_rate_idx = 0;
2456 //MS_U8 pilot_flag = 0;
2457 // MS_U8 fec_type_idx = 0;
2458 MS_U8 mod_type_idx = 0;
2459 //MS_U16 k_bch_array[2][11] ={
2460 // {16008, 21408, 25728, 32208, 38688, 43040, 48408, 51648, 53840, 57472, 58192},
2461 // { 3072, 5232, 6312, 7032, 9552, 10632, 11712, 12432, 13152, 14232, 0}};
2462 //MS_U16 n_ldpc_array[2] = {64800, 16200};
2463 //MS_FLOAT pilot_term = 0;
2464 //MS_FLOAT k_bch;
2465 //MS_FLOAT n_ldpc;
2466 //MS_FLOAT ts_div_num_offset = 2.0;
2467 //MS_U32 u32Time_start,u32Time_end;
2468 //MS_U32 u32temp;
2469 //MS_FLOAT pkt_interval;
2470 //MS_U8 time_counter=0;
2471
2472 INTERN_DVBS_GetCurrentSymbolRate(u32SymbolRate);
2473 //fSymbolRate=u32SymbolRate+0.0;///1000.0;//Symbol Rate(KHz)
2474 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum u32SymbolRate=%d\n", *u32SymbolRate));
2475 // DMD_DVBS_MODULATION_TYPE pQAMMode;
2476
2477 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
2478 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum GetCurrentDemodType E_DMD_S2_SYSTEM_TYPE=%d\n", u8Data));//u8Data:0 is S2; 1 is DVBS
2479 *system_type_reg=u8Data;
2480 if(!u8Data)//DVBS2
2481 {
2482 /*
2483 //Get DVBS2 Code Rate
2484 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);//V
2485 printf("[S2]INTERN_DVBS_GetTsDivNum DVBS2 E_DMD_S2_CODERATE=0x%x\n", u8Data);
2486 switch (u8Data)
2487 {
2488 case 0x03: //CR 1/2
2489 k_bch=32208.0;
2490 _u8_DVBS2_CurrentCodeRate = 5;
2491 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
2492 break;
2493 case 0x01: //CR 1/3
2494 k_bch=21408.0; //8PSK???
2495 _u8_DVBS2_CurrentCodeRate = 6;
2496 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
2497 break;
2498 case 0x05: //CR 2/3
2499 k_bch=43040.0;
2500 _u8_DVBS2_CurrentCodeRate = 7;
2501 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
2502 break;
2503 case 0x00: //CR 1/4
2504 k_bch=16008.0; //8PSK???
2505 _u8_DVBS2_CurrentCodeRate = 8;
2506 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
2507 break;
2508 case 0x06: //CR 3/4
2509 k_bch=48408.0;
2510 _u8_DVBS2_CurrentCodeRate = 9;
2511 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
2512 break;
2513 case 0x02: //CR 2/5
2514 k_bch=25728.0; //8PSK???
2515 _u8_DVBS2_CurrentCodeRate = 10;
2516 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
2517 break;
2518 case 0x04: //CR 3/5
2519 k_bch=38688.0;
2520 _u8_DVBS2_CurrentCodeRate = 11;
2521 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
2522 break;
2523 case 0x07: //CR 4/5
2524 k_bch=51648.0;
2525 _u8_DVBS2_CurrentCodeRate = 12;
2526 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
2527 break;
2528 case 0x08: //CR 5/6
2529 k_bch=53840.0;
2530 _u8_DVBS2_CurrentCodeRate = 13;
2531 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
2532 break;
2533 case 0x09: //CR 8/9
2534 k_bch=57472.0;
2535 _u8_DVBS2_CurrentCodeRate = 14;
2536 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
2537 break;
2538 case 0x0A: //CR 9/10
2539 k_bch=58192.0;
2540 _u8_DVBS2_CurrentCodeRate = 15;
2541 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
2542 break;
2543 default:
2544 k_bch=58192.0;
2545 _u8_DVBS2_CurrentCodeRate = 15;
2546 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS2_GetCurrentCodeRate= default 9_10\n"));
2547 break;
2548 } //printf("INTERN_DVBS_GetTsDivNum k_bch=%ld\n", (MS_U32)k_bch);
2549 */
2550 //INTERN_DVBS_GetCurrentModulationType(&pQAMMode); //V
2551 //printf("INTERN_DVBS_GetTsDivNum Mod_order=%d\n", modulation_order);
2552
2553 // pilot_flag => 0 : off 1 : on
2554 // fec_type_idx => 0 : normal 1 : short
2555 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK 3 : 32APSK
2556 // code_rate_idx => d0: 1/4, d1: 1/3, d2: 2/5, d3: 1/2, d4: 3/5, d5: 2/3, d6: 3/4, d7: 4/5, d8: 5/6, d9: 8/9, d10: 9/10
2557 //set TS clock rate
2558 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, code_rate_idx);
2559 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FEC_TYPE, fec_type_idx);
2560 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &mod_type_idx);
2561 modulation_order = mod_type_idx;
2562 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, pilot_flag);
2563 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_PILOT_FLAG, &u8Data);
2564
2565 /*
2566 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_ISSY_ACTIVE, ISSY_EN);
2567 if(*ISSY_EN==0)
2568 {
2569 k_bch = k_bch_array[fec_type_idx][code_rate_idx];
2570 n_ldpc = n_ldpc_array[fec_type_idx];
2571 pilot_term = ((float) n_ldpc / modulation_order / 1440 * 36) * pilot_flag;
2572 if(sDMD_DVBS_Info.bSerialTS)//serial mode
2573 {
2574 *fTSDivNum =(288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)) - ts_div_num_offset);
2575 *fTSDivNum = (*fTSDivNum-1)/2;// since 288/(2(fTSDivNum+1)) = 288/TS_RATE = A ==> fTSDivNum = (A-1)/2
2576 }
2577 else//parallel mode
2578 {
2579 *fTSDivNum = (288000.0/(k_bch/((n_ldpc/modulation_order+90+pilot_term)/u32SymbolRate)/8) - ts_div_num_offset);
2580 *fTSDivNum = (*fTSDivNum-1)/2;
2581 }
2582 }
2583 else if(*ISSY_EN==1)//ISSY = 1
2584 {
2585 //u32Time_start = msAPI_Timer_GetTime0();
2586 time_counter=0;
2587 do
2588 {
2589 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x4D*2), &u8Data);//DVBS2OPPRO_ISCR_CAL_DONE (_REG_DVBS2OPPRO(0x4D)+0)
2590 u8Data &= 0x01;
2591 // u32Time_end =msAPI_Timer_GetTime0();
2592 MsOS_DelayTask(1);
2593 time_counter = time_counter +1;
2594 }while( (u8Data!=0x01) && ( (time_counter )< 50) );
2595
2596 //read pkt interval
2597 MDrv_SYS_DMD_VD_MBX_ReadReg((0x3E00 + 0x70*2), &u8Data);
2598 *u32temp = u8Data;
2599 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x70*2+1), &u8Data);
2600 *u32temp |= (MS_U32)u8Data<<8;
2601 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2), &u8Data);
2602 *u32temp |= (MS_U32)u8Data<<16;
2603 MDrv_SYS_DMD_VD_MBX_ReadReg((DVBS2OPPRO_REG_BASE + 0x71*2+1), &u8Data);
2604 *u32temp |= (MS_U32)u8Data<<24;
2605
2606 pkt_interval = (MS_FLOAT) u32temp / 1024.0;
2607 if(sDMD_DVBS_Info.bSerialTS)//serial mode
2608 {
2609 *fTSDivNum=288000.0 / (188*8*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2610 *fTSDivNum = (*fTSDivNum-1)/2;
2611 }
2612 else
2613 {
2614 *fTSDivNum=288000.0 / (188*u32SymbolRate/pkt_interval) - ts_div_num_offset;
2615 *fTSDivNum = (*fTSDivNum-1)/2;
2616 }
2617
2618 }
2619 else
2620 {
2621 // *fTSDivNum =0x0A;
2622 }
2623
2624 if(*fTSDivNum>255)
2625 *fTSDivNum=255;
2626 if(*fTSDivNum<1)
2627 *fTSDivNum=1;
2628 */
2629 #if 0
2630 //printf("INTERN_DVBS_GetTsDivNum Pilot E_DMD_S2_MB_DMDTOP_DBG_9=%d\n", u8Data);
2631 /*if(u8Data) // Pilot ON
2632 printf(">>>INTERN_DVBS_GetTsDivNum Pilot ON<<<\n");
2633 else //Pilot off
2634 printf(">>>INTERN_DVBS_GetTsDivNum Pilot off<<<\n");
2635 */
2636 if(_bSerialTS)
2637 {
2638 if(u8Data)//if pilot ON
2639 {
2640 if(modulation_order==2)
2641 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*22)/u32SymbolRate)) - 3);
2642 else if(modulation_order==3)
2643 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90+36*15)/u32SymbolRate)) - 3);
2644 }
2645 else
2646 *u8TSDivNum = (MS_U8)(144000/(k_bch/((64800/modulation_order+90)/u32SymbolRate)) - 3);
2647 }
2648 else//Parallel mode
2649 {
2650 if(u8Data)
2651 {
2652 if(modulation_order==2)
2653 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*22)/u32SymbolRate)/8.0) - 3);
2654 else if(modulation_order==3)
2655 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0+36*15)/u32SymbolRate)/8.0) - 3);
2656 }
2657 else
2658 *u8TSDivNum = (MS_U8)(float)(144000/(k_bch/((64800/modulation_order+90.0)/u32SymbolRate)/8.0) - 3);
2659 }
2660 #endif
2661 }
2662 else //S
2663 {
2664 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
2665 //u8_gCodeRate = (u8Data & 0x70)>>4;
2666 //DVBS Code Rate
2667 //switch (u8_gCodeRate)
2668 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
2669 *code_rate_reg=u8Data;
2670 switch (u8Data)
2671 {
2672 case 0x00: //CR 1/2
2673 _u8_DVBS2_CurrentCodeRate = 0;
2674 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
2675 /*
2676 if(sDMD_DVBS_Info.bSerialTS)
2677 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2678 else
2679 *fTSDivNum = (288000.0/((1.0/2.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2680
2681 *fTSDivNum = (*fTSDivNum-1)/2;
2682 if(*fTSDivNum>255)
2683 *fTSDivNum=255;
2684 if(*fTSDivNum<1)
2685 *fTSDivNum=1;
2686 */
2687 break;
2688 case 0x01: //CR 2/3
2689 _u8_DVBS2_CurrentCodeRate = 1;
2690 DBG_INTERN_DVBS(printf("INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
2691 /*
2692 if(sDMD_DVBS_Info.bSerialTS)
2693 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2694 else
2695 *fTSDivNum = (MS_U8)(288000.0/((2.0/3.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2696
2697 *fTSDivNum = (*fTSDivNum-1)/2;
2698 if(*fTSDivNum>255)
2699 *fTSDivNum=255;
2700 if(*fTSDivNum<1)
2701 *fTSDivNum=1;
2702 */
2703 break;
2704 case 0x02: //CR 3/4
2705 _u8_DVBS2_CurrentCodeRate = 2;
2706 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
2707 /*
2708 if(sDMD_DVBS_Info.bSerialTS)
2709 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2710 else
2711 *fTSDivNum = (288000.0/((3.0/4.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2712 *fTSDivNum = (*fTSDivNum-1)/2;
2713 if(*fTSDivNum>255)
2714 *fTSDivNum=255;
2715 if(*fTSDivNum<1)
2716 *fTSDivNum=1;
2717 */
2718 break;
2719 case 0x03: //CR 5/6
2720 _u8_DVBS2_CurrentCodeRate = 3;
2721 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
2722 /*
2723 if(sDMD_DVBS_Info.bSerialTS)
2724 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2725 else
2726 *fTSDivNum = (288000.0/((5.0/6.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2727
2728 *fTSDivNum = (*fTSDivNum-1)/2;
2729 if(*fTSDivNum>255)
2730 *fTSDivNum=255;
2731 if(*fTSDivNum<1)
2732 *fTSDivNum=1;
2733 */
2734 break;
2735 case 0x04: //CR 7/8
2736 _u8_DVBS2_CurrentCodeRate = 4;
2737 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
2738 /*
2739 if(sDMD_DVBS_Info.bSerialTS)
2740 *fTSDivNum =(288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2741 else
2742 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2743
2744 *fTSDivNum = (*fTSDivNum-1)/2;
2745 if(*fTSDivNum>255)
2746 *fTSDivNum=255;
2747 if(*fTSDivNum<1)
2748 *fTSDivNum=1;
2749 */
2750 break;
2751 default:
2752 _u8_DVBS2_CurrentCodeRate = 4;
2753 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetTsDivNum INTERN_DVBS_GetCurrentCodeRate= default 7_8\n"));
2754 /*
2755 if(sDMD_DVBS_Info.bSerialTS)
2756 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2) - 5);
2757 else
2758 *fTSDivNum = (288000.0/((7.0/8.0)*(188.0/204.0)*u32SymbolRate*2/8.0) - 5);
2759
2760 *fTSDivNum = (*fTSDivNum-1)/2;
2761 if(*fTSDivNum>255)
2762 *fTSDivNum=255;
2763 if(*fTSDivNum<1)
2764 *fTSDivNum=1;
2765 */
2766 break;
2767 }
2768 } //printf("INTERN_DVBS_GetTsDivNum u8TSClk = 0x%x\n", *u8TSDivNum);
2769 return status;
2770 }
2771
INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType,MS_U16 fCurrRFPowerDbm,MS_U16 fNoChannelRFPowerDbm,MS_U32 u32TimeInterval)2772 MS_BOOL INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK_TYPE eType, MS_U16 fCurrRFPowerDbm, MS_U16 fNoChannelRFPowerDbm, MS_U32 u32TimeInterval)
2773 {
2774 MS_U8 u8Data =0; //MS_U8 u8Data2 =0;
2775 MS_U8 bRet = TRUE;
2776 //MS_FLOAT fTSDivNum=0;
2777
2778 switch( eType )
2779 {
2780 case DMD_DVBS_GETLOCK:
2781 #if (INTERN_DVBS_INTERNAL_DEBUG)
2782 INTERN_DVBS_info();
2783 #endif
2784 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg((TOP_REG_BASE + 0x60*2), &u8Data);
2785 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_GetLock manual tune=%d<<<\n", u8Data));
2786 if ((u8Data&0x02)==0x00)//manual mode
2787 {
2788 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
2789 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_GetLock MailBox state=%d<<<\n", u8Data));
2790
2791 if((u8Data == 15) || (u8Data == 16))
2792 {
2793 if (u8Data==15)
2794 {
2795 _bDemodType=FALSE; //S
2796 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS Lock<<<\n"));
2797 }
2798 else if(u8Data==16)
2799 {
2800 _bDemodType=TRUE; //S2
2801 DBG_INTERN_DVBS(ULOGD("DEMOD",">>>INTERN_DVBS_Demod DVBS2 Lock<<<\n"));
2802 }
2803 if(g_dvbs_lock == 0)
2804 {
2805 g_dvbs_lock = 1;
2806 }
2807
2808 if(u8DemodLockFlag==0)
2809 {
2810 u8DemodLockFlag=1;
2811
2812 // caculate TS clock divider number
2813 /*
2814 INTERN_DVBS_GetTsDivNum(&fTSDivNum); //ts_div_num
2815 u8Data = (MS_U8)fTSDivNum;
2816 DBG_INTERN_DVBS(printf(">>>INTERN_DVBS_GetLock TsClkDivNum = 0x%x<<<\n", u8Data));
2817
2818 if (u8Data > 0x1F)
2819 u8Data=0x1F;
2820 //if (u8Data < 0x05) u8Data=0x05;
2821 HAL_DMD_RIU_WriteByte(0x103300, u8Data);
2822
2823 //Ts Output Enable
2824 HAL_DMD_RIU_WriteByte(0x101eaa,0x10);
2825 */
2826 }
2827 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod Lock+++\n"));
2828 bRet = TRUE;
2829 }
2830 else
2831 {
2832 if(g_dvbs_lock == 1)
2833 {
2834 g_dvbs_lock = 0;
2835 u8DemodLockFlag=0;
2836 }
2837 DBG_INTERN_DVBS(ULOGD("DEMOD","@INTERN_DVBS_Demod UnLock---\n"));
2838 bRet = FALSE;
2839 }
2840
2841 if(_bSerialTS==1)
2842 {
2843 if (bRet==FALSE)
2844 {
2845 _bTSDataSwap=FALSE;
2846 }
2847 else
2848 {
2849 if (_bTSDataSwap==FALSE)
2850 {
2851 _bTSDataSwap=TRUE;
2852 MDrv_SYS_DMD_VD_MBX_ReadReg( (DVBTM_REG_BASE + 0x20*2), &u8Data);//DVBTM_REG_BASE
2853 u8Data^=0x20;//h0020 h0020 5 5 reg_ts_data_reverse
2854 MDrv_SYS_DMD_VD_MBX_WriteReg( (DVBTM_REG_BASE + 0x20*2), u8Data);
2855 }
2856 }
2857 }
2858 }
2859 else
2860 {
2861 bRet = TRUE;
2862 }
2863 break;
2864
2865 default:
2866 bRet = FALSE;
2867 }
2868 return bRet;
2869 }
2870
INTERN_DVBS_GetTunrSignalLevel_PWR(MS_U16 * u16Data)2871 MS_BOOL INTERN_DVBS_GetTunrSignalLevel_PWR(MS_U16 *u16Data)// Need check debug out table
2872 {
2873 MS_BOOL status=TRUE;
2874 MS_U8 u8Data =0;
2875 //MS_U8 u8Index =0;
2876 //float fCableLess = 0.0;
2877 /*
2878 if (FALSE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0) )//Demod unlock
2879 {
2880 fCableLess = 0;
2881 }
2882 */
2883 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x11*2, &u8Data);//FRONTEND_AGC_DEBUG_SEL
2884 u8Data=(u8Data&0xF0)|0x03;
2885 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x11*2, u8Data);
2886
2887 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LATCH
2888 u8Data|=0x80;
2889 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
2890
2891 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2+1, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R1
2892 *u16Data=u8Data;
2893 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x12*2, &u8Data);//FRONTEND_AGC_DEBUG_OUT_R0
2894 *u16Data=(*u16Data<<8)|u8Data;
2895 //printf("===========================Tuner 65535-u16Data = %d\n", (65535-u16Data));
2896 //MsOS_DelayTask(400);
2897
2898 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE+0x02, &u8Data);//FRONTEND_LOAD0
2899 u8Data&=~(0x80);
2900 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE+0x02, u8Data);
2901 /*
2902 if (status==FALSE)
2903 {
2904 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSignalStrength fail!!! \n "));
2905 fCableLess = 0;
2906 }
2907 */
2908 // printf("#### INTERN_DVBS_GetTunrSignalLevel_PWR u16Data = %d\n", (int)u16Data);
2909 /*
2910 for (u8Index=0; u8Index < (sizeof(_u16SignalLevel)/sizeof(_u16SignalLevel[0])); u8Index++)
2911 {
2912 if ((65535 - u16Data) <= _u16SignalLevel[u8Index][0])
2913 {
2914 if (u8Index >=1)
2915 {
2916 fCableLess = (float)(_u16SignalLevel[u8Index][1])+((float)(_u16SignalLevel[u8Index][0] - (65535 - u16Data)) / (float)(_u16SignalLevel[u8Index][0] - _u16SignalLevel[u8Index-1][0]))*(float)(_u16SignalLevel[u8Index-1][1] - _u16SignalLevel[u8Index][1]);
2917 }
2918 else
2919 {
2920 fCableLess = _u16SignalLevel[u8Index][1];
2921 }
2922 }
2923 }
2924 //---------------------------------------------------
2925 if (fCableLess >= 350)
2926 fCableLess = fCableLess - 35;
2927 else if ((fCableLess < 350) && (fCableLess >= 250))
2928 fCableLess = fCableLess - 25;
2929 else
2930 fCableLess = fCableLess - 5;
2931
2932 if (fCableLess < 0)
2933 fCableLess = 0;
2934 if (fCableLess > 920)
2935 fCableLess = 920;
2936
2937 fCableLess = (-1.0)*(fCableLess/10.0);
2938
2939 //printf("===========================fCableLess2 = %.2f\n",fCableLess);
2940
2941 DBG_INTERN_DVBS(printf("INTERN_DVBS GetSignalStrength %f\n", fCableLess));
2942 */
2943 return status;
2944 }
2945
2946 /****************************************************************************
2947 Subject: To get the Post viterbi BER
2948 Function: INTERN_DVBS_GetPostViterbiBer
2949 Parmeter: Quility
2950 Return: E_RESULT_SUCCESS
2951 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBC_VIT_STATUS_NG
2952 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
2953 We will not read the Period, and have the "/256/8"
2954 *****************************************************************************/
2955
INTERN_DVBS_GetPostViterbiBer(MS_U32 * BitErr,MS_U16 * BitErrPeriod)2956 MS_BOOL INTERN_DVBS_GetPostViterbiBer(MS_U32 *BitErr, MS_U16 *BitErrPeriod)//POST BER //V
2957 {
2958 MS_BOOL status = true;
2959 MS_U8 reg = 0, reg_frz = 0;
2960 //MS_U16 BitErrPeriod;
2961 //MS_U32 BitErr;
2962
2963 /////////// Post-Viterbi BER /////////////After Viterbi
2964
2965 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
2966 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1*2+1, ®_frz);//h0001 h0001 8 8 reg_ber_en
2967 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz|0x01);
2968
2969 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
2970 // 0x47 [15:8] reg_bit_err_sblprd_15_8
2971 //KRIS register table
2972 //h0018 h0018 7 0 reg_bit_err_sblprd_7_0
2973 //h0018 h0018 15 8 reg_bit_err_sblprd_15_8
2974 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2+1, ®);
2975 *BitErrPeriod = reg;
2976
2977 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x18*2, ®);
2978 *BitErrPeriod = (*BitErrPeriod << 8)|reg;
2979
2980
2981 //h001d h001d 7 0 reg_bit_err_num_7_0
2982 //h001d h001d 15 8 reg_bit_err_num_15_8
2983 //h001e h001e 7 0 reg_bit_err_num_23_16
2984 //h001e h001e 15 8 reg_bit_err_num_31_24
2985
2986 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2+1, ®);
2987 *BitErr = reg;
2988 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1E*2, ®);
2989 *BitErr = (*BitErr << 8)|reg;
2990 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2+1, ®);
2991 *BitErr = (*BitErr << 8)|reg;
2992 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x1D*2, ®);
2993 *BitErr = (*BitErr << 8)|reg;
2994
2995 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
2996 reg_frz=reg_frz&(~0x01);
2997 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x1*2+1, reg_frz);
2998 /*
2999 if (BitErrPeriod == 0 ) //PRD
3000 BitErrPeriod = 1;
3001
3002 if (BitErr <= 0 )
3003 *postber = 0.5f / ((float)BitErrPeriod*128*188*8);
3004 else
3005 *postber = (float)BitErr / ((float)BitErrPeriod*128*188*8);
3006
3007 if (*postber <= 0.0f)
3008 *postber = 1.0e-10f;
3009
3010 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PostVitBER = %8.3e \n", *postber));
3011 */
3012 return status;
3013 }
3014
3015
INTERN_DVBS_GetPreViterbiBer(float * preber)3016 MS_BOOL INTERN_DVBS_GetPreViterbiBer(float *preber)//PER BER // not yet
3017 {
3018 MS_BOOL status = true;
3019 //MS_U8 reg = 0, reg_frz = 0;
3020 //MS_U16 BitErrPeriod;
3021 //MS_U32 BitErr;
3022
3023 #if 0
3024 /////////// Pre-Viterbi BER /////////////Before Viterbi
3025
3026 // freeze ,DVBSRS_BACKEND_BIT_ERR_NUM_FREEZE
3027 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x10, ®_frz);
3028 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSTFEC_REG_BASE+0x10, reg_frz|0x08);
3029
3030 // bank 1f 0x46 [7:0] reg_bit_err_sblprd_7_0 ,DVBSFEC_BIT_ERR_SBLPRD_7_0
3031 // 0x47 [15:8] reg_bit_err_sblprd_15_8
3032 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x19, ®);
3033 BitErrPeriod = reg;
3034
3035 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x18, ®);
3036 BitErrPeriod = (BitErrPeriod << 8)|reg;
3037
3038 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x17, ®);
3039 BitErrPeriod = (BitErrPeriod << 8)|reg;
3040
3041 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x16, ®);
3042 BitErrPeriod = (BitErrPeriod << 8)|reg;
3043 BitErrPeriod = (BitErrPeriod & 0x3FFF);
3044
3045 // bank 1f 0x6a [7:0] reg_bit_err_num_7_0
3046 // 0x6b [15:8] reg_bit_err_num_15_8
3047 // bank 1f 0x6c [7:0] reg_bit_err_num_23_16
3048 // 0x6d [15:8] reg_bit_err_num_31_24
3049 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1F, ®);
3050 BitErr = reg;
3051
3052 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE+0x1E, ®);
3053 BitErr = (BitErr << 8)|reg;
3054
3055 // bank 1f 0x03 [1:0] reg_bit_err_num_freeze
3056 reg_frz=reg_frz&(~0x08);
3057 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x10, reg_frz);
3058
3059 if (BitErrPeriod ==0 )//protect 0
3060 BitErrPeriod=1;
3061 if (BitErr <=0 )
3062 *perber=0.5f / (float)BitErrPeriod / 256;
3063 else
3064 *perber=(float)BitErr / (float)BitErrPeriod / 256;
3065
3066 if (*perber <= 0.0f)
3067 *perber = 1.0e-10f;
3068
3069 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS PerVitBER = %8.3e \n", *perber));
3070 #endif
3071
3072 return status;
3073 }
3074
3075 /****************************************************************************
3076 Subject: To get the Packet error
3077 Function: INTERN_DVBS_GetPacketErr
3078 Parmeter: pktErr
3079 Return: E_RESULT_SUCCESS
3080 E_RESULT_FAILURE =>Read I2C fail, INTERN_DVBT_VIT_STATUS_NG
3081 Remark: For the Performance issue, here we just return the Post Value.(Not BER)
3082 We will not read the Period, and have the "/256/8"
3083 *****************************************************************************/
INTERN_DVBS_GetPacketErr(MS_U16 * pktErr)3084 MS_BOOL INTERN_DVBS_GetPacketErr(MS_U16 *pktErr)//V
3085 {
3086 MS_BOOL status = true;
3087 MS_U8 u8Data = 0;
3088 MS_U16 u16PktErr = 0;
3089
3090 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3091 if(!u8Data) //DVB-S2
3092 {
3093 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);//DVBS2FEC_OUTER_FREEZE (_REG_DVBS2FEC(0x02)+0) //[0]
3094 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data|0x01);
3095
3096 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2+1, &u8Data);//DVBS2FEC_BCH_EFLAG2_SUM1 (_REG_DVBS2FEC(0x2B)+1)
3097 u16PktErr = u8Data;
3098 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x26*2, &u8Data);
3099 u16PktErr = (u16PktErr << 8)|u8Data;
3100
3101 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2FEC_REG_BASE+0x02*2, &u8Data);
3102 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE+0x02*2, u8Data&(~0x01));
3103 }
3104 else
3105 { //DVB-S
3106 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3107 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data|0x80);
3108
3109 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2+1, &u8Data);// DVBSFEC_UNCRT_PKT_NUM_15_8 (_REG_DVBSFEC(0x1F)+1)
3110 u16PktErr = u8Data;
3111 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(REG_BACKEND+0x33*2, &u8Data);
3112 u16PktErr = (u16PktErr << 8)|u8Data;
3113
3114 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE+0x19*2, &u8Data); //0x19 [7] reg_bit_err_num_freeze
3115 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBSFEC_REG_BASE+0x19*2, u8Data&(~0x80));
3116 }
3117 *pktErr = u16PktErr;
3118
3119 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS PktErr = %d \n", (int)u16PktErr));
3120
3121 return status;
3122 }
3123
3124 /****************************************************************************
3125 Subject: Read the signal to noise ratio (SNR)
3126 Function: INTERN_DVBS_GetSNR
3127 Parmeter: None
3128 Return: -1 mean I2C fail, otherwise I2C success then return SNR value
3129 Remark:
3130 *****************************************************************************/
3131
INTERN_DVBS_GetSNR(MS_U32 * u32NDA_SNR_A,MS_U32 * u32NDA_SNR_AB)3132 MS_BOOL INTERN_DVBS_GetSNR(MS_U32 *u32NDA_SNR_A, MS_U32 *u32NDA_SNR_AB)//V
3133 {
3134 MS_BOOL status= TRUE;
3135 MS_U8 u8Data =0, reg_frz =0;
3136 //NDA SNR
3137 // MS_U32 u32NDA_SNR_A =0;
3138 //MS_U32 u32NDA_SNR_AB =0;
3139 //NDA SNR
3140 //float NDA_SNR_A =0.0;
3141 //float NDA_SNR_AB =0.0;
3142 //float NDA_SNR =0.0;
3143 //double NDA_SNR_LINEAR=0.0;
3144 //float snr_poly =0.0;
3145 //float Fixed_SNR =0.0;
3146 /*
3147 if (INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0)== FALSE)
3148 {
3149 return 0;
3150 }
3151 */
3152 // freeze
3153 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE+0x04*2, ®_frz);
3154 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x04*2, reg_frz|0x10);//INNE_LATCH bit[4]
3155
3156 //NDA SNR_A
3157 // read Linear_SNR
3158 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x47*2, &u8Data);
3159 *u32NDA_SNR_A=(u8Data&0x03);
3160 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2 + 1, &u8Data);
3161 *u32NDA_SNR_A=(*u32NDA_SNR_A<<8)|u8Data;
3162 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x46*2, &u8Data);
3163 *u32NDA_SNR_A=(*u32NDA_SNR_A<<8)|u8Data;
3164 //NDA SNR_AB
3165 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2+1, &u8Data);
3166 *u32NDA_SNR_AB=(u8Data&0x3F);
3167 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x49*2, &u8Data);
3168 *u32NDA_SNR_AB = (*u32NDA_SNR_AB<<8)|u8Data;
3169 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2 + 1, &u8Data);
3170 *u32NDA_SNR_AB=(*u32NDA_SNR_AB<<8)|u8Data;
3171 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x48*2, &u8Data);
3172 *u32NDA_SNR_AB=(*u32NDA_SNR_AB<<8)|u8Data;
3173
3174 //UN_freeze
3175 reg_frz=reg_frz&(~0x10);
3176 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_INNER_REG_BASE+0x08, reg_frz);
3177
3178 if (status== FALSE)
3179 {
3180 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetSNR Fail! \n"));
3181 return 0;
3182 }
3183
3184 //NDA SNR
3185 //NDA_SNR_A=(float)u32NDA_SNR_A/65536;
3186 //NDA_SNR_AB=(float)u32NDA_SNR_AB/4194304;
3187 //
3188 //since support 16,32APSK we need to add judgement
3189 /*
3190 if(modulation_order==4)
3191 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.252295758529242));//for 16APSK CR2/3
3192 else if(modulation_order==5)//(2-1.41333232789)
3193 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB/(2-1.41333232789));//for 32APSK CR3/4
3194 else
3195 NDA_SNR_AB=(float)sqrt(NDA_SNR_AB);
3196
3197 NDA_SNR_LINEAR =(1/((NDA_SNR_A/NDA_SNR_AB)-1)) ;
3198
3199 if(NDA_SNR_LINEAR<=0)
3200 NDA_SNR=1.0;
3201 else
3202 NDA_SNR=10*log10(NDA_SNR_LINEAR);
3203
3204 //printf("[DVBS]: NDA_SNR ================================: %.1f\n", NDA_SNR);
3205 _f_DVBS_CurrentSNR = NDA_SNR;
3206 */
3207 /*
3208 //[DVBS/S2, QPSK/8PSK, 1/2~9/10 the same CN]
3209 snr_poly = 0.0; //use Polynomial curve fitting to fix SNR
3210 snr_poly = 0.005261367463671*pow(NDA_SNR, 3)-0.116517828301214*pow(NDA_SNR, 2)+0.744836970505452*pow(NDA_SNR, 1)-0.86727609780167;
3211 Fixed_SNR = NDA_SNR + snr_poly;
3212 //printf("[DVBS]: NDA_SNR + snr_poly =====================: %.1f\n", Fixed_SNR);
3213
3214 if (Fixed_SNR < 17.0)
3215 Fixed_SNR = Fixed_SNR;
3216 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3217 Fixed_SNR = Fixed_SNR - 0.8;
3218 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3219 Fixed_SNR = Fixed_SNR - 2.0;
3220 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3221 Fixed_SNR = Fixed_SNR - 3.0;
3222 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3223 Fixed_SNR = Fixed_SNR - 3.5;
3224 else if (Fixed_SNR >= 29.0)
3225 Fixed_SNR = Fixed_SNR - 3.0;
3226
3227 if (Fixed_SNR < 1.0)
3228 Fixed_SNR = 1.0;
3229 if (Fixed_SNR > 30.0)
3230 Fixed_SNR = 30.0;
3231 */
3232 //*f_snr = NDA_SNR;
3233 //printf("[DVBS]: NDA_SNR=============================: %.1f\n", NDA_SNR);
3234
3235 return status;
3236 }
3237
INTERN_DVBS_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)3238 MS_BOOL INTERN_DVBS_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
3239 {
3240 MS_BOOL status = true;
3241
3242 status = HAL_DMD_IFAGC_RegRead(ifagc_reg, ifagc_reg_lsb, ifagc_err);
3243
3244 return status;
3245 }
3246
3247 //SSI
INTERN_DVBS_GetSignalStrength(MS_U16 fRFPowerDbm,DMD_DVBS_DEMOD_TYPE * pDemodType,MS_U8 * u8_DVBS2_CurrentCodeRateLocal,MS_U8 * u8_DVBS2_CurrentConstellationLocal)3248 MS_BOOL INTERN_DVBS_GetSignalStrength(MS_U16 fRFPowerDbm, DMD_DVBS_DEMOD_TYPE *pDemodType, MS_U8 *u8_DVBS2_CurrentCodeRateLocal, MS_U8 *u8_DVBS2_CurrentConstellationLocal)
3249 {
3250 //-1.2~-92.2 dBm
3251 MS_BOOL status = true;
3252 MS_U8 u8Data =0;
3253 //MS_U8 _u8_DVBS2_CurrentCodeRateLocal = 0;
3254 //float ch_power_db=0.0f, ch_power_db_rel=0.0f;
3255 MS_U8 u8Data2 = 0;
3256 //MS_U8 _u8_DVBS2_CurrentConstellationLocal = 0;
3257 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3258
3259 //DBG_INTERN_DVBS_TIME(printf("INTERN_DVBS_GetSignalStrength, t=%ld, RF level=%f, Table=%lx\n",MsOS_GetSystemTime(), fRFPowerDbm, (MS_U32)(sDMD_DVBS_InitData->pTuner_RfagcSsi)));
3260
3261 // if (INTERN_DVBC_Lock(COFDM_TPS_LOCK))
3262 // if (INTERN_DVBC_Lock(COFDM_AGC_LOCK))
3263 // Actually, it's more reasonable, that signal level depended on cable input power level
3264 // thougth the signal isn't dvb-t signal.
3265 //
3266 // use pointer of IFAGC table to identify
3267 // case 1: RFAGC from SAR, IFAGC controlled by demod
3268 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
3269 //status=HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
3270 // sDMD_DVBS_InitData->pTuner_RfagcSsi, sDMD_DVBS_InitData->u16Tuner_RfagcSsi_Size,
3271 // sDMD_DVBS_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_HiRef_Size,
3272 // sDMD_DVBS_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcSsi_LoRef_Size,
3273 // sDMD_DVBS_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_HiRef_Size,
3274 // sDMD_DVBS_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBS_InitData->u16Tuner_IfagcErr_LoRef_Size);
3275 //ch_power_db = INTERN_DVBS_GetTunrSignalLevel_PWR();
3276 //printf("@@@@@@@@@ ch_power_db = %f \n", ch_power_db);
3277
3278
3279
3280
3281 status &= INTERN_DVBS_GetCurrentDemodType(pDemodType);
3282
3283 if((MS_U8)*pDemodType == (MS_U8)DMD_SAT_DVBS)//S
3284 {
3285 /*
3286 float fDVBS_SSI_Pref[]=
3287 {
3288 //0, 1, 2, 3, 4
3289 -78.9, -77.15, -76.14, -75.19, -74.57,//QPSK
3290 };
3291 */
3292 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSFEC_REG_BASE + 0x84, &u8Data);
3293 *u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x07);
3294 //ch_power_db_rel = ch_power_db - fDVBS_SSI_Pref[_u8_DVBS2_CurrentCodeRateLocal];
3295 }
3296 else
3297 {
3298 /*
3299 float fDVBS2_SSI_Pref[][11]=
3300 {
3301 // 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10
3302 //1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, 9/10
3303 {-85.17, -84.08, -83.15, -81.86, -80.63, -79.77, -78.84, -78.19, -77.69, -76.68, -76.46}, //QPSK
3304 { 0.0, 0.0, 0.0, 0.0, -77.36, -76.24, -74.95, 0.0, -73.52, -72.18, -71.84} //8PSK
3305 };
3306 */
3307 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3308 *u8_DVBS2_CurrentCodeRateLocal = (u8Data & 0x3C)>>2;
3309
3310 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3311 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD6, &u8Data2);
3312
3313 if(((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x00))
3314 {
3315 *u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_QPSK;
3316 }
3317 else if (((u8Data & 0x03)==0x01) && ((u8Data2 & 0x80)==0x80))
3318 {
3319 *u8_DVBS2_CurrentConstellationLocal = DMD_DVBS_8PSK;//8PSK
3320 }
3321 //ch_power_db_rel = ch_power_db - fDVBS2_SSI_Pref[_u8_DVBS2_CurrentConstellationLocal][_u8_DVBS2_CurrentCodeRateLocal];
3322 }
3323 /*
3324 if(ch_power_db_rel <= -15.0f)
3325 {
3326 *pu16SignalBar = 0;
3327 }
3328 else if (ch_power_db_rel <= 0.0f)
3329 {
3330 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel+15.0f));
3331 }
3332 else if (ch_power_db_rel <= 20.0f)
3333 {
3334 *pu16SignalBar = (MS_U16)(4.0f * ch_power_db_rel + 10.0f);
3335 }
3336 else if (ch_power_db_rel <= 35.0f)
3337 {
3338 *pu16SignalBar = (MS_U16)(2.0f/3 * (ch_power_db_rel-20.0f) + 90.0);
3339 }
3340 else
3341 {
3342 *pu16SignalBar = 100;
3343 }
3344 */
3345 //printf("SSI_CH_PWR(dB) = %f \n", ch_power_db_rel);
3346 //DBG_INTERN_DVBS(printf(">>>>>Signal Strength(SSI) = %d\n", (int)*pu16SignalBar));
3347
3348 return status;
3349 }
3350
3351 //SQI
3352 /****************************************************************************
3353 Subject: To get the DVT Signal quility
3354 Function: INTERN_DVBS_GetSignalQuality
3355 Parmeter: Quility
3356 Return: E_RESULT_SUCCESS
3357 E_RESULT_FAILURE
3358 Remark: Here we have 4 level range
3359 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT_SIGNAL_BASE_100)
3360 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT_SIGNAL_BASE_60)
3361 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT_SIGNAL_BASE_10)
3362 <4>.4th Range => Quality <10
3363 *****************************************************************************/
3364 #if (0)
INTERN_DVBS_GetSignalQuality(MS_U16 * quality,const DMD_DVBS_InitData * sDMD_DVBS_InitData,MS_U8 u8SarValue,float fRFPowerDbm)3365 MS_BOOL INTERN_DVBS_GetSignalQuality(MS_U16 *quality, const DMD_DVBS_InitData *sDMD_DVBS_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
3366 {
3367
3368 float fber = 0.0;
3369 //float log_ber;
3370 MS_BOOL status = TRUE;
3371 float f_snr = 0.0, ber_sqi = 0.0, cn_rel = 0.0;
3372 //MS_U8 u8Data =0;
3373 DMD_DVBS_CODE_RATE_TYPE _u8_DVBS2_CurrentCodeRateLocal ;
3374 MS_U16 bchpkt_error,BCH_Eflag2_Window;
3375 //fRFPowerDbm = fRFPowerDbm;
3376 float snr_poly =0.0;
3377 float Fixed_SNR =0.0;
3378 double eFlag_PER=0.0;
3379
3380 if (TRUE == INTERN_DVBS_GetLock(DMD_DVBS_GETLOCK, 200.0f, -200.0f, 0))
3381 {
3382 if(_bDemodType) //S2
3383 {
3384
3385 INTERN_DVBS_GetSNR(&f_snr);
3386 snr_poly = 0.005261367463671*pow(f_snr, 3)-0.116517828301214*pow(f_snr, 2)+0.744836970505452*pow(f_snr, 1)-0.86727609780167;
3387 Fixed_SNR = f_snr + snr_poly;
3388
3389 if (Fixed_SNR < 17.0)
3390 Fixed_SNR = Fixed_SNR;
3391 else if ((Fixed_SNR < 20.0) && (Fixed_SNR >= 17.0))
3392 Fixed_SNR = Fixed_SNR - 0.8;
3393 else if ((Fixed_SNR < 22.5) && (Fixed_SNR >= 20.0))
3394 Fixed_SNR = Fixed_SNR - 2.0;
3395 else if ((Fixed_SNR < 27.0) && (Fixed_SNR >= 22.5))
3396 Fixed_SNR = Fixed_SNR - 3.0;
3397 else if ((Fixed_SNR < 29.0) && (Fixed_SNR >= 27.0))
3398 Fixed_SNR = Fixed_SNR - 3.5;
3399 else if (Fixed_SNR >= 29.0)
3400 Fixed_SNR = Fixed_SNR - 3.0;
3401
3402
3403 if (Fixed_SNR < 1.0)
3404 Fixed_SNR = 1.0;
3405 if (Fixed_SNR > 30.0)
3406 Fixed_SNR = 30.0;
3407
3408 //BCH EFLAG2_Window, window size 0x2000
3409 BCH_Eflag2_Window=0x2000;
3410 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 + 1, (BCH_Eflag2_Window>>8));
3411 MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2FEC_REG_BASE + 0x25*2 , (BCH_Eflag2_Window&0xff));
3412 INTERN_DVBS_GetPacketErr(&bchpkt_error);
3413 eFlag_PER = (float)(bchpkt_error)/(float)(BCH_Eflag2_Window);
3414 if(eFlag_PER>0)
3415 fber = 0.089267531133002*pow(eFlag_PER, 2) + 0.019640560289510*eFlag_PER + 0.0000001;
3416 else
3417 fber = 0;
3418
3419 #ifdef MSOS_TYPE_LINUX
3420 //log_ber = ( - 1) *log10f(1 / fber);
3421 if (fber > 1.0E-1)
3422 ber_sqi = (log10f(1.0f/fber))*20.0f + 8.0f;
3423 else if(fber > 8.5E-7)
3424 ber_sqi = (log10f(1.0f/fber))*20.0f - 30.0f;
3425 else
3426 ber_sqi = 100.0;
3427 #else
3428 //log_ber = ( - 1) *Log10Approx(1 / fber);
3429 if (fber > 1.0E-1)
3430 ber_sqi = (Log10Approx(1.0f/fber))*20.0f + 8.0f;
3431 else if(fber > 8.5E-7)
3432 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 30.0f;
3433 else
3434 ber_sqi = 100.0;
3435
3436 #endif
3437
3438 *quality = Fixed_SNR/30*ber_sqi;
3439 DBG_INTERN_DVBS(printf(" Fixed_SNR %f\n",Fixed_SNR));
3440 DBG_INTERN_DVBS(printf(" BCH_Eflag2_Window %d\n",BCH_Eflag2_Window));
3441 DBG_INTERN_DVBS(printf(" eFlag_PER [%f]\n fber [%8.3e]\n ber_sqi [%f]\n",eFlag_PER,fber,ber_sqi));
3442 }
3443 else //S
3444 {
3445 if (INTERN_DVBS_GetPostViterbiBer(&fber) == FALSE)//ViterbiBer
3446 {
3447 DBG_INTERN_DVBS(printf("\nGetPostViterbiBer Fail!"));
3448 return FALSE;
3449 }
3450 _fPostBer=fber;
3451
3452
3453 if (status==FALSE)
3454 {
3455 DBG_INTERN_DVBS(printf("MSB131X_DTV_GetSignalQuality GetPostViterbiBer Fail!\n"));
3456 return 0;
3457 }
3458 float fDVBS_SQI_CNref[]=
3459 { //0, 1, 2, 3, 4
3460 4.2, 5.9, 6, 6.9, 7.5,//QPSK
3461 };
3462
3463 INTERN_DVBS_GetCurrentDemodCodeRate(&_u8_DVBS2_CurrentCodeRateLocal);
3464 #if 0
3465 #ifdef MSOS_TYPE_LINUX
3466 log_ber = ( - 1.0f) *log10f(1.0f / fber); //BY modify
3467 #else
3468 log_ber = ( - 1.0f) *Log10Approx(1.0f / fber); //BY modify
3469 #endif
3470 DBG_INTERN_DVBS(printf("\nLog(BER) = %f\n",log_ber));
3471 #endif
3472 if (fber > 2.5E-2)
3473 ber_sqi = 0.0;
3474 else if(fber > 8.5E-7)
3475 #ifdef MSOS_TYPE_LINUX
3476 ber_sqi = (log10f(1.0f/fber))*20.0f - 32.0f; //40.0f;
3477 #else
3478 ber_sqi = (Log10Approx(1.0f/fber))*20.0f - 32.0f;//40.0f;
3479 #endif
3480 else
3481 ber_sqi = 100.0;
3482
3483 status &= INTERN_DVBS_GetSNR(&f_snr);
3484 DBG_GET_SIGNAL_DVBS(printf("INTERN_DVBS GetSNR = %d \n", (int)f_snr));
3485
3486 cn_rel = f_snr - fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal];
3487
3488 DBG_INTERN_DVBS(printf(" fber = %f\n",fber));
3489 DBG_INTERN_DVBS(printf(" f_snr = %f\n",f_snr));
3490 DBG_INTERN_DVBS(printf(" cn_nordig_s1 = %f\n",fDVBS_SQI_CNref[_u8_DVBS2_CurrentCodeRateLocal]));
3491 DBG_INTERN_DVBS(printf(" cn_rel = %f\n",cn_rel));
3492 DBG_INTERN_DVBS(printf(" ber_sqi = %f\n",ber_sqi));
3493
3494 if (cn_rel < -7.0f)
3495 {
3496 *quality = 0;
3497 }
3498 else if (cn_rel < 3.0)
3499 {
3500 *quality = (MS_U16)(ber_sqi*((cn_rel - 3.0)/10.0 + 1.0));
3501 }
3502 else
3503 {
3504 *quality = (MS_U16)ber_sqi;
3505 }
3506
3507
3508 }
3509 //INTERN_DVBS_GetTunrSignalLevel_PWR();//For Debug.
3510 DBG_INTERN_DVBS(printf(">>>>>Signal Quility(SQI) = %d\n", *quality));
3511 return TRUE;
3512 }
3513 else
3514 {
3515 *quality = 0;
3516 }
3517
3518 return TRUE;
3519 }
3520 #endif
3521 /****************************************************************************
3522 Subject: To get the Cell ID
3523 Function: INTERN_DVBS_Get_CELL_ID
3524 Parmeter: point to return parameter cell_id
3525
3526 Return: TRUE
3527 FALSE
3528 Remark:
3529 *****************************************************************************/
INTERN_DVBS_Get_CELL_ID(MS_U16 * cell_id)3530 MS_BOOL INTERN_DVBS_Get_CELL_ID(MS_U16 *cell_id)
3531 {
3532 MS_BOOL status = true;
3533 MS_U8 value1 = 0;
3534 MS_U8 value2 = 0;
3535
3536 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2B, &value2); //TPS Cell ID [15:8]
3537 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FDP_REG_BASE+0x2A, &value1); //TPS Cell ID [7:0]
3538
3539 *cell_id = ((MS_U16)value1<<8)|value2;
3540 return status;
3541 }
3542
3543 /****************************************************************************
3544 Subject: To get the DVBC Carrier Freq Offset
3545 Function: INTERN_DVBS_Get_FreqOffset
3546 Parmeter: Frequency offset (in KHz), bandwidth
3547 Return: E_RESULT_SUCCESS
3548 E_RESULT_FAILURE
3549 Remark:
3550 *****************************************************************************/
INTERN_DVBS_Get_FreqOffset(MS_S16 * s16CFO)3551 MS_BOOL INTERN_DVBS_Get_FreqOffset(MS_S16 *s16CFO)
3552 {
3553 MS_U8 u8Data=0;
3554 MS_U16 u16Data;
3555 //MS_S16 s16CFO;
3556 //float FreqOffset;
3557 //MS_U32 u32FreqOffset = 0;
3558 //MS_U8 reg = 0;
3559 MS_BOOL status = TRUE;
3560
3561 DBG_INTERN_DVBS(ULOGD("DEMOD",">>> INTERN_DVBS_Get_FreqOffset DVBS_Estimated_CFO <<<\n"));
3562 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_97, &u8Data);
3563 u16Data=u8Data;
3564 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_96, &u8Data);
3565 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
3566 if (u16Data >= 0x8000)
3567 {
3568 u16Data=0x10000- u16Data;
3569 *s16CFO=-1*u16Data;
3570 }
3571 else
3572 {
3573 *s16CFO=u16Data;
3574 }
3575 DBG_INTERN_DVBS(ULOGD("DEMOD",">>> INTERN_DVBS_Get_FreqOffset CFO = %d[KHz] <<<\n", *s16CFO));
3576 /*
3577 if(abs(s16CFO)%1000 >= 500)
3578 {
3579 if(s16CFO < 0)
3580 *pFreqOff=(s16CFO/1000)-1.0;
3581 else
3582 *pFreqOff=(s16CFO/1000)+1.0;
3583 }
3584 else
3585 *pFreqOff = s16CFO/1000;
3586 DBG_INTERN_DVBS(printf(">>> INTERN_DVBS_Get_FreqOffset *pFreqOff = %d[MHz] <<<\n", (MS_S16)*pFreqOff));
3587 */
3588 // no use.
3589 //u8BW = u8BW;
3590 /*
3591 printf("INTERN_DVBS_Get_FreqOffset\n");//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset\n"));
3592
3593 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x1C*2 + 1, 0x08);
3594
3595 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3596 reg|=0x80;
3597 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3598
3599 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x23*2, ®);
3600 u32FreqOffset=reg;
3601 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2 + 1, ®);
3602 u32FreqOffset=(u32FreqOffset<<8)|reg;
3603 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x22*2, ®);
3604 u32FreqOffset=(u32FreqOffset<<8)|reg;
3605
3606 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x05, ®);
3607 reg&=~(0x80);
3608 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x05, reg);
3609
3610 FreqOffset=(float)u32FreqOffset;
3611 if (FreqOffset>=2048)
3612 {
3613 FreqOffset=FreqOffset-4096;
3614 }
3615 FreqOffset=(FreqOffset/4096)*SAMPLING_RATE_FS;
3616
3617 *pFreqOff = FreqOffset/1000; //KHz
3618 printf("INTERN_DVBS_Get_FreqOffset:%d[MHz]\n", (MS_S16)FreqOffset/1000);//DBG_INTERN_DVBS(printf("INTERN_DVBS_Get_FreqOffset:%f[MHz]\n", FreqOffset/1000));
3619 */
3620
3621 return status;
3622 }
3623
3624 /****************************************************************************
3625 Subject: To get the current modulation type at the DVB-S Demod
3626 Function: INTERN_DVBS_GetCurrentModulationType
3627 Parmeter: pointer for return QAM type
3628
3629 Return: TRUE
3630 FALSE
3631 Remark:
3632 *****************************************************************************/
INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE * pQAMMode)3633 MS_BOOL INTERN_DVBS_GetCurrentModulationType(DMD_DVBS_MODULATION_TYPE *pQAMMode)
3634 {
3635 MS_U8 u8Data=0;
3636 MS_U16 u16tmp=0;
3637 MS_U8 MOD_type;
3638 MS_BOOL status = true;
3639 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3640
3641 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType\n"));
3642
3643 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3644
3645 // read code rate, pilot on/off, long/short FEC type, and modulation type for calculating TOP_DVBTM_TS_CLK_DIVNUM
3646 // pilot_flag => 0 : off 1 : on
3647 // fec_type_idx => 0 : normal 1 : short
3648 // mod_type_idx => 0 : QPSK 1 : 8PSK 2 : 16APSK
3649 // code_rate_idx => 0 : 1/4 1 : 1/3 2 : 2/5 3 : 1/2 4 : 3/5 5 : 2/3
3650 // 6 : 3/4 7 : 4/5 8 : 5/6 9 : 8/9 10 : 9/10
3651 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//V
3652 if(u8Data)
3653 {
3654 *pQAMMode = DMD_DVBS_QPSK;
3655 modulation_order=2;
3656 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3657 //return TRUE;
3658 }
3659 else //S2
3660 {
3661 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x96, &u8Data);
3662 //printf(">>> INTERN_DVBS_GetCurrentModulationType INNER 0x4B = 0x%x <<<\n", u8Data);
3663 //if((u8Data & 0x0F)==0x02) //QPSK
3664 /*MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MOD_TYPE, &u8Data1);
3665 printf("@@@@@E_DMD_S2_MOD_TYPE = %d \n ",u8Data1);
3666 printf("@@@@@ E_DMD_S2_MOD_TYPE=%d \n",E_DMD_S2_MOD_TYPE);
3667
3668 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_IS_ID, &u8Data1);
3669 printf("@@@@@E_DMD_S2_IS_ID = %d \n ",u8Data1);
3670 printf("@@@@@ E_DMD_S2_IS_ID=%d \n",E_DMD_S2_IS_ID);*/
3671
3672 // INNER_DEBUG_SEL
3673 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x04*2+1, &u8Data);
3674 u8Data = u8Data & 0xc0;
3675 MDrv_SYS_DMD_VD_MBX_WriteReg(0x3b00+0x04*2+1, u8Data);
3676
3677 // reg_plscdec_debug_out
3678 // PLSCDEC info
3679 //[0:4] PLSC MODCOD
3680 //[5] dummy frame
3681 //[6] reserve frame
3682 //[7:9] modulation type
3683 //[10:13] code rate type
3684 //[14] FEC type
3685 //[15] pilot type
3686 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2 , &u8Data);
3687 u16tmp = (MS_U16)u8Data;
3688 MDrv_SYS_DMD_VD_MBX_ReadReg(0x3b00+0x6b*2+1 , &u8Data);
3689 u16tmp |= (MS_U16)u8Data << 8;
3690 MOD_type = ((MS_U8)(u16tmp>>7)&0x07); // 2:QPSK, 3:8PSK, 4:16APSK, 5:32APSK
3691
3692 if(MOD_type==2)
3693 {
3694 *pQAMMode = DMD_DVBS_QPSK;
3695 modulation_order=2;
3696 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_QPSK\n"));
3697 //return TRUE;
3698 }
3699 else if(MOD_type==3)
3700 {
3701 *pQAMMode = DMD_DVBS_8PSK;
3702 modulation_order=3;
3703 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_8PSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS2_8PSK\n"));
3704 //return TRUE;
3705 }
3706 else if(MOD_type==4)
3707 {
3708 *pQAMMode = DMD_DVBS_16APSK;
3709 modulation_order=4;
3710 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=DVBS2_16APSK\n");
3711 }
3712 else
3713 {
3714 *pQAMMode = DMD_DVBS_QPSK;
3715 modulation_order=2;
3716 ULOGD("DEMOD","INTERN_DVBS_GetCurrentModulationType [dvbs2]ModulationType=NOT SUPPORT\n");
3717 return FALSE;
3718 }
3719
3720 }
3721
3722 return status;
3723 /*#else
3724 *pQAMMode = DMD_DVBS_QPSK;
3725 printf("[dvbs]ModulationType=DVBS_QPSK\n");//DBG_INTERN_DVBS_LOCK(printf("[dvbs]ModulationType=DVBS_QPSK\n"));
3726 //return true;
3727 #endif*/
3728 }
3729
3730 /****************************************************************************
3731 Subject: To get the current DemodType at the DVB-S Demod
3732 Function: INTERN_DVBS_GetCurrentDemodType
3733 Parmeter: pointer for return DVBS/DVBS2 type
3734
3735 Return: TRUE
3736 FALSE
3737 Remark:
3738 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE * pDemodType)3739 MS_BOOL INTERN_DVBS_GetCurrentDemodType(DMD_DVBS_DEMOD_TYPE *pDemodType)//V
3740 {
3741 MS_U8 u8Data=0;
3742 MS_BOOL status = true;
3743
3744 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentDemodType\n"));
3745
3746 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);//status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x80, &u8Data);
3747 //printf(">>> INTERN_DVBS_GetCurrentDemodType INNER 0x40 = 0x%x <<<\n", u8Data);
3748 //if ((u8Data & 0x01) == 0)
3749 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);//E_DMD_S2_SYSTEM_TYPE 0: S2 ; 1 :S
3750 if(!u8Data) //S2
3751 {
3752 *pDemodType = DMD_SAT_DVBS2;
3753 DBG_INTERN_DVBS(ULOGD("DEMOD","[dvbs]DemodType=DVBS2\n"));
3754 }
3755 else //S
3756 {
3757 *pDemodType = DMD_SAT_DVBS;
3758 DBG_INTERN_DVBS(ULOGD("DEMOD","[dvbs]DemodType=DVBS\n"));
3759 }
3760 return status;
3761 }
3762 /****************************************************************************
3763 Subject: To get the current CodeRate at the DVB-S Demod
3764 Function: INTERN_DVBS_GetCurrentCodeRate
3765 Parmeter: pointer for return Code Rate type
3766
3767 Return: TRUE
3768 FALSE
3769 Remark:
3770 *****************************************************************************/
INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE * pCodeRate)3771 MS_BOOL INTERN_DVBS_GetCurrentDemodCodeRate(DMD_DVBS_CODE_RATE_TYPE *pCodeRate)
3772 {
3773 MS_U8 u8Data = 0;//, u8_gCodeRate = 0;
3774 MS_BOOL status = true;
3775
3776 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate\n"));
3777 //DMD_DVBS_DEMOD_TYPE pDemodType = 0;
3778 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SYSTEM_TYPE, &u8Data);
3779 //status &= INTERN_DVBS_GetCurrentDemodType(&pDemodType);
3780 if(!u8Data)
3781 //if((MS_U8)pDemodType == (MS_U8)DMD_SAT_DVBS2 ) //S2
3782 {
3783 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3784 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0xD7, &u8Data);
3785 //u8_gCodeRate = (u8Data & 0x3C);
3786 //_u8_DVBS2_CurrentCodeRate = 0;
3787 switch (u8Data)
3788 //switch (u8_gCodeRate)
3789 {
3790 case 0x03:
3791 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
3792 _u8_DVBS2_CurrentCodeRate = 5;//0;
3793 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_2\n"));
3794 break;
3795 case 0x01:
3796 *pCodeRate = DMD_CONV_CODE_RATE_1_3;
3797 _u8_DVBS2_CurrentCodeRate = 6;//1;
3798 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_3\n"));
3799 break;
3800 case 0x05:
3801 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
3802 _u8_DVBS2_CurrentCodeRate = 7;//2;
3803 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=2_3\n"));
3804 break;
3805 case 0x00:
3806 *pCodeRate = DMD_CONV_CODE_RATE_1_4;
3807 _u8_DVBS2_CurrentCodeRate = 8;//3;
3808 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=1_4\n"));
3809 break;
3810 case 0x06:
3811 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
3812 _u8_DVBS2_CurrentCodeRate = 9;//4;
3813 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=3_4\n"));
3814 break;
3815 case 0x02:
3816 *pCodeRate = DMD_CONV_CODE_RATE_2_5;
3817 _u8_DVBS2_CurrentCodeRate = 10;//5;
3818 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=2_5\n"));
3819 break;
3820 case 0x04:
3821 *pCodeRate = DMD_CONV_CODE_RATE_3_5;
3822 _u8_DVBS2_CurrentCodeRate = 11;//6;
3823 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=3_5\n"));
3824 break;
3825 case 0x07:
3826 *pCodeRate = DMD_CONV_CODE_RATE_4_5;
3827 _u8_DVBS2_CurrentCodeRate = 12;//7;
3828 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=4_5\n"));
3829 break;
3830 case 0x08:
3831 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
3832 _u8_DVBS2_CurrentCodeRate = 13;//8;
3833 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=5_6\n"));
3834 break;
3835 case 0x09:
3836 *pCodeRate = DMD_CONV_CODE_RATE_8_9;
3837 _u8_DVBS2_CurrentCodeRate = 14;//9;
3838 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=8_9\n"));
3839 break;
3840 case 0x0a:
3841 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3842 _u8_DVBS2_CurrentCodeRate = 15;//10;
3843 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=9_10\n"));
3844 break;
3845 default:
3846 *pCodeRate = DMD_CONV_CODE_RATE_9_10;
3847 _u8_DVBS2_CurrentCodeRate = 15;//10;
3848 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS2_GetCurrentCodeRate=DVBS2_Default\n"));
3849 }
3850 }
3851 else //S
3852 {
3853 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_CODE_RATE, &u8Data);
3854 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBSTFEC_REG_BASE + 0x3A*2, &u8Data);
3855 //u8_gCodeRate = (u8Data & 0x70)>>4;
3856 switch (u8Data)
3857 //switch (u8_gCodeRate)
3858 {
3859 case 0x00:
3860 *pCodeRate = DMD_CONV_CODE_RATE_1_2;
3861 _u8_DVBS2_CurrentCodeRate = 0;
3862 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=1_2\n"));
3863 break;
3864 case 0x01:
3865 *pCodeRate = DMD_CONV_CODE_RATE_2_3;
3866 _u8_DVBS2_CurrentCodeRate = 1;
3867 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=2_3\n"));
3868 break;
3869 case 0x02:
3870 *pCodeRate = DMD_CONV_CODE_RATE_3_4;
3871 _u8_DVBS2_CurrentCodeRate = 2;
3872 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=3_4\n"));
3873 break;
3874 case 0x03:
3875 *pCodeRate = DMD_CONV_CODE_RATE_5_6;
3876 _u8_DVBS2_CurrentCodeRate = 3;
3877 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=5_6\n"));
3878 break;
3879 case 0x04:
3880 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
3881 _u8_DVBS2_CurrentCodeRate = 4;
3882 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=7_8\n"));
3883 break;
3884 default:
3885 *pCodeRate = DMD_CONV_CODE_RATE_7_8;
3886 _u8_DVBS2_CurrentCodeRate = 4;
3887 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetCurrentCodeRate=DVBS_Default\n"));
3888 }
3889 }
3890 return status;
3891 }
3892
3893 /****************************************************************************
3894 Subject: To get the current symbol rate at the DVB-S Demod
3895 Function: INTERN_DVBS_GetCurrentSymbolRate
3896 Parmeter: pointer pData for return Symbolrate
3897
3898 Return: TRUE
3899 FALSE
3900 Remark:
3901 *****************************************************************************/
INTERN_DVBS_GetCurrentSymbolRate(MS_U32 * u32SymbolRate)3902 MS_BOOL INTERN_DVBS_GetCurrentSymbolRate(MS_U32 *u32SymbolRate)
3903 {
3904 MS_U8 tmp = 0;
3905 MS_U16 u16SymbolRateTmp = 0;
3906
3907 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_H, &tmp);
3908 u16SymbolRateTmp = tmp;
3909 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MANUAL_TUNE_SYMBOLRATE_L, &tmp);
3910 u16SymbolRateTmp = (u16SymbolRateTmp<<8)|tmp;
3911
3912 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_5, &tmp);
3913 *u32SymbolRate = (tmp<<16)|u16SymbolRateTmp;
3914
3915 DBG_INTERN_DVBS_LOCK(ULOGD("DEMOD","[dvbs]Symbol Rate=%d\n",*u32SymbolRate));
3916
3917 return TRUE;
3918 }
3919
INTERN_DVBS_Version(MS_U16 * ver)3920 MS_BOOL INTERN_DVBS_Version(MS_U16 *ver)
3921 {
3922 MS_U8 status = true;
3923 MS_U8 tmp = 0;
3924 MS_U16 u16_INTERN_DVBS_Version;
3925
3926 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_L, &tmp);
3927 u16_INTERN_DVBS_Version = tmp;
3928 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_FW_VERSION_H, &tmp);
3929 u16_INTERN_DVBS_Version = u16_INTERN_DVBS_Version<<8|tmp;
3930 *ver = u16_INTERN_DVBS_Version;
3931
3932 return status;
3933 }
3934
INTERN_DVBS_Show_Demod_Version(void)3935 MS_BOOL INTERN_DVBS_Show_Demod_Version(void)
3936 {
3937 MS_BOOL status = true;
3938 MS_U16 u16_INTERN_DVBS_Version;
3939
3940 status &= INTERN_DVBS_Version(&u16_INTERN_DVBS_Version);
3941
3942 ULOGD("DEMOD",">>> [Maserati]Demod FW Version: R%d.%d <<<\n", (u16_INTERN_DVBS_Version&0x00FF),((u16_INTERN_DVBS_Version>>8)&0x00FF));
3943
3944
3945 return status;
3946 }
3947
INTERN_DVBS_GetRollOff(MS_U8 * pRollOff)3948 MS_BOOL INTERN_DVBS_GetRollOff(MS_U8 *pRollOff)
3949 {
3950 MS_BOOL status=TRUE;
3951 MS_U8 u8Data=0;
3952
3953 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_INNER_REG_BASE + 0x1E, &u8Data);//#define INNER_TR_ROLLOFF (_REG_INNER(0x0F)+0)
3954 if ((u8Data&0x03)==0x00)
3955 *pRollOff = 0; //Rolloff 0.35
3956 else if (((u8Data&0x03)==0x01) || ((u8Data&0x03)==0x03))
3957 *pRollOff = 1; //Rolloff 0.25
3958 else
3959 *pRollOff = 2; //Rolloff 0.20
3960 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_GetRollOff:%d\n", *pRollOff));
3961
3962 return status;
3963 }
3964
INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 * u8_gSQValue)3965 MS_BOOL INTERN_DVBS_Get_DTV_SQuality_BAR(MS_U8 *u8_gSQValue)
3966 {
3967 MS_BOOL status=TRUE;
3968 //MS_U16 u16_gSignalQualityValue;
3969 MS_U16 _u16_packetError;
3970
3971 // status = INTERN_DVBS_GetSignalQuality(&u16_gSignalQualityValue,0,0,0);
3972 status = INTERN_DVBS_GetPacketErr(&_u16_packetError);
3973 /*
3974 if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 30)) //Average
3975 {
3976 *u8_gSQValue = 30;
3977 }
3978 else if ((_u16_packetError >= 1) && (u16_gSignalQualityValue > 10)) //Poor
3979 {
3980 *u8_gSQValue = 10;
3981 }
3982 */
3983 return status;
3984 }
3985
3986 /****************************************************************************
3987 ** Function: Read demod related information
3988 ** Polling after demod lock
3989 ** GAIN & DCR /Fine CFO & PR & IIS & IQB & SNR /PacketErr & BER
3990 ****************************************************************************/
INTERN_DVBS_Show_AGC_Info(void)3991 MS_BOOL INTERN_DVBS_Show_AGC_Info(void)
3992 {
3993 MS_BOOL status = TRUE;
3994
3995 //MS_U8 tmp = 0;
3996 //MS_U8 agc_k = 0,d0_k = 0,d0_ref = 0,d1_k = 0,d1_ref = 0,d2_k = 0,d2_ref = 0,d3_k = 0,d3_ref = 0;
3997 //MS_U16 if_agc_gain = 0,d0_gain = 0,d1_gain = 0,d2_gain = 0,d3_gain = 0, agc_ref = 0;
3998 //MS_U16 if_agc_err = 0;
3999 #if 0
4000 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x08*2 + 1,&agc_k);
4001 agc_k = ((agc_k & 0xF0)>>4);
4002 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x09*2 + 1,&tmp);
4003 agc_ref = tmp;
4004 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0xE8,&tmp);
4005 //agc_ref = (agc_ref<<8)|tmp;
4006 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2,&d0_k);
4007 d0_k = ((d0_k & 0xF0)>>4);
4008 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x38*2 + 1,&d0_ref);
4009 d0_ref = (d0_ref & 0xFF);
4010 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2,&d1_k);
4011 d1_k = (d1_k & 0xF0)>>4;
4012 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x58*2 + 1,&d1_ref);
4013 d1_ref = (d1_ref & 0xFF);
4014 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5E*2,&d2_k);
4015 d2_k = ((d2_k & 0xF0)>>4);
4016 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x5E*2 + 1,&d2_ref);
4017 d2_ref = (d2_ref & 0xFF);
4018 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6A*2,&d3_k);
4019 d3_k = ((d3_k & 0xF0)>>4);
4020 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6A*2 + 1,&d3_ref);
4021 d3_ref = (d3_ref & 0xFF);
4022
4023
4024 // select IF gain to read
4025 //Debug Select
4026 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4027 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x03);
4028 //IF_AGC_GAIN
4029 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4030 if_agc_gain = tmp;
4031 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4032 if_agc_gain = (if_agc_gain<<8)|tmp;
4033
4034
4035 // select d0 gain to read.
4036 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x74*2 + 1, &tmp);
4037 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x74*2 + 1, (tmp&0xF0)|0x03);
4038 //DAGC0_GAIN
4039 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3D*2, &tmp);
4040 d0_gain = tmp;
4041 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2 + 1, &tmp);
4042 d0_gain = (d0_gain<<8)|tmp;
4043 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x3C*2, &tmp);
4044 d0_gain = (d0_gain<<4)|(tmp>>4);
4045
4046
4047 // select d1 gain to read.
4048 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x8C, &tmp);
4049 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x8C, (tmp&0xF0)|0x00);
4050 //DAGC1_GAIN
4051 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2 + 1, &tmp);
4052 d1_gain = tmp;
4053 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x5C*2, &tmp);
4054 d1_gain = (d1_gain<<8)|tmp;
4055
4056
4057 // select d2 gain to read.
4058 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x06, &tmp);
4059 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT_REG_BASE + 0x06, (tmp&0xF0)|0x03);
4060 //DAGC2_GAIN
4061 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2 + 1, &tmp);
4062 d2_gain = tmp;
4063 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x62*2, &tmp);
4064 d2_gain = (d2_gain<<8)|tmp;
4065
4066
4067 // select d3 gain to read.
4068 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT2_REG_BASE + 0x6D*2, &tmp);
4069 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTENDEXT2_REG_BASE + 0x6D*2, (tmp&0xF0)|0x03);
4070 //DAGC3_GAIN
4071 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6F*2, &tmp);
4072 d3_gain = tmp;
4073 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2 + 1, &tmp);
4074 d3_gain = (d3_gain<<8)|tmp;
4075 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTENDEXT_REG_BASE + 0x6E*2, &tmp);
4076 d3_gain = (d3_gain<<4)|(tmp>>4);
4077
4078
4079 // select IF gain err to read
4080 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x13*2, &tmp);
4081 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(FRONTEND_REG_BASE + 0x13*2, (tmp&0xF0)|0x00);
4082
4083 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2 + 1, &tmp);
4084 if_agc_err = tmp;
4085 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(FRONTEND_REG_BASE + 0x14*2, &tmp);
4086 if_agc_err = (if_agc_err<<8)|tmp;
4087
4088
4089 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4090 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4091
4092 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4093
4094 DBG_INTERN_DVBS(printf("[dvbs]agc_k=0x%x, agc_ref=0x%x, d0_k=0x%x, d0_ref=0x%x, d1_k=0x%x, d1_ref=0x%x, d2_k=0x%x, d2_ref=0x%x, d3_k=0x%x, d3_ref=0x%x\n",
4095 agc_k, agc_ref, d0_k, d0_ref, d1_k, d1_ref, d2_k, d2_ref, d3_k, d3_ref));
4096
4097 DBG_INTERN_DVBS(printf("[dvbs]agc_g=0x%x, d0_g=0x%x, d1_g=0x%x, d2_g=0x%x, d3_g=0x%x, agc_err=0x%x\n", if_agc_gain, d0_gain, d1_gain, d2_gain, d3_gain, if_agc_err));
4098 #endif
4099 return status;
4100 }
4101
INTERN_DVBS_info(void)4102 void INTERN_DVBS_info(void)
4103 {
4104 //status &= INTERN_DVBS_Show_Demod_Version();
4105 //status &= INTERN_DVBS_Demod_Get_Debug_Info_get_once();
4106 //status &= INTERN_DVBS_Demod_Get_Debug_Info_polling();
4107 }
4108
INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)4109 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_get_once(void)
4110 {
4111 MS_BOOL status = TRUE;
4112 //MS_U8 u8Data = 0;
4113 //MS_U16 u16Data = 0, u16Address = 0;
4114 //float psd_smooth_factor;
4115 //float srd_right_bottom_value, srd_right_top_value, srd_left_bottom_value, srd_left_top_value;
4116 //MS_U16 u32temp5;
4117 //MS_U16 srd_left, srd_right, srd_left_top, srd_left_bottom, srd_right_top, srd_right_bottom;
4118
4119 #if 0
4120 //Lock Flag
4121 printf("========================================================================\n");
4122 printf("Debug Message Flag [Lock Flag]==========================================\n");
4123
4124 u16Address = (AGC_LOCK>>16)&0xffff;
4125 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4126 if ((u16Data&(AGC_LOCK&0xffff))!=(AGC_LOCK&0xffff))
4127 printf("[DVBS]: AGC LOCK ======================: Fail. \n");
4128 else
4129 printf("[DVBS]: AGC LOCK ======================: OK. \n");
4130
4131 u16Address = (DAGC0_LOCK>>16)&0xffff;
4132 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4133 if ((u16Data&(DAGC0_LOCK&0xffff))!=(DAGC0_LOCK&0xffff))
4134 printf("[DVBS]: DAGC0 LOCK ====================: Fail. \n");
4135 else
4136 printf("[DVBS]: DAGC0 LOCK ====================: OK. \n");
4137
4138 u16Address = (DAGC1_LOCK>>16)&0xffff;
4139 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4140 if ((u16Data&(DAGC1_LOCK&0xffff))!=(DAGC1_LOCK&0xffff))
4141 printf("[DVBS]: DAGC1 LOCK ====================: Fail. \n");
4142 else
4143 printf("[DVBS]: DAGC1 LOCK ====================: OK. \n");
4144
4145 u16Address = (DAGC2_LOCK>>16)&0xffff;
4146 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4147 if ((u16Data&(DAGC2_LOCK&0xffff))!=(DAGC2_LOCK&0xffff))
4148 printf("[DVBS]: DAGC2 LOCK ====================: Fail. \n");
4149 else
4150 printf("[DVBS]: DAGC2 LOCK ====================: OK. \n");
4151
4152 u16Address = (DAGC3_LOCK>>16)&0xffff;
4153 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4154 if ((u16Data&(DAGC3_LOCK&0xffff))!=(DAGC3_LOCK&0xffff))
4155 printf("[DVBS]: DAGC3 LOCK ====================: Fail. \n");
4156 else
4157 printf("[DVBS]: DAGC3 LOCK ====================: OK. \n");
4158
4159 u16Address = (DCR_LOCK>>16)&0xffff;
4160 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4161 if ((u16Data&(DCR_LOCK&0xffff))!=(DCR_LOCK&0xffff))
4162 printf("[DVBS]: DCR LOCK ======================: Fail. \n");
4163 else
4164 printf("[DVBS]: DCR LOCK ======================: OK. \n");
4165 //Mark Coarse SRD
4166 //Mark Fine SRD
4167 /*
4168 u16Address = (CLOSE_COARSE_CFO_LOCK>>16)&0xffff;
4169 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4170 if ((u16Data&(CLOSE_COARSE_CFO_LOCK&0xffff))!=(CLOSE_COARSE_CFO_LOCK&0xffff))
4171 printf("[DVBS]: Close CFO =====================: Fail. \n");
4172 else
4173 printf("[DVBS]: Close CFO =====================: OK. \n");
4174 */
4175 u16Address = (TR_LOCK>>16)&0xffff;
4176 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4177 if ((u16Data&(TR_LOCK&0xffff))!=(TR_LOCK&0xffff))
4178 printf("[DVBS]: TR LOCK =======================: Fail. \n");
4179 else
4180 printf("[DVBS]: TR LOCK =======================: OK. \n");
4181
4182 u16Address = (FRAME_SYNC_ACQUIRE>>16)&0xffff;
4183 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4184 if ((u16Data&(FRAME_SYNC_ACQUIRE&0xffff))!=(FRAME_SYNC_ACQUIRE&0xffff))
4185 printf("[DVBS]: FS Acquire ====================: Fail. \n");
4186 else
4187 printf("[DVBS]: FS Acquire ====================: OK. \n");
4188
4189 u16Address = (PR_LOCK>>16)&0xffff;
4190 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4191 if ((u16Data&(PR_LOCK&0xffff))!=(PR_LOCK&0xffff))
4192 printf("[DVBS]: PR LOCK =======================: Fail. \n");
4193 else
4194 printf("[DVBS]: PR LOCK =======================: OK. \n");
4195
4196 u16Address = (EQ_LOCK>>16)&0xffff;
4197 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4198 if ((u16Data&(EQ_LOCK&0xffff))!=(EQ_LOCK&0xffff))
4199 printf("[DVBS]: EQ LOCK =======================: Fail. \n");
4200 else
4201 printf("[DVBS]: EQ LOCK =======================: OK. \n");
4202
4203 u16Address = (P_SYNC_LOCK>>16)&0xffff;
4204 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4205 if ((u16Data&0x0002)!=0x0002)
4206 printf("[DVBS]: P_sync ========================: Fail. \n");
4207 else
4208 printf("[DVBS]: P_sync ========================: OK. \n");
4209
4210 u16Address = (IN_SYNC_LOCK>>16)&0xffff;
4211 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4212 if ((u16Data&0x8000)!=0x8000)
4213 printf("[DVBS]: In_sync =======================: Fail. \n");
4214 else
4215 printf("[DVBS]: In_sync =======================: OK. \n");
4216 //---------------------------------------------------------
4217 //Lock Time
4218 printf("------------------------------------------------------------------------\n");
4219 printf("Debug Message [Lock Time]===============================================\n");
4220
4221 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_05, &u8Data);
4222 printf("[DVBS]: AGC Lock Time =================: %d\n",u8Data&0x00FF);
4223 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_06, &u8Data);
4224 printf("[DVBS]: DCR Lock Time =================: %d\n",u8Data&0x00FF);
4225 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_2, &u8Data);
4226 printf("[DVBS]: TR Lock Time ==================: %d\n",u8Data&0x00FF);
4227 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_3, &u8Data);
4228 printf("[DVBS]: FS Lock Time ==================: %d\n",u8Data&0x00FF);
4229 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_4, &u8Data);
4230 printf("[DVBS]: PR Lock Time ==================: %d\n",u8Data&0x00FF);
4231 //printf("[DVBS]: PLSC Lock Time ================: %d\n",(u16Data>>8)&0x00FF);//No used
4232 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_6, &u8Data);
4233 printf("[DVBS]: EQ Lock Time ==================: %d\n",u8Data&0x00FF);
4234 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_7, &u8Data);
4235 printf("[DVBS]: FEC Lock Time =================: %d\n",u8Data&0x00FF);
4236
4237 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_0, &u8Data);
4238 printf("[DVBS]: CSRD ==========================: %d\n",u8Data&0x00FF);
4239 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_1, &u8Data);
4240 printf("[DVBS]: FSRD ==========================: %d\n",u8Data&0x00FF);
4241 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_01, &u8Data);
4242 printf("[DVBS]: CCFO ==========================: %d\n",u8Data&0x00FF);
4243 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_INFO_02, &u8Data);
4244 printf("[DVBS]: FCFO ==========================: %d\n",u8Data&0x00FF);
4245 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);
4246 printf("[DVBS]: State =========================: %d\n",u8Data&0x00FF);
4247 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);
4248 printf("[DVBS]: SubState ======================: %d\n",u8Data&0x00FF);
4249
4250 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4251 u16Data = u8Data;
4252 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4253 u16Data = (u16Data<<8)|u8Data;
4254 printf("[DVBS]: DBG1: =========================: 0x%x\n",u16Data);
4255 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4256 u16Data = u8Data;
4257 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4258 u16Data = (u16Data<<8)|u8Data;
4259 printf("[DVBS]: DBG2: =========================: 0x%x\n",u16Data);
4260 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02H, &u8Data);
4261 u16Data = u8Data;
4262 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE02L, &u8Data);
4263 u16Data = (u16Data<<8)|u8Data;
4264 printf("[DVBS]: DBG3: =========================: 0x%x\n",u16Data);
4265 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03H, &u8Data);
4266 u16Data = u8Data;
4267 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE03L, &u8Data);
4268 u16Data = (u16Data<<8)|u8Data;
4269 printf("[DVBS]: DBG4: =========================: 0x%x\n",u16Data);
4270 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04H, &u8Data);
4271 u16Data = u8Data;
4272 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE04L, &u8Data);
4273 u16Data = (u16Data<<8)|u8Data;
4274 printf("[DVBS]: DBG5: =========================: 0x%x\n",u16Data);
4275 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05H, &u8Data);
4276 u16Data = u8Data;
4277 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE05L, &u8Data);
4278 u16Data = (u16Data<<8)|u8Data;
4279 printf("[DVBS]: DBG6: =========================: 0x%x\n",u16Data);
4280 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06H, &u8Data);
4281 u16Data = u8Data;
4282 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE06L, &u8Data);
4283 u16Data = (u16Data<<8)|u8Data;
4284 printf("[DVBS]: EQ Sum: =======================: 0x%x\n",u16Data);
4285 //---------------------------------------------------------
4286 //FIQ Status
4287 printf("------------------------------------------------------------------------\n");
4288 printf("Debug Message [FIQ Status]==============================================\n");
4289 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00H, &u8Data);
4290 u16Data = u8Data;
4291 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE00L, &u8Data);
4292 u16Data = (u16Data<<8)|u8Data;
4293
4294 if ((u16Data&0x0001)==0x0000)
4295 printf("[DVBS]: AGC Lock ======================: Fail. \n");
4296 else
4297 printf("[DVBS]: AGC Lock ======================: OK. \n");
4298
4299 if ((u16Data&0x0002)==0x0000)
4300 printf("[DVBS]: Hum Detect ====================: Fail. \n");
4301 else
4302 printf("[DVBS]: Hum Detect ====================: OK. \n");
4303
4304 if ((u16Data&0x0004)==0x0000)
4305 printf("[DVBS]: DCR Lock ======================: Fail. \n");
4306 else
4307 printf("[DVBS]: DCR Lock ======================: OK. \n");
4308
4309 if ((u16Data&0x0008)==0x0000)
4310 printf("[DVBS]: IIS Detect ====================: Fail. \n");
4311 else
4312 printf("[DVBS]: IIS Detect ====================: OK. \n");
4313
4314 if ((u16Data&0x0010)==0x0000)
4315 printf("[DVBS]: DAGC0 Lock ====================: Fail. \n");
4316 else
4317 printf("[DVBS]: DAGC0 Lock ====================: OK. \n");
4318
4319 if ((u16Data&0x0020)==0x0000)
4320 printf("[DVBS]: DAGC1 Lock ====================: Fail. \n");
4321 else
4322 printf("[DVBS]: DAGC1 Lock ====================: OK. \n");
4323
4324 if ((u16Data&0x0040)==0x0000)
4325 printf("[DVBS]: DAGC2 Lock ====================: Fail. \n");
4326 else
4327 printf("[DVBS]: DAGC2 Lock ====================: OK. \n");
4328
4329 if ((u16Data&0x0080)==0x0000)
4330 printf("[DVBS]: CCI Detect ====================: Fail. \n");
4331 else
4332 printf("[DVBS]: CCI Detect ====================: OK. \n");
4333
4334 if ((u16Data&0x0100)==0x0000)
4335 printf("[DVBS]: SRD Coarse Done ===============: Fail. \n");
4336 else
4337 printf("[DVBS]: SRD Coarse Done ===============: OK. \n");
4338
4339 if ((u16Data&0x0200)==0x0000)
4340 printf("[DVBS]: SRD Fine Done =================: Fail. \n");
4341 else
4342 printf("[DVBS]: SRD Fine Done =================: OK. \n");
4343
4344 if ((u16Data&0x0400)==0x0000)
4345 printf("[DVBS]: EQ Lock =======================: Fail. \n");
4346 else
4347 printf("[DVBS]: EQ Lock =======================: OK. \n");
4348
4349 if ((u16Data&0x0800)==0x0000)
4350 printf("[DVBS]: FineFE Done ===================: Fail. \n");
4351 else
4352 printf("[DVBS]: FineFE Done ===================: OK. \n");
4353
4354 if ((u16Data&0x1000)==0x0000)
4355 printf("[DVBS]: PR Lock =======================: Fail. \n");
4356 else
4357 printf("[DVBS]: PR Lock =======================: OK. \n");
4358
4359 if ((u16Data&0x2000)==0x0000)
4360 printf("[DVBS]: Reserved Frame ================: Fail. \n");
4361 else
4362 printf("[DVBS]: Reserved Frame ================: OK. \n");
4363
4364 if ((u16Data&0x4000)==0x0000)
4365 printf("[DVBS]: Dummy Frame ===================: Fail. \n");
4366 else
4367 printf("[DVBS]: Dummy Frame ===================: OK. \n");
4368
4369 if ((u16Data&0x8000)==0x0000)
4370 printf("[DVBS]: PLSC Done =====================: Fail. \n");
4371 else
4372 printf("[DVBS]: PLSC Done =====================: OK. \n");
4373
4374 printf("------------------------------------------------------------------------\n");
4375 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01H, &u8Data);
4376 u16Data = u8Data;
4377 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_SWUSE01L, &u8Data);
4378 u16Data = (u16Data<<8)|u8Data;
4379 if ((u16Data&0x0001)==0x0000)
4380 printf("[DVBS]: FS Get Info From Len ==========: Fail. \n");
4381 else
4382 printf("[DVBS]: FS Get Info From Len ==========: OK. \n");
4383
4384 if ((u16Data&0x0002)==0x0000)
4385 printf("[DVBS]: IQ Swap Detect ================: Fail. \n");
4386 else
4387 printf("[DVBS]: IQ Swap Detect ================: OK. \n");
4388
4389 if ((u16Data&0x0004)==0x0000)
4390 printf("[DVBS]: FS Acquisition ================: Fail. \n");
4391 else
4392 printf("[DVBS]: FS Acquisition ================: OK. \n");
4393
4394 if ((u16Data&0x0008)==0x0000)
4395 printf("[DVBS]: TR Lock =======================: Fail. \n");
4396 else
4397 printf("[DVBS]: TR Lock =======================: OK. \n");
4398
4399 if ((u16Data&0x0010)==0x0000)
4400 printf("[DVBS]: CLCFE Lock ====================: Fail. \n");
4401 else
4402 printf("[DVBS]: CLCFE Lock ====================: OK. \n");
4403
4404 if ((u16Data&0x0020)==0x0000)
4405 printf("[DVBS]: OLCFE Lock ====================: Fail. \n");
4406 else
4407 printf("[DVBS]: OLCFE Lock ====================: OK. \n");
4408
4409 if ((u16Data&0x0040)==0x0000)
4410 printf("[DVBS]: Fsync Found ===================: Fail. \n");
4411 else
4412 printf("[DVBS]: Fsync Found ===================: OK. \n");
4413
4414 if ((u16Data&0x0080)==0x0000)
4415 printf("[DVBS]: Fsync Lock ====================: Fail. \n");
4416 else
4417 printf("[DVBS]: Fsync Lock ====================: OK. \n");
4418
4419 if ((u16Data&0x0100)==0x0000)
4420 printf("[DVBS]: Fsync Fail Search =============: Fail. \n");
4421 else
4422 printf("[DVBS]: Fsync Fail Search =============: OK. \n");
4423
4424 if ((u16Data&0x0200)==0x0000)
4425 printf("[DVBS]: Fsync Fail Lock ===============: Fail. \n");
4426 else
4427 printf("[DVBS]: Fsync Fail Lock ===============: OK. \n");
4428
4429 if ((u16Data&0x0400)==0x0000)
4430 printf("[DVBS]: False Alarm ===================: Fail. \n");
4431 else
4432 printf("[DVBS]: False Alarm ===================: OK. \n");
4433
4434 if ((u16Data&0x0800)==0x0000)
4435 printf("[DVBS]: Viterbi In Sync ===============: Fail. \n");
4436 else
4437 printf("[DVBS]: Viterbi In Sync ===============: OK. \n");
4438
4439 if ((u16Data&0x1000)==0x0000)
4440 printf("[DVBS]: Uncrt Over ====================: Fail. \n");
4441 else
4442 printf("[DVBS]: Uncrt Over ====================: OK. \n");
4443
4444 if ((u16Data&0x2000)==0x0000)
4445 printf("[DVBS]: CLK Cnt Over ==================: Fail. \n");
4446 else
4447 printf("[DVBS]: CLK Cnt Over ==================: OK. \n");
4448
4449 //if ((u16Data&0x4000)==0x0000)
4450 // printf("[DVBS]: Data In Ready FIFO ============: Fail. \n");
4451 //else
4452 // printf("[DVBS]: Data In Ready FIFO ============: OK. \n");
4453
4454 //if ((u16Data&0x8000)==0x0000)
4455 // printf("[DVBS]: IIR Buff Busy =================: Fail. \n");
4456 //else
4457 // printf("[DVBS]: IIR Buff Busy =================: OK. \n");
4458
4459 /*
4460 printf("------------------------------------------------------------------------\n");
4461 u16Address = 0x0B64;
4462 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address+1, &u8Data);
4463 u16Data = u8Data;
4464 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Address , &u8Data);
4465 u16Data = (u16Data<<8)|u8Data;
4466 if ((u16Data&0x0001)==0x0000)
4467 printf("[DVBS]: IIR Busy LDPC =================: Fail. \n");
4468 else
4469 printf("[DVBS]: IIR Busy LDPC =================: OK. \n");
4470
4471 if ((u16Data&0x0002)==0x0000)
4472 printf("[DVBS]: BCH Busy ======================: Fail. \n");
4473 else
4474 printf("[DVBS]: BCH Busy ======================: OK. \n");
4475
4476 if ((u16Data&0x0004)==0x0000)
4477 printf("[DVBS]: Oppro Ready Out ===============: Fail. \n");
4478 else
4479 printf("[DVBS]: Oppro Ready Out ===============: OK. \n");
4480
4481 if ((u16Data&0x0008)==0x0000)
4482 printf("[DVBS]: LDPC Win ======================: Fail. \n");
4483 else
4484 printf("[DVBS]: LDPC Win ======================: OK. \n");
4485
4486 if ((u16Data&0x0010)==0x0000)
4487 printf("[DVBS]: LDPC Error ====================: Fail. \n");
4488 else
4489 printf("[DVBS]: LDPC Error ====================: OK. \n");
4490
4491 if ((u16Data&0x0020)==0x0000)
4492 printf("[DVBS]: Out BCH Error =================: Fail. \n");
4493 else
4494 printf("[DVBS]: Out BCH Error =================: OK. \n");
4495
4496 if ((u16Data&0x0040)==0x0000)
4497 printf("[DVBS]: Descr BCH FEC Num Error =======: Fail. \n");
4498 else
4499 printf("[DVBS]: Descr BCH FEC Num Error =======: OK. \n");
4500
4501 if ((u16Data&0x0080)==0x0000)
4502 printf("[DVBS]: Descr BCH Data Num Error ======: Fail. \n");
4503 else
4504 printf("[DVBS]: Descr BCH Data Num Error ======: OK. \n");
4505
4506 if ((u16Data&0x0100)==0x0000)
4507 printf("[DVBS]: Packet Error Out ==============: Fail. \n");
4508 else
4509 printf("[DVBS]: Packet Error Out ==============: OK. \n");
4510
4511 if ((u16Data&0x0200)==0x0000)
4512 printf("[DVBS]: BBH CRC Error =================: Fail. \n");
4513 else
4514 printf("[DVBS]: BBH CRC Error =================: OK. \n");
4515
4516 if ((u16Data&0x0400)==0x0000)
4517 printf("[DVBS]: BBH Decode Done ===============: Fail. \n");
4518 else
4519 printf("[DVBS]: BBH Decode Done ===============: OK. \n");
4520
4521 if ((u16Data&0x0800)==0x0000)
4522 printf("[DVBS]: ISRC Calculate Done ===========: Fail. \n");
4523 else
4524 printf("[DVBS]: ISRC Calculate Done ===========: OK. \n");
4525
4526 if ((u16Data&0x1000)==0x0000)
4527 printf("[DVBS]: Syncd Check Error =============: Fail. \n");
4528 else
4529 printf("[DVBS]: Syncd Check Error =============: OK. \n");
4530
4531 //if ((u16Data&0x2000)==0x0000)
4532 // printf("[DVBS]: Syncd Check Error======: Fail. \n");
4533 //else
4534 // printf("[DVBS]: Syncd Check Error======: OK. \n");
4535
4536 if ((u16Data&0x4000)==0x0000)
4537 printf("[DVBS]: Demap Init ====================: Fail. \n");
4538 else
4539 printf("[DVBS]: Demap Init ====================: OK. \n");
4540 */
4541 //Spectrum Information
4542 printf("------------------------------------------------------------------------\n");
4543
4544 u16Address = 0x2836;
4545 status &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4546 psd_smooth_factor=(u16Data>>8)&0x7F;
4547
4548 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
4549 u16Data = u8Data;
4550 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
4551 u16Data = (u16Data<<8)|u8Data;
4552 u32temp5=u16Data;
4553 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
4554 u16Data = u8Data;
4555 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
4556 u16Data = (u16Data<<8)|u8Data;
4557 u32temp5|=(u16Data<<16);
4558 if (psd_smooth_factor!=0)
4559 srd_left_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4560 else
4561 srd_left_top_value=0;
4562
4563 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4564 u16Data = u8Data;
4565 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4566 u16Data = (u16Data<<8)|u8Data;
4567 u32temp5=u16Data;
4568 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
4569 u16Data = u8Data;
4570 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
4571 u16Data = (u16Data<<8)|u8Data;
4572 u32temp5|=(u16Data<<16);
4573 if (psd_smooth_factor!=0)
4574 srd_left_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4575 else
4576 srd_left_bottom_value=0;
4577
4578 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
4579 u16Data = u8Data;
4580 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
4581 u16Data = (u16Data<<8)|u8Data;
4582 u32temp5=u16Data;
4583 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17H, &u8Data);
4584 u16Data = u8Data;
4585 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE17L, &u8Data);
4586 u16Data = (u16Data<<8)|u8Data;
4587 u32temp5|=(u16Data<<16);
4588 if (psd_smooth_factor!=0)
4589 srd_right_top_value=(float)u32temp5/256.0/psd_smooth_factor;
4590 else
4591 srd_right_top_value=0;
4592
4593 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
4594 u16Data = u8Data;
4595 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
4596 u16Data = (u16Data<<8)|u8Data;
4597 u32temp5=u16Data;
4598 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
4599 u16Data = u8Data;
4600 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
4601 u16Data = (u16Data<<8)|u8Data;
4602 u32temp5|=(u16Data<<16);
4603 if (psd_smooth_factor!=0)
4604 srd_right_bottom_value=(float)u32temp5/256.0/psd_smooth_factor;
4605 else
4606 srd_right_bottom_value=0;
4607
4608 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AH, &u8Data);
4609 u16Data = u8Data;
4610 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1AL, &u8Data);
4611 u16Data = (u16Data<<8)|u8Data;
4612 srd_left=u16Data;
4613 printf("[DVBS]: FFT Left ======================: %d, %f\n", srd_left, srd_left_top_value - srd_left_bottom_value);
4614 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BH, &u8Data);
4615 u16Data = u8Data;
4616 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1BL, &u8Data);
4617 u16Data = (u16Data<<8)|u8Data;
4618 srd_right=u16Data;
4619 printf("[DVBS]: FFT Right =====================: %d, %f\n", srd_right, srd_right_top_value - srd_right_bottom_value);
4620 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CH, &u8Data);
4621 u16Data = u8Data;
4622 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1CL, &u8Data);
4623 u16Data = (u16Data<<8)|u8Data;
4624 srd_left_top=u16Data;
4625 printf("[DVBS]: FFT Left Top ==================: %d, %f\n", srd_left_top, srd_left_top_value);
4626 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DH, &u8Data);
4627 u16Data = u8Data;
4628 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1DL, &u8Data);
4629 u16Data = (u16Data<<8)|u8Data;
4630 srd_left_bottom=u16Data;
4631 printf("[DVBS]: FFT Left Bottom ===============: %d, %f\n", srd_left_bottom, srd_left_bottom_value);
4632 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EH, &u8Data);
4633 u16Data = u8Data;
4634 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1EL, &u8Data);
4635 u16Data = (u16Data<<8)|u8Data;
4636 srd_right_top=u16Data;
4637 printf("[DVBS]: FFT Right Top =================: %d, %f\n", srd_right_top, srd_right_top_value);
4638 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FH, &u8Data);
4639 u16Data = u8Data;
4640 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE1FL, &u8Data);
4641 u16Data = (u16Data<<8)|u8Data;
4642 srd_right_bottom=u16Data;
4643 printf("[DVBS]: FFT Right Bottom ==============: %d, %f\n", srd_right_bottom, srd_right_bottom_value);
4644
4645 printf("-----------------------------------------\n");
4646 printf("[DVBS]: Left-Bottom ===================: %d\n", srd_left-srd_left_bottom);
4647 printf("[DVBS]: Left-Top ======================: %d\n", srd_left_top - srd_left);
4648 printf("[DVBS]: Right-Top =====================: %d\n", srd_right - srd_right_top);
4649 printf("[DVBS]: Right-Bottom ==================: %d\n", srd_right_bottom - srd_right);
4650
4651 if (psd_smooth_factor!=0)
4652 {
4653 if ((srd_left_top-srd_left_bottom)!=0)
4654 printf("[DVBS]: Left Slope ====================: %f\n", (srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom));
4655 else
4656 printf("[DVBS]: Left Slope ====================: %f\n", 0.000000);
4657
4658 if((srd_right_bottom - srd_right_top)!=0)
4659 printf("[DVBS]: Right Slope ===================: %f\n", (srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top));
4660 else
4661 printf("[DVBS]: Right Slope ===================: %f\n", 0.000000);
4662
4663 if (((srd_right_top_value - srd_right_bottom_value)!=0)&&((srd_right_bottom - srd_right_top))!=0)
4664 printf("[DVBS]: Slope Ratio ===================: %f\n", ((srd_left_top_value - srd_left_bottom_value)/(srd_left_top-srd_left_bottom))/((srd_right_top_value - srd_right_bottom_value)/(srd_right_bottom - srd_right_top)));
4665 else
4666 printf("[DVBS]: Slope Ratio ===================: %f\n", 0.000000);
4667 }
4668 else
4669 {
4670 printf("[DVBS]: Left Slope ======================: %d\n", 0);
4671 printf("[DVBS]: Right Slope =====================: %d\n", 0);
4672 printf("[DVBS]: Slope Ratio =====================: %d\n", 0);
4673 }
4674 #endif
4675 return status;
4676 }
4677
INTERN_DVBS_Demod_Get_Debug_Info_polling(void)4678 MS_BOOL INTERN_DVBS_Demod_Get_Debug_Info_polling(void)
4679 {
4680 MS_BOOL bRet = FALSE;
4681 #if 0
4682 MS_U8 u8Data = 0;
4683 MS_U16 u16Data = 0;
4684 MS_U16 u16Address = 0;
4685 MS_U32 u32DebugInfo_Fb = 0; //Fb, SymbolRate
4686 MS_U32 u32DebugInfo_Fs = 96000; //Fs, 96000k
4687 float AGC_IF_Gain;
4688 float DAGC0_Gain, DAGC1_Gain, DAGC2_Gain, DAGC3_Gain, DAGC0_Peak_Mean, DAGC1_Peak_Mean, DAGC2_Peak_Mean, DAGC3_Peak_Mean;
4689 short AGC_Err, DAGC0_Err, DAGC1_Err, DAGC2_Err, DAGC3_Err;
4690 float DCR_Offset_I, DCR_Offset_Q;
4691 float FineCFO_loop_input_value, FineCFO_loop_out_value;
4692 double FineCFO_loop_ki_value, TR_loop_ki;
4693 float PR_in_value, PR_out_value, PR_loop_ki, PR_loopback_ki;
4694 float IQB_Phase, IQB_Gain;
4695 MS_U16 IIS_cnt, ConvegenceLen;
4696 float Linear_SNR_dd, SNR_dd_dB, Linear_SNR_da, SNR_da_dB, SNR_nda_dB, Linear_SNR;
4697 float Packet_Err, BER;
4698 float TR_Indicator_ff, TR_SFO_Converge, Fs_value, Fb_value;
4699 float TR_Loop_Output, TR_Loop_Ki, TR_loop_input, TR_tmp0, TR_tmp1, TR_tmp2;
4700 float Eq_variance_da, Eq_variance_dd;
4701 float ndasnr_ratio, ndasnr_a, ndasnr_ab;
4702 MS_U16 BitErr, BitErrPeriod;
4703 MS_BOOL BEROver;
4704
4705 //Fb
4706 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
4707 //bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
4708 if((u8Data&0x02)==0x00) //Manual Tune
4709 {
4710 u32DebugInfo_Fb = 0x0;//_u32CurrentSR;
4711 }
4712 else //Blind Scan
4713 {
4714 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
4715 u16Data = u8Data;
4716 bRet &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
4717 u16Data = (u16Data<<8)|u8Data;
4718 u32DebugInfo_Fb = u16Data;
4719 }
4720 printf("++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++\n");
4721 printf("Fs ====================================: %lu [kHz]\n",u32DebugInfo_Fs);
4722 printf("Fb ====================================: %lu [kHz]\n",u32DebugInfo_Fb);
4723 //---------------------------------------------------------
4724 //Page1-GAIN & DCR
4725 //---------------------------------------------------------
4726 //GAIN
4727 printf("\n");
4728 printf("========================================================================\n");
4729 printf("Debug Message [GAIN & DCR]==============================================\n");
4730
4731 //Debug select
4732 u16Address = (DEBUG_SEL_IF_AGC_GAIN>>16)&0xffff;
4733 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4734 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_IF_AGC_GAIN)&0xffff);
4735 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4736
4737 //Freeze and dump
4738 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4739 //AGC_IF_GAIN
4740 u16Address = (DEBUG_OUT_AGC)&0xffff;
4741 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4742 AGC_IF_Gain=u16Data;
4743 //Unfreeze
4744 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4745
4746 AGC_IF_Gain=AGC_IF_Gain/0x8000; //(16, 15)
4747 printf("[DVBS]: AGC_IF_Gain ===================: %f\n", AGC_IF_Gain);
4748 //---------------------------------------------------------
4749 //Debug select
4750 u16Address = (DEBUG_SEL_DAGC0_GAIN>>16)&0xffff;
4751 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4752 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_GAIN)&0xffff);
4753 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4754
4755 //Freeze and dump
4756 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4757 //DAGC0_GAIN
4758 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4759 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4760 u16Data = (u16Data>>4);
4761 DAGC0_Gain=(u16Data&0x0fff);
4762 //Unfreeze
4763 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4764 //---------------------------------------------------------
4765 //Debug select
4766 u16Address = (DEBUG_SEL_DAGC1_GAIN>>16)&0xffff;
4767 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4768 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_GAIN)&0xffff);
4769 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4770
4771 //Freeze and dump
4772 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4773 //DAGC1_GAIN
4774 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4775 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4776 DAGC1_Gain=(u16Data&0x07ff);
4777 //Unfreeze
4778 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4779 //---------------------------------------------------------
4780 //Debug select
4781 u16Address = (DEBUG_SEL_DAGC2_GAIN>>16)&0xffff;
4782 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4783 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_GAIN)&0xffff);
4784 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4785
4786 //Freeze and dump
4787 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4788 //DAGC2_GAIN
4789 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
4790 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4791 DAGC2_Gain=(u16Data&0x0fff);
4792 //Unfreeze
4793 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4794 //---------------------------------------------------------
4795 //Debug select
4796 u16Address = (DEBUG_SEL_DAGC3_GAIN>>16)&0xffff;
4797 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4798 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_GAIN)&0xffff);
4799 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4800
4801 //Freeze and dump
4802 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4803 //DAGC3_GAIN
4804 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
4805 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4806 u16Data = (u16Data>>4);
4807 DAGC3_Gain=(u16Data&0x0fff);
4808 //Unfreeze
4809 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4810 //---------------------------------------------------------
4811
4812 DAGC0_Gain=DAGC0_Gain/0x200; //<12,9>
4813 DAGC1_Gain=DAGC1_Gain/0x200; //<11,9>
4814 DAGC2_Gain=DAGC2_Gain/0x200; //<12,9>
4815 DAGC3_Gain=DAGC3_Gain/0x200; //<12,9>
4816 printf("[DVBS]: DAGC0_Gain ====================: %f\n", DAGC0_Gain);
4817 printf("[DVBS]: DAGC1_Gain ====================: %f\n", DAGC1_Gain);
4818 printf("[DVBS]: DAGC2_Gain ====================: %f\n", DAGC2_Gain);
4819 printf("[DVBS]: DAGC3_Gain ====================: %f\n", DAGC3_Gain);
4820
4821 //---------------------------------------------------------
4822 //ERROR
4823 //Debug select
4824 u16Address = (DEBUG_SEL_AGC_ERR>>16)&0xffff;
4825 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4826 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_AGC_ERR)&0xffff);
4827 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4828
4829 //Freeze and dump
4830 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4831 //AGC_ERR
4832 u16Address = (DEBUG_OUT_AGC)&0xffff;
4833 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4834 AGC_Err=(u16Data&0x03ff);
4835 //Unfreeze
4836 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4837
4838 //Debug select
4839 u16Address = (DEBUG_SEL_DAGC0_ERR>>16)&0xffff;
4840 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4841 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_ERR)&0xffff);
4842 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4843
4844 //Freeze and dump
4845 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4846 //DAGC0_ERR
4847 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4848 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4849 u16Data = (u16Data>>4);
4850 DAGC0_Err=(u16Data&0x7fff);
4851 //Unfreeze
4852 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4853
4854 //Debug select
4855 u16Address = (DEBUG_SEL_DAGC1_ERR>>16)&0xffff;
4856 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4857 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_ERR)&0xffff);
4858 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4859
4860 //Freeze and dump
4861 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4862 //DAGC1_ERR
4863 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4864 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4865 DAGC1_Err=(u16Data&0x7fff);
4866 //Unfreeze
4867 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4868
4869 //Debug select
4870 u16Address = (DEBUG_SEL_DAGC2_ERR>>16)&0xffff;
4871 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4872 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_ERR)&0xffff);
4873 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4874
4875 //Freeze and dump
4876 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4877 //DAGC2_ERR
4878 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
4879 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4880 DAGC2_Err=(u16Data&0x7fff);
4881 //Unfreeze
4882 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4883
4884 //Debug select
4885 u16Address = (DEBUG_SEL_DAGC3_ERR>>16)&0xffff;
4886 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4887 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_ERR)&0xffff);
4888 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4889
4890 //Freeze and dump
4891 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4892 //DAGC3_ERR
4893 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
4894 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4895 u16Data = (u16Data>>4);
4896 DAGC3_Err=(u16Data&0x7fff);
4897 //Unfreeze
4898 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4899
4900 if (AGC_Err>=0x200)
4901 AGC_Err=AGC_Err-0x400;
4902 if (DAGC0_Err>=0x4000)
4903 DAGC0_Err=DAGC0_Err-0x8000;
4904 if (DAGC1_Err>=0x4000)
4905 DAGC1_Err=DAGC1_Err-0x8000;
4906 if (DAGC2_Err>=0x4000)
4907 DAGC2_Err=DAGC2_Err-0x8000;
4908 if (DAGC3_Err>=0x4000)
4909 DAGC3_Err=DAGC3_Err-0x8000;
4910
4911 printf("[DVBS]: AGC_Err =========================: %.3f\n", (float)AGC_Err);
4912 printf("[DVBS]: DAGC0_Err =======================: %.3f\n", (float)DAGC0_Err);
4913 printf("[DVBS]: DAGC1_Err =======================: %.3f\n", (float)DAGC1_Err);
4914 printf("[DVBS]: DAGC2_Err =======================: %.3f\n", (float)DAGC2_Err);
4915 printf("[DVBS]: DAGC3_Err =======================: %.3f\n", (float)DAGC3_Err);
4916 //---------------------------------------------------------
4917 //PEAK_MEAN
4918 //Debug select
4919 u16Address = (DEBUG_SEL_DAGC0_PEAK_MEAN>>16)&0xffff;
4920 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4921 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC0_PEAK_MEAN)&0xffff);
4922 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4923
4924 //Freeze and dump
4925 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4926 //DAGC0_PEAK_MEAN
4927 u16Address = (DEBUG_OUT_DAGC0)&0xffff;
4928 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4929 u16Data = (u16Data>>4);
4930 DAGC0_Peak_Mean=(u16Data&0x0fff);
4931 //Unfreeze
4932 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4933
4934 //Debug select
4935 u16Address = (DEBUG_SEL_DAGC1_PEAK_MEAN>>16)&0xffff;
4936 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4937 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC1_PEAK_MEAN)&0xffff);
4938 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4939
4940 //Freeze and dump
4941 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4942 //DAGC1_PEAK_MEAN
4943 u16Address = (DEBUG_OUT_DAGC1)&0xffff;
4944 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4945 DAGC1_Peak_Mean=(u16Data&0x0fff);
4946 //Unfreeze
4947 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4948
4949 //Debug select
4950 u16Address = (DEBUG_SEL_DAGC2_PEAK_MEAN>>16)&0xffff;
4951 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4952 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC2_PEAK_MEAN)&0xffff);
4953 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4954
4955 //Freeze and dump
4956 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4957 //DAGC2_PEAK_MEAN
4958 u16Address = (DEBUG_OUT_DAGC2)&0xffff;
4959 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4960 DAGC2_Peak_Mean=(u16Data&0x0fff);
4961 //Unfreeze
4962 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4963
4964 //Debug select
4965 u16Address = (DEBUG_SEL_DAGC3_PEAK_MEAN>>16)&0xffff;
4966 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4967 u16Data=(((u16Data&0xfff0)|DEBUG_SEL_DAGC3_PEAK_MEAN)&0xffff);
4968 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
4969
4970 //Freeze and dump
4971 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4972 //DAGC3_PEAK_MEAN
4973 u16Address = (DEBUG_OUT_DAGC3)&0xffff;
4974 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4975 u16Data = (u16Data>>4);
4976 DAGC3_Peak_Mean=(u16Data&0x0fff);
4977 //Unfreeze
4978 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
4979
4980
4981 DAGC0_Peak_Mean = DAGC0_Peak_Mean / 0x800; //<12,11>
4982 DAGC1_Peak_Mean = DAGC1_Peak_Mean / 0x800; //<12,11>
4983 DAGC2_Peak_Mean = DAGC2_Peak_Mean / 0x800; //<12,11>
4984 DAGC3_Peak_Mean = DAGC3_Peak_Mean / 0x800; //<12,11>
4985
4986 printf("[DVBS]: DAGC0_Peak_Mean ===============: %f\n", DAGC0_Peak_Mean);
4987 printf("[DVBS]: DAGC1_Peak_Mean ===============: %f\n", DAGC1_Peak_Mean);
4988 printf("[DVBS]: DAGC2_Peak_Mean ===============: %f\n", DAGC2_Peak_Mean);
4989 printf("[DVBS]: DAGC3_Peak_Mean ===============: %f\n", DAGC3_Peak_Mean);
4990 //---------------------------------------------------------
4991 //Freeze and dump
4992 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
4993
4994 u16Address = (DCR_OFFSET)&0xffff;
4995 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
4996
4997 DCR_Offset_I=(u16Data&0xff);
4998 if (DCR_Offset_I >= 0x80)
4999 DCR_Offset_I = DCR_Offset_I-0x100;
5000 DCR_Offset_I = DCR_Offset_I/0x80;
5001
5002 DCR_Offset_Q=(u16Data>>8)&0xff;
5003 if (DCR_Offset_Q >= 0x80)
5004 DCR_Offset_Q = DCR_Offset_Q-0x100;
5005 DCR_Offset_Q = DCR_Offset_Q/0x80;
5006
5007 //Unfreeze
5008 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5009
5010 printf("[DVBS]: DCR_Offset_I ==================: %f\n", DCR_Offset_I);
5011 printf("[DVBS]: DCR_Offset_Q ==================: %f\n", DCR_Offset_Q);
5012 //---------------------------------------------------------
5013 ////Page1-FineCFO & PR & IIS & IQB
5014 //---------------------------------------------------------
5015 //FineCFO
5016 printf("------------------------------------------------------------------------\n");
5017 printf("Debug Message [FineCFO & PR & IIS & IQB & SNR Status]===================\n");
5018 //Debug Select
5019 u16Address = INNER_DEBUG_SEL;
5020 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5021 u16Data=((u16Data&0xC0FF)|0x0400);
5022 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5023
5024 //Freeze and dump
5025 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5026
5027 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5028 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5029 FineCFO_loop_out_value=u16Data;
5030 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5031 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5032 FineCFO_loop_out_value=(FineCFO_loop_out_value+(float)u16Data*pow(2.0, 16));
5033
5034 //Too large.Use 10Bit
5035 u16Address = INNEREXT_FINEFE_KI_FF0;
5036 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5037 FineCFO_loop_ki_value=u16Data;
5038 u16Address = INNEREXT_FINEFE_KI_FF2;
5039 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5040 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(float)u16Data*pow(2.0, 16));
5041 u16Address = INNEREXT_FINEFE_KI_FF4;
5042 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5043 FineCFO_loop_ki_value=(FineCFO_loop_ki_value+(double)(u16Data&0x00FF)*pow(2.0, 32));
5044 //Unfreeze
5045 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5046
5047 //---------------------------------------------------------
5048 //Debug Select
5049 u16Address = INNER_DEBUG_SEL;
5050 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5051 u16Data=((u16Data&0xC0FF)|0x0100);
5052 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5053
5054 //Freeze and dump
5055 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5056
5057 u16Address = INNEREXT_FINEFE_DBG_OUT0;
5058 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5059 FineCFO_loop_input_value=u16Data;
5060 u16Address = INNEREXT_FINEFE_DBG_OUT2;
5061 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5062 FineCFO_loop_input_value=(FineCFO_loop_input_value+(float)u16Data*pow(2.0, 16));
5063
5064 //Unfreeze
5065 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5066
5067 FineCFO_loop_ki_value = FineCFO_loop_ki_value/1024;
5068
5069 if (FineCFO_loop_out_value > 8388608)
5070 FineCFO_loop_out_value=FineCFO_loop_out_value - 16777216;
5071 if (FineCFO_loop_ki_value > 536870912)//549755813888/1024)
5072 FineCFO_loop_ki_value=FineCFO_loop_ki_value - 1073741824;//1099511627776/1024;
5073 if (FineCFO_loop_input_value> 1048576)
5074 FineCFO_loop_input_value=FineCFO_loop_input_value - 2097152;
5075
5076 FineCFO_loop_out_value = ((float)FineCFO_loop_out_value/16777216);
5077 FineCFO_loop_ki_value = ((double)FineCFO_loop_ki_value/67108864*u32DebugInfo_Fb);//68719476736/1024*Fb
5078 FineCFO_loop_input_value = ((float)FineCFO_loop_input_value/2097152);
5079
5080 printf("[DVBS]: FineCFO_loop_out_value ========: %f \n", FineCFO_loop_out_value);
5081 printf("[DVBS]: FineCFO_loop_ki_value =========: %f \n", FineCFO_loop_ki_value);
5082 printf("[DVBS]: FineCFO_loop_input_value ======: %f \n", FineCFO_loop_input_value);
5083
5084 //---------------------------------------------------------
5085 //Phase Recovery
5086 //Debug select
5087 u16Address = INNER_DEBUG_SEL;
5088 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5089 u16Data=(((u16Data&0x00FF)|0x0600)&0xffff);
5090 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5091
5092 //Freeze and dump
5093 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5094
5095 u16Address = INNER_PR_DEBUG_OUT0;
5096 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5097 PR_out_value=u16Data;
5098 if (PR_out_value>=0x1000)
5099 PR_out_value=PR_out_value-0x2000;
5100
5101 //Unfreeze
5102 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5103 //---------------------------------------------------------
5104 //Debug select
5105 u16Address = INNER_DEBUG_SEL;
5106 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5107 u16Data=(((u16Data&0x00FF)|0x0100)&0xffff);
5108 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5109
5110 //Freeze and dump
5111 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5112
5113 u16Address = INNER_PR_DEBUG_OUT0;
5114 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5115 PR_in_value=u16Data;
5116 u16Address = INNER_PR_DEBUG_OUT2;
5117 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5118 PR_in_value=(((u16Data&0x000F)<<16)|(MS_U16)PR_in_value);
5119 if (PR_in_value>=0x80000)
5120 PR_in_value=PR_in_value-0x100000;
5121
5122 //Unfreeze
5123 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5124 //---------------------------------------------------------
5125 //Debug select
5126 u16Address = INNER_DEBUG_SEL;
5127 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5128 u16Data=(((u16Data&0xC0FF)|0x0400)&0xffff);
5129 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5130
5131 //Freeze and dump
5132 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5133
5134 u16Address = INNER_PR_DEBUG_OUT0;
5135 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5136 PR_loop_ki=u16Data;
5137 u16Address = INNER_PR_DEBUG_OUT2;
5138 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5139 PR_loop_ki=(((u16Data&0x00FF)<<16)+PR_loop_ki);
5140 if (PR_loop_ki>=0x800000)
5141 PR_loop_ki=PR_loop_ki-0x1000000;
5142
5143 //Unfreeze
5144 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5145 //---------------------------------------------------------
5146 //Debug select
5147 u16Address = INNER_DEBUG_SEL;
5148 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5149 u16Data=(((u16Data&0x00FF)|0x0500)&0xffff);
5150 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5151
5152 //Freeze and dump
5153 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5154
5155 u16Address = INNER_PR_DEBUG_OUT0;
5156 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5157 PR_loopback_ki=u16Data;
5158 u16Address = INNER_PR_DEBUG_OUT2;
5159 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5160 PR_loopback_ki=(((u16Data&0x00FF)<<16)+PR_loopback_ki);
5161 if (PR_loopback_ki>=0x800000)
5162 PR_loopback_ki=PR_loopback_ki-0x1000000;
5163
5164 //Unfreeze
5165 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5166
5167 PR_out_value = ((float)PR_out_value/4096);
5168 PR_in_value = ((float)PR_in_value/131072);
5169 PR_loop_ki = ((float)PR_loop_ki/67108864*u32DebugInfo_Fb);
5170 PR_loopback_ki = ((float)PR_loopback_ki/67108864*u32DebugInfo_Fb);
5171
5172 printf("[DVBS]: PR_out_value ==================: %f\n", PR_out_value);
5173 printf("[DVBS]: PR_in_value ===================: %f\n", PR_in_value);
5174 printf("[DVBS]: PR_loop_ki ====================: %f\n", PR_loop_ki);
5175 printf("[DVBS]: PR_loopback_ki ================: %f\n", PR_loopback_ki);
5176 //---------------------------------------------------------
5177 //IIS
5178 //Freeze and dump
5179 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5180
5181 u16Address = (IIS_COUNT0)&0xffff;
5182 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5183 IIS_cnt=u16Data;
5184 u16Address = (IIS_COUNT2)&0xffff;
5185 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5186 IIS_cnt=(u16Data&0x1f)<<16|IIS_cnt;
5187
5188 printf("[DVBS]: IIS_cnt =======================: %d\n", IIS_cnt);
5189
5190 //Unfreeze
5191 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5192 //IQB
5193 //Freeze and dump
5194 bRet &= INTERN_DVBS_DTV_FrontendSetFreeze();
5195
5196 u16Address = (IQB_PHASE)&0xffff;
5197 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5198 IQB_Phase=u16Data&0x3FF;
5199 if (IQB_Phase>=0x200)
5200 IQB_Phase=IQB_Phase-0x400;
5201 IQB_Phase=IQB_Phase/0x400*180;
5202
5203 u16Address = (IQB_GAIN)&0xffff;
5204 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5205 IQB_Gain=u16Data&0x7FF;
5206 IQB_Gain=IQB_Gain/0x400;
5207
5208 printf("[DVBS]: IQB_Phase =====================: %f\n", IQB_Phase);
5209 printf("[DVBS]: IQB_Gain ======================: %f\n", IQB_Gain);
5210
5211 //Unfreeze
5212 bRet &= INTERN_DVBS_DTV_FrontendUnFreeze();
5213 //---------------------------------------------------------
5214 //SNR
5215 //Freeze and dump
5216 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5217
5218 Eq_variance_da=0;
5219 u16Address = 0x249E;
5220 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5221 Eq_variance_da=u16Data;
5222 u16Address = 0x24A0;
5223 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5224 Eq_variance_da=((float)(u16Data&0x03fff)*pow(2.0, 16)+Eq_variance_da)/pow(2.0, 29);
5225
5226 if (Eq_variance_da==0)
5227 Eq_variance_da=1;
5228 Linear_SNR_da=1.0/Eq_variance_da;
5229 SNR_da_dB=10*log10(Linear_SNR_da);
5230
5231 Eq_variance_dd=0;
5232 u16Address = 0x24A2;
5233 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5234 Eq_variance_dd=u16Data;
5235 u16Address = 0x24A4;
5236 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5237 Eq_variance_dd=(((float)(u16Data&0x3fff)*65536)+Eq_variance_dd)/pow(2.0, 29);
5238
5239 if (Eq_variance_dd==0)
5240 Eq_variance_dd=1;
5241 Linear_SNR_dd=1.0/Eq_variance_dd;
5242 SNR_dd_dB=10*log10(Linear_SNR_dd);
5243
5244 ndasnr_a=0;
5245 u16Address = 0x248C;
5246 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5247 ndasnr_a=u16Data;
5248 u16Address = 0x248E;
5249 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5250 ndasnr_a=(((float)(u16Data&0x0003)*pow(2.0, 16))+ndasnr_a)/65536;
5251
5252 ndasnr_ab=0;
5253 u16Address = 0x2490;
5254 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5255 ndasnr_ab=u16Data;
5256 u16Address = 0x2492;
5257 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5258 ndasnr_ab=(((float)(u16Data&0x03ff)*pow(2.0, 16))+ndasnr_ab)/4194304;
5259
5260 ndasnr_ab=sqrt(ndasnr_ab);
5261 if (ndasnr_ab==0)
5262 ndasnr_ab=1;
5263 ndasnr_ratio=(float)ndasnr_a/ndasnr_ab;
5264 if (ndasnr_ratio> 1)
5265 SNR_nda_dB=10*log10(1/(ndasnr_ratio - 1));
5266 else
5267 SNR_nda_dB=0;
5268
5269 u16Address = 0x24BA;
5270 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5271 Linear_SNR=u16Data;
5272 u16Address = 0x24BC;
5273 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5274 Linear_SNR=(((float)(u16Data&0x0007)*pow(2.0, 16))+Linear_SNR)/64;
5275 if (Linear_SNR==0)
5276 Linear_SNR=1;
5277 Linear_SNR=10*log10(Linear_SNR);
5278
5279 //Unfreeze
5280 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5281 printf("[DVBS]: SNR ===========================: %.2f\n", Linear_SNR);
5282 printf("[DVBS]: SNR_DA_dB =====================: %.2f\n", SNR_da_dB);
5283 printf("[DVBS]: SNR_DD_dB =====================: %.2f\n", SNR_dd_dB);
5284 printf("[DVBS]: SNR_NDA_dB ====================: %.2f\n", SNR_nda_dB);
5285 //---------------------------------------------------------
5286 printf("------------------------------------------------------------------------\n");
5287 printf("Debug Message [DVBS - PacketErr & BER]==================================\n");
5288 //BER
5289 //freeze
5290 u16Address = 0x2103;
5291 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5292 u16Data=u16Data|0x0001;
5293 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5294
5295 // bank 17 0x18 [7:0] reg_bit_err_sblprd_7_0 [15:8] reg_bit_err_sblprd_15_8
5296 u16Address = 0x2166;
5297 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5298 Packet_Err=u16Data;
5299
5300 printf("[DVBS]: Packet Err ====================: %.3E\n", Packet_Err);
5301
5302 /////////// Post-Viterbi BER /////////////
5303 // bank 7 0x18 [7:0] reg_bit_err_sblprd_7_0
5304 // [15:8] reg_bit_err_sblprd_15_8
5305 u16Address = 0x2146;
5306 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5307 BitErrPeriod=u16Data;
5308
5309 // bank 17 0x1D [7:0] reg_bit_err_num_7_0 [15:8] reg_bit_err_num_15_8
5310 // bank 17 0x1E [7:0] reg_bit_err_num_23_16 [15:8] reg_bit_err_num_31_24
5311 u16Address = 0x216A;
5312 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5313 BitErr=u16Data;
5314 u16Address = 0x216C;
5315 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5316 BitErr=(u16Data<<16)|BitErr;
5317
5318 if (BitErrPeriod ==0 )//protect 0
5319 BitErrPeriod=1;
5320 if (BitErr <=0 )
5321 BER=0.5 / (float)(BitErrPeriod*128*188*8);
5322 else
5323 BER=(float)(BitErr) / (float)(BitErrPeriod*128*188*8);
5324
5325 printf("[DVBS]: Post-Viterbi BER ==============: %.3E\n", BER);
5326
5327 // bank 7 0x19 [7] reg_bit_err_num_freeze
5328 u16Address = 0x2103;
5329 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5330 u16Data=u16Data&(~0x0001);
5331 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5332
5333 /////////// Pre-Viterbi BER /////////////
5334 // bank 17 0x08 [3] reg_rd_freezeber
5335 u16Address = 0x2110;
5336 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5337 u16Data=u16Data|0x0008;
5338 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5339
5340 // bank 17 0x0b [7:0] reg_ber_timerl [15:8] reg_ber_timerm
5341 // bank 17 0x0c [5:0] reg_ber_timerh
5342 u16Address = 0x2116;
5343 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5344 BitErrPeriod=u16Data;
5345 u16Address = 0x2118;
5346 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5347 BitErrPeriod=((u16Data&0x3f)<<16)|BitErrPeriod;
5348
5349 // bank 17 0x0f [7:0] reg_ber_7_0 [15:8] reg_ber_15_8
5350 u16Address = 0x211E;
5351 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5352 BitErr=u16Data;
5353
5354 // bank 17 0x0D [13:8] reg_cor_intstat_reg
5355 u16Address = 0x211A;
5356 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5357 if (u16Data & 0x1000)
5358 {
5359 BEROver = true;
5360 }
5361 else
5362 {
5363 BEROver = false;
5364 }
5365
5366 if (BitErrPeriod ==0 )//protect 0
5367 BitErrPeriod=1;
5368 if (BitErr <=0 )
5369 BER=0.5 / (float)(BitErrPeriod) / 256;
5370 else
5371 BER=(float)(BitErr) / (float)(BitErrPeriod) / 256;
5372 printf("[DVBS]: Pre-Viterbi BER ===============: %.3E\n", BER);
5373
5374 // bank 17 0x08 [3] reg_rd_freezeber
5375 u16Address = 0x2110;
5376 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5377 u16Data=u16Data&(~0x0008);
5378 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5379
5380 u16Address = 0x2188;
5381 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5382 ConvegenceLen = ((u16Data>>8)&0xFF);
5383 printf("[DVBS]: ConvegenceLen =================: %d\n", ConvegenceLen);
5384
5385 //---------------------------------------------------------
5386 //Timing Recovery
5387 //Debug select
5388 u16Address = (INNER_DEBUG_SEL_TR>>16)&0xffff;
5389 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5390 u16Data=(((u16Data&0x00ff)|INNER_DEBUG_SEL_TR)&0xffff);
5391 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5392
5393 //Freeze and dump
5394 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5395
5396 u16Address = (TR_INDICATOR_FF0)&0xffff;
5397 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5398 TR_Indicator_ff=u16Data;
5399 u16Address = (TR_INDICATOR_FF0)&0xffff;
5400 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5401 TR_Indicator_ff=((u16Data<<16) | (MS_U16)TR_Indicator_ff)&0x7fffff;
5402 if (TR_Indicator_ff >= 0x400000)
5403 TR_Indicator_ff=TR_Indicator_ff - 0x800000;
5404
5405 //Unfreeze
5406 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5407
5408 //Debug select
5409 u16Address = (DEBUG_SEL_TR_SFO_CONVERGE>>16)&0xffff;
5410 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5411 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_SFO_CONVERGE)&0xffff);
5412 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5413
5414 //Freeze and dump
5415 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5416
5417 u16Address = (TR_INDICATOR_FF0)&0xffff;
5418 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5419 TR_SFO_Converge=u16Data;
5420 u16Address = (TR_INDICATOR_FF0)&0xffff;
5421 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5422 TR_SFO_Converge=((u16Data<<16) | (MS_U16)TR_SFO_Converge)&0x7fffff;
5423 if (TR_SFO_Converge >= 0x400000)
5424 TR_SFO_Converge=TR_SFO_Converge - 0x800000;
5425
5426 u16Address = INNER_TR_LOPF_VALUE_DEBUG0;
5427 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5428 TR_loop_ki=u16Data;
5429 u16Address = INNER_TR_LOPF_VALUE_DEBUG2;
5430 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5431 TR_loop_ki=((float)u16Data*pow(2.0, 16))+TR_loop_ki;
5432 u16Address = INNER_TR_LOPF_VALUE_DEBUG4;
5433 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5434 TR_loop_ki=(((double)(u16Data&0x01ff)*pow(2.0, 32))+ TR_loop_ki);
5435 if (TR_loop_ki>=pow(2.0, 40))
5436 TR_loop_ki=TR_loop_ki-pow(2.0, 41);
5437
5438 //Unfreeze
5439 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5440
5441 //Debug select
5442 u16Address = (DEBUG_SEL_TR_INPUT>>16)&0xffff;
5443 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5444 u16Data=(((u16Data&0x00ff)|DEBUG_SEL_TR_INPUT)&0xffff);
5445 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
5446
5447 //Freeze and dump
5448 bRet &= INTERN_DVBS_DTV_InnerSetFreeze();
5449
5450 u16Address = (TR_INDICATOR_FF0)&0xffff;
5451 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
5452 TR_loop_input=u16Data;
5453 //banknum=(TR_INDICATOR_FF1>>8)&0xff;
5454 //addr=(TR_INDICATOR_FF1)&0xff;
5455 //if(InformRead(banknum, addr, &data)==FALSE) return;
5456 //TR_loop_input=((float)((data&0x00ff)<<16) + TR_loop_input);
5457 if (TR_loop_input >= 0x8000)
5458 TR_loop_input=TR_loop_input - 0x10000;
5459
5460 //Unfreeze
5461 bRet &= INTERN_DVBS_DTV_InnerUnFreeze();
5462
5463 Fs_value=u32DebugInfo_Fs;
5464 Fb_value=u32DebugInfo_Fb;
5465 TR_tmp0=(float)TR_SFO_Converge/0x200000;
5466 TR_tmp2=TR_loop_ki/pow(2.0, 39);
5467 TR_tmp1=(float)Fs_value/2/Fb_value;
5468
5469 TR_Indicator_ff = (TR_Indicator_ff/0x400);
5470 TR_Loop_Output = (TR_tmp0/TR_tmp1*1000000);
5471 TR_Loop_Ki = (TR_tmp2/TR_tmp1*1000000);
5472 TR_loop_input = (TR_loop_input/0x8000);
5473
5474 printf("[DVBS]: TR_Indicator_ff================: %f \n", TR_Indicator_ff);
5475 printf("[DVBS]: TR_Loop_Output=================: %f [ppm]\n", TR_Loop_Output);
5476 printf("[DVBS]: TR_Loop_Ki=====================: %f [ppm]\n", TR_Loop_Ki);
5477 printf("[DVBS]: TR_loop_input==================: %f \n", TR_loop_input);
5478 #endif
5479 bRet=true;
5480 return bRet;
5481 }
5482
5483 //------------------------------------------------------------------
5484 // END Get And Show Info Function
5485 //------------------------------------------------------------------
5486
5487 //------------------------------------------------------------------
5488 // BlindScan Function
5489 //------------------------------------------------------------------
5490
INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)5491 MS_BOOL INTERN_DVBS_BlindScan_Start(MS_U16 u16StartFreq,MS_U16 u16EndFreq)
5492 {
5493 MS_BOOL status=TRUE;
5494 MS_U8 u8Data=0;
5495
5496 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Start+\n"));
5497
5498 _u16BlindScanStartFreq=u16StartFreq;
5499 _u16BlindScanEndFreq=u16EndFreq;
5500 _u16TunerCenterFreq=0;
5501 _u16ChannelInfoIndex=0;
5502
5503 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5504 u8Data&=0xd0;
5505 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5506
5507 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)_u16BlindScanStartFreq&0x00ff);
5508 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(_u16BlindScanStartFreq>>8)&0x00ff);
5509
5510 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Start- _u16BlindScanStartFreq%d u16StartFreq %d u16EndFreq %d\n", _u16BlindScanStartFreq, u16StartFreq, u16EndFreq));
5511
5512 return status;
5513 }
5514
INTERN_DVBS_BlindScan_NextFreq(MS_BOOL * bBlindScanEnd)5515 MS_BOOL INTERN_DVBS_BlindScan_NextFreq(MS_BOOL* bBlindScanEnd)
5516 {
5517 MS_BOOL status=TRUE;
5518 MS_U8 u8Data=0;
5519
5520 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_NextFreq+\n"));
5521
5522 * bBlindScanEnd=FALSE;
5523
5524 if (_u16TunerCenterFreq >=_u16BlindScanEndFreq)
5525 {
5526 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_NextFreq . _u16TunerCenterFreq %d _u16BlindScanEndFreq%d\n", _u16TunerCenterFreq, _u16BlindScanEndFreq));
5527 * bBlindScanEnd=TRUE;
5528
5529 return status;
5530 }
5531 //Set Tuner Frequency
5532 MsOS_DelayTask(10);
5533
5534 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5535 if ((u8Data&0x02)==0x00)//Manual Tune
5536 {
5537 u8Data&=~(0x28);
5538 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5539 u8Data|=0x02;
5540 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5541 u8Data|=0x01;
5542 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5543 }
5544 else
5545 {
5546 u8Data&=~(0x28);
5547 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5548 }
5549
5550 return status;
5551 }
5552
INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 * u16TunerCenterFreq,MS_U16 * u16TunerCutOffFreq)5553 MS_BOOL INTERN_DVBS_BlindScan_GetTunerFreq(MS_U16 *u16TunerCenterFreq, MS_U16 *u16TunerCutOffFreq)
5554 {
5555 MS_BOOL status=TRUE;
5556 MS_U8 u8Data=0;
5557 MS_U16 u16WaitCount;
5558 MS_U16 u16TunerCutOff;
5559
5560 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_SetTunerFreq+\n"));
5561
5562 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5563 if ((u8Data&0x02)==0x02)
5564 {
5565 u8Data|=0x08;
5566 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5567 u16WaitCount=0;
5568 do
5569 {
5570 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5571 u16WaitCount++;
5572 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5573 MsOS_DelayTask(1);
5574 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5575 }
5576 else if((u8Data&0x01)==0x01)
5577 {
5578 u8Data|=0x20;
5579 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5580 u16WaitCount=0;
5581 do
5582 {
5583 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data);//SubState
5584 u16WaitCount++;
5585 //DBG_INTERN_DVBS(printf("MDrv_Demod_BlindScan_NextFreq u8Data:0x%x u16WaitCount:%d\n", u8Data, u16WaitCount));
5586 MsOS_DelayTask(1);
5587 }while((u8Data!=0x01)&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
5588 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5589 u8Data|=0x02;
5590 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5591 }
5592 u16WaitCount=0;
5593
5594 _u16TunerCenterFreq=0;
5595
5596 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5597 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_H=%d\n", u8Data);//RRRRR
5598 _u16TunerCenterFreq=u8Data;
5599 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5600 //printf("INTERN_DVBS_BlindScan_GetTunerFreq E_DMD_S2_BS_Tuner_Center_Freq_L=%d\n", u8Data);//RRRRR
5601 _u16TunerCenterFreq=(_u16TunerCenterFreq<<8)|u8Data;
5602
5603 *u16TunerCenterFreq = _u16TunerCenterFreq;
5604 //claire test
5605 u16TunerCutOff=44000;
5606 if(_u16TunerCenterFreq<=990)//980
5607 {
5608
5609 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BALANCE_TRACK, &u8Data);
5610 if(u8Data==0x01)
5611 {
5612 if(_u16TunerCenterFreq<970)//970
5613 {
5614 u16TunerCutOff=10000;
5615 }
5616 else
5617 {
5618 u16TunerCutOff=20000;
5619 }
5620 u8Data=0x02;
5621 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5622 }
5623 else if(u8Data==0x02)
5624 {
5625 u8Data=0x00;
5626 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_BALANCE_TRACK, u8Data);
5627 }
5628 }
5629 *u16TunerCutOffFreq = u16TunerCutOff;
5630
5631 //end claire test
5632
5633 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_SetTunerFreq- _u16TunerCenterFreq:%d\n", _u16TunerCenterFreq));
5634
5635
5636 return status;
5637 }
5638
INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8 * u8Progress,MS_U8 * u8FindNum,MS_U8 * substate_reg,MS_U32 * u32Data,MS_U16 * symbolrate_reg,MS_U16 * CFO_reg)5639 MS_BOOL INTERN_DVBS_BlindScan_WaitCurFreqFinished(MS_U8* u8Progress,MS_U8 *u8FindNum, MS_U8 *substate_reg, MS_U32 *u32Data, MS_U16 *symbolrate_reg, MS_U16 *CFO_reg)
5640 {
5641 MS_BOOL status=TRUE;
5642 //MS_U32 u32Data=0;
5643 MS_U16 u16Data=0;
5644 MS_U8 u8Data=0, u8Data2=0;
5645 MS_U16 u16WaitCount;
5646
5647 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished+\n"));
5648
5649 u16WaitCount=0;
5650 *u8FindNum=0;
5651 *u8Progress=0;
5652
5653 do
5654 {
5655 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_STATE_FLAG, &u8Data); //State=BlindScan
5656 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_BLINDSCAN_CHECK, &u8Data2); //SubState=BlindScan
5657 u16WaitCount++;
5658 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount));
5659 //printf("INTERN_DVBS_BlindScan_WaitCurFreqFinished State: 0x%x Status: 0x%x u16WaitCount:%d\n", u8Data, u8Data2, u16WaitCount);
5660
5661 MsOS_DelayTask(1);
5662 }while(((u8Data!=17)||(u8Data2!=0xff))&&(u16WaitCount<INTERN_DVBS_DEMOD_WAIT_TIMEOUT));//E_DMD_S2_STATE_FLAG
5663
5664
5665
5666 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DUMMY_REG_2, &u8Data);
5667 u16Data=u8Data;
5668
5669
5670 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished OuterCheckStatus:0x%x\n", u16Data));
5671
5672 if (u16WaitCount>=INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
5673 {
5674 status=false;
5675 ULOGD("DEMOD","Debug blind scan wait finished time out!!!!\n");
5676 }
5677 else
5678 {
5679
5680 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_SUBSTATE_FLAG, &u8Data);//SubState
5681 *substate_reg=u8Data;
5682 if (u8Data==0)
5683 {
5684
5685 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5686 *u32Data=u8Data;
5687 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5688 *u32Data=(*u32Data<<8)|u8Data;
5689 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5690 *u32Data=(*u32Data<<8)|u8Data;
5691 //_u16ChannelInfoArray[0][_u16ChannelInfoIndex]=((*u32Data+500)/1000);
5692 //_u16LockedCenterFreq=((*u32Data+500)/1000); //Center Freq
5693
5694
5695 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5696 u16Data=u8Data;
5697 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5698 u16Data=(u16Data<<8)|u8Data;
5699 *symbolrate_reg=u16Data;
5700 //_u16ChannelInfoArray[1][_u16ChannelInfoIndex]=(u16Data);//Symbol Rate
5701 //_u16LockedSymbolRate=u16Data;
5702 //_u16ChannelInfoIndex++;
5703 //*u8FindNum=_u16ChannelInfoIndex;
5704 //printf("claire debug blind scan: find TP frequency %d SR %d index %d\n",_u16LockedCenterFreq,_u16LockedSymbolRate,_u16ChannelInfoIndex);
5705
5706
5707 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5708 u16Data=u8Data;
5709 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5710 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset_Locked
5711 *CFO_reg=u16Data;
5712 /*
5713 if (u16Data*1000 >= 0x8000)
5714 {
5715 u16Data=0x10000- u16Data*1000;
5716 _s16CurrentCFO=-1*u16Data/1000;
5717 }
5718 else
5719 {
5720 _s16CurrentCFO=u16Data;
5721 }
5722 */
5723 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5724 u16Data=u8Data;
5725 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5726 u16Data=(u16Data<<8)|u8Data;
5727 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5728
5729
5730 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18H, &u8Data);
5731 u16Data=u8Data;
5732 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE18L, &u8Data);
5733 u16Data=(u16Data<<8)|u8Data;
5734 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5735
5736
5737 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19H, &u8Data);
5738 u16Data=u8Data;
5739 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE19L, &u8Data);
5740 u16Data=(u16Data<<8)|u8Data;
5741 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5742
5743 DBG_INTERN_DVBS(ULOGD("DEMOD","Current Locked BWH:%d BWL:%d Step:%d\n ",_u16PreLockedHB, _u16PreLockedLB, _u16CurrentStepSize));
5744 }
5745 else if (u8Data==1)
5746 {
5747 //printf("claire debug blind scan: no find TP\n");
5748
5749
5750 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, &u8Data);
5751 u16Data=u8Data;
5752 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, &u8Data);
5753 u16Data=(u16Data<<8)|u8Data;
5754 _u16NextCenterFreq=u16Data;
5755
5756
5757 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12H, &u8Data);
5758 u16Data=u8Data;
5759 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE12L, &u8Data);
5760 u16Data=(u16Data<<8)|u8Data;
5761 _u16PreLockedHB=u16Data; //Pre_Scanned_HB
5762
5763
5764
5765 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13H, &u8Data);
5766 u16Data=u8Data;
5767 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE13L, &u8Data);
5768 u16Data=(u16Data<<8)|u8Data;
5769 _u16PreLockedLB=u16Data; //Pre_Scanned_LB
5770
5771
5772 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14H, &u8Data);
5773 u16Data=u8Data;
5774 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE14L, &u8Data);
5775 u16Data=(u16Data<<8)|u8Data;
5776 _u16CurrentSymbolRate=u16Data; //Fine_Symbol_Rate
5777
5778
5779 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15H, &u8Data);
5780 u16Data=u8Data;
5781 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE15L, &u8Data);
5782 u16Data=(u16Data<<8)|u8Data; //Center_Freq_Offset
5783 *CFO_reg=u16Data;
5784 /*
5785 if (u16Data*1000 >= 0x8000)
5786 {
5787 u16Data=0x1000- u16Data*1000;
5788 _s16CurrentCFO=-1*u16Data/1000;
5789 }
5790 else
5791 {
5792 _s16CurrentCFO=u16Data;
5793 }
5794 */
5795 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16H, &u8Data);
5796 u16Data=u8Data;
5797 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_SWUSE16L, &u8Data);
5798 u16Data=(u16Data<<8)|u8Data;
5799 _u16CurrentStepSize=u16Data; //Tuner_Frequency_Step
5800
5801 DBG_INTERN_DVBS(ULOGD("DEMOD","Pre Locked BWH:%d BWL:%d Step:%d\n ",_u16PreLockedHB, _u16PreLockedLB, _u16CurrentStepSize));
5802 }
5803 }
5804 *u8Progress=100;
5805
5806 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_WaitCurFreqFinished- u8Progress: %d u8FindNum %d\n", *u8Progress, *u8FindNum));
5807
5808 return status;
5809 }
5810
INTERN_DVBS_BlindScan_Cancel(void)5811 MS_BOOL INTERN_DVBS_BlindScan_Cancel(void)
5812 {
5813 MS_BOOL status=TRUE;
5814 MS_U8 u8Data=0;
5815 MS_U16 u16Data;
5816
5817 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Cancel+\n"));
5818
5819 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5820 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5821 u8Data&=0xF0;
5822 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5823 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5824
5825 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5826 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5827 u16Data = 0x0000;
5828 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
5829 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
5830
5831 _u16TunerCenterFreq=0;
5832 _u16ChannelInfoIndex=0;
5833
5834 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_Cancel-\n"));
5835
5836 return status;
5837 }
5838
INTERN_DVBS_BlindScan_End(void)5839 MS_BOOL INTERN_DVBS_BlindScan_End(void)
5840 {
5841 MS_BOOL status=TRUE;
5842 MS_U8 u8Data=0;
5843 MS_U16 u16Data;
5844
5845 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_End+\n"));
5846
5847 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
5848 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
5849 u8Data&=0xF0;
5850 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
5851 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
5852
5853 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E1, 0x00);
5854 //MDrv_SYS_DMD_VD_MBX_WriteReg(0x20E0, 0x00);
5855 u16Data = 0x0000;
5856 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_92, (MS_U8)u16Data&0x00ff);
5857 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_93, (MS_U8)(u16Data>>8)&0x00ff);
5858
5859 _u16TunerCenterFreq=0;
5860 _u16ChannelInfoIndex=0;
5861
5862 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_End-\n"));
5863
5864 return status;
5865 }
5866
INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16 * u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM * pTable)5867 MS_BOOL INTERN_DVBS_BlindScan_GetChannel(MS_U16 u16ReadStart,MS_U16* u16TPNum,HAL_DEMOD_MS_FE_CARRIER_PARAM *pTable)
5868 {
5869 MS_BOOL status=TRUE;
5870 MS_U16 u16TableIndex;
5871
5872 *u16TPNum=_u16ChannelInfoIndex-u16ReadStart;
5873 for(u16TableIndex = 0; u16TableIndex < (*u16TPNum); u16TableIndex++)
5874 {
5875 pTable[u16TableIndex].u32Frequency = _u16ChannelInfoArray[0][_u16ChannelInfoIndex-1];
5876 pTable[u16TableIndex].SatParam.u32SymbolRate = _u16ChannelInfoArray[1][_u16ChannelInfoIndex-1];
5877 DBG_INTERN_DVBS(ULOGD("DEMOD","MDrv_Demod_BlindScan_GetChannel Freq: %d SymbolRate: %d\n", pTable[u16TableIndex].u32Frequency, pTable[u16TableIndex].SatParam.u32SymbolRate));
5878 }
5879 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_u16TPNum:%d\n", *u16TPNum));
5880
5881 return status;
5882 }
5883
INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 * u32CurrentFeq)5884 MS_BOOL INTERN_DVBS_BlindScan_GetCurrentFreq(MS_U32 *u32CurrentFeq)
5885 {
5886 MS_BOOL status=TRUE;
5887 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_GetCurrentFreq+\n"));
5888
5889 *u32CurrentFeq=_u16TunerCenterFreq;
5890 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_BlindScan_GetCurrentFreq-: %d\n", _u16TunerCenterFreq));
5891 return status;
5892 }
5893
5894 //------------------------------------------------------------------
5895 // END BlindScan Function
5896 //------------------------------------------------------------------
5897
5898 //------------------------------------------------------------------
5899 // DiSEqc Function
5900 //------------------------------------------------------------------
INTERN_DVBS_DiSEqC_Init(void)5901 MS_BOOL INTERN_DVBS_DiSEqC_Init(void)
5902 {
5903 MS_BOOL status = true;
5904 MS_U8 u8Data = 0;
5905
5906 //Clear status
5907 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
5908 u8Data=(u8Data|0x3E)&(~0x3E);
5909 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
5910
5911 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x00);
5912 //Tone En
5913 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC0, &u8Data);
5914 u8Data=(u8Data&(~0x06))|(0x06);
5915 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, u8Data);
5916
5917 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_Init\n"));
5918
5919 return status;
5920 }
5921
INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)5922 MS_BOOL INTERN_DVBS_DiSEqC_SetTone(MS_BOOL bTone1)
5923 {
5924 MS_BOOL status=TRUE;
5925 MS_U8 u8Data=0;
5926 MS_U8 u8ReSet22k=0;
5927
5928 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4, 0x01);//0x62;DVBS2_DISEQC_TX1
5929 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC0, 0x4E);//0x60
5930 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x88);//0x66
5931
5932 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);//0x61
5933 u8ReSet22k=u8Data;
5934
5935 if (bTone1==TRUE)
5936 {
5937 //Tone burst 1
5938 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x19);
5939 _u8ToneBurstFlag=1;
5940 }
5941 else
5942 {
5943 //Tone burst 0
5944 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, 0x11);
5945 _u8ToneBurstFlag=2;
5946 }
5947 //DIG_DISEQC_TX_EN
5948 //status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
5949 //u8Data=u8Data&~(0x01);//Tx Disable
5950 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
5951
5952 MsOS_DelayTask(1);
5953 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);//0x66 high byte DVBS2_DISEQC_TX_EN
5954 u8Data=u8Data|0x3E; //Status clear
5955 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
5956 MsOS_DelayTask(10);
5957 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
5958 u8Data=u8Data&~(0x3E);
5959 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
5960 MsOS_DelayTask(1);
5961
5962 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xCD, &u8Data);
5963 u8Data=u8Data|0x01; //Tx Enable
5964 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCD, u8Data);
5965
5966 MsOS_DelayTask(30);//(100)
5967 //For ToneBurst 22k issue.
5968 u8Data=u8ReSet22k;
5969 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);//0x61
5970
5971 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_SetTone:%d\n", bTone1));
5972 //MsOS_DelayTask(100);
5973 return status;
5974 }
5975
INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)5976 MS_BOOL INTERN_DVBS_DiSEqC_SetLNBOut(MS_BOOL bLow)
5977 {
5978 MS_BOOL status=TRUE;
5979 MS_U8 u8Data=0;
5980
5981 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
5982 if (bLow==TRUE)
5983 {
5984 u8Data=(u8Data|0x40); //13V
5985 }
5986 else
5987 {
5988 u8Data=(u8Data&(~0x40));//18V
5989 }
5990 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
5991
5992 return status;
5993 }
5994
INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL * bLNBOutLow)5995 MS_BOOL INTERN_DVBS_DiSEqC_GetLNBOut(MS_BOOL* bLNBOutLow)
5996 {
5997 MS_BOOL status=TRUE;
5998 MS_U8 u8Data=0;
5999
6000 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6001 if( (u8Data&0x40)==0x40)
6002 {
6003 * bLNBOutLow=TRUE;
6004 }
6005 else
6006 {
6007 * bLNBOutLow=FALSE;
6008 }
6009
6010 return status;
6011 }
6012
INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)6013 MS_BOOL INTERN_DVBS_DiSEqC_Set22kOnOff(MS_BOOL b22kOn)
6014 {
6015 MS_BOOL status=TRUE;
6016 MS_U8 u8Data=0;
6017
6018 //Set DiSeqC 22K
6019 //status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xCC, 0x44); //Set 11K-->22K
6020
6021 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6022
6023 if (b22kOn==TRUE)
6024 {
6025 u8Data=(u8Data&0xc7);
6026 u8Data=(u8Data|0x08);
6027 }
6028 else
6029 {
6030 u8Data=(u8Data&0xc7);
6031 }
6032 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC2, u8Data);
6033
6034 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS_DiSEqC_Set22kOnOff:%d\n", b22kOn));
6035 return status;
6036 }
6037
INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL * b22kOn)6038 MS_BOOL INTERN_DVBS_DiSEqC_Get22kOnOff(MS_BOOL* b22kOn)
6039 {
6040 MS_BOOL status=TRUE;
6041 MS_U8 u8Data=0;
6042
6043 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data);
6044 if ((u8Data&0x38)==0x08)
6045 {
6046 *b22kOn=TRUE;
6047 }
6048 else
6049 {
6050 *b22kOn=FALSE;
6051 }
6052
6053 return status;
6054 }
6055
INTERN_DVBS_DiSEqC_SendCmd(MS_U8 * pCmd,MS_U8 u8CmdSize)6056 MS_BOOL INTERN_DVBS_DiSEqC_SendCmd(MS_U8* pCmd,MS_U8 u8CmdSize)
6057 {
6058 MS_BOOL status=TRUE;
6059 MS_U8 u8Data;
6060 MS_U8 u8Index;
6061 MS_U16 u16WaitCount;
6062 /*
6063 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6064 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6065 u8Data=(u8Data&~(0x10));
6066 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6067 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6068 */
6069 #if 0 //For Unicable command timing
6070 u16WaitCount=0;
6071 do
6072 {
6073 MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data);
6074 //printf(">>> INTERN_DVBS_DiSEqC_SendCmd DiSEqC Status = 0x%x <<<\n", u8Data);
6075 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6076 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6077 MsOS_DelayTask(1);
6078 u16WaitCount++;
6079 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT));
6080
6081 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6082 {
6083 DBG_INTERN_DVBS(printf("INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6084 return FALSE;
6085 }
6086 #endif
6087
6088 //u16Address=0x0BC4;
6089 for (u8Index=0; u8Index < u8CmdSize; u8Index++)
6090 {
6091 u8Data=*(pCmd+u8Index);
6092 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xC4 + u8Index, u8Data);//#define DVBS2_DISEQC_TX1 (_REG_DVBS2(0x62)+0)//[7:0]
6093 DBG_INTERN_DVBS(ULOGD("DEMOD","=============INTERN_DVBS_DiSEqC_SendCmd(Demod1) = 0x%X\n",u8Data));
6094 }
6095
6096 //set DiSEqC Tx Length, Odd Enable, Tone Burst Mode
6097 u8Data=((u8CmdSize-1)&0x07)|0x40;
6098 if (_u8ToneBurstFlag==1)
6099 {
6100 u8Data|=0x80;//0x20;
6101 }
6102 else if (_u8ToneBurstFlag==2)
6103 {
6104 u8Data|=0x20;//0x80;
6105 }
6106 _u8ToneBurstFlag=0;
6107 status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, u8Data);
6108
6109 //add this only for check mailbox R/W
6110 #if 1
6111 DBG_INTERN_DVBS(ULOGD("DEMOD"," Write into E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6112 status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_DMDTOP_DBG_8, &u8Data);
6113 DBG_INTERN_DVBS(ULOGD("DEMOD"," Read from E_DMD_S2_MB_DMDTOP_DBG_8 = 0x%X!!!\n",u8Data));
6114 #endif
6115
6116 MsOS_DelayTask(25);//MsOS_DelayTask(10);
6117 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);//#define TOP_WR_DBG_90 (_REG_DMDTOP(0x3A)+0)
6118 //u8Data=u8Data|0x10;
6119 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data|0x10);//enable DiSEqC_Data_Tx
6120 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X +++<<<\n",u8Data));
6121 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>+++ INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d +++<<<\n",u8Data));
6122
6123 #if 1 //For Unicable command timing???
6124 u16WaitCount=0;
6125 do
6126 {
6127 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ***<<<\n",u8Data));
6128 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); DBG_INTERN_DVBS(printf(">>>*** INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ***<<<\n",u8Data));
6129 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6130 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6131 MsOS_DelayTask(1);
6132 u16WaitCount++;
6133 }while(((u8Data&0x10)==0x10)&&(u16WaitCount < INTERN_DVBS_DEMOD_WAIT_TIMEOUT)) ;
6134
6135 if (u16WaitCount >= INTERN_DVBS_DEMOD_WAIT_TIMEOUT)
6136 {
6137 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS DiSEqC Send Command Busy!!!\n"));
6138 return FALSE;
6139 }
6140 else
6141 {
6142 DBG_INTERN_DVBS(ULOGD("DEMOD","INTERN_DVBS DiSEqC Send Command Success!!!\n"));
6143 return TRUE;
6144 }
6145
6146
6147 #endif
6148 //MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xC2, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_Init_Mode = 0x%X ---<<<\n",u8Data);
6149 //MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_DISEQC_STATUS_FLAG, &u8Data); printf(">>>--- INTERN_DVBS_DiSEqC_SendCmd DiSEqC_State_Flag = %d ---<<<\n",u8Data+1);
6150
6151 return status;
6152 }
6153
INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)6154 MS_BOOL INTERN_DVBS_DiSEqC_SetTxToneMode(MS_BOOL bTxTone22kOff)
6155 {
6156 MS_BOOL status=TRUE;
6157 MS_U8 u8Data=0;
6158
6159 status &= MDrv_SYS_DMD_VD_MBX_ReadReg(DVBS2_REG_BASE + 0xD7, &u8Data);//h006b h006b 15 15 reg_diseqc_tx_tone_mode
6160 if (bTxTone22kOff==TRUE)
6161 {
6162 u8Data=(u8Data|0x80); //1: without 22K.
6163 }
6164 else
6165 {
6166 u8Data=(u8Data&(~0x80)); //0: with 22K.
6167 }
6168 status &= MDrv_SYS_DMD_VD_MBX_WriteReg(DVBS2_REG_BASE + 0xD7, u8Data);
6169
6170 return status;
6171 }
6172
INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)6173 MS_BOOL INTERN_DVBS_UnicableAGCCheckPower(MS_BOOL pbAGCCheckPower)
6174 {
6175 //MS_BOOL status = TRUE;
6176 MS_U8 u8Data=0;
6177
6178 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, 0x00);
6179
6180 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6181 u8Data &= 0xFE;//clean bit0
6182 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6183
6184 if (pbAGCCheckPower == FALSE)//0
6185 {
6186 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6187 u8Data &= 0xFE;//clean bit0
6188 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6189 //printf("CMD=MS_FALSE==============================\n");
6190 }
6191 else
6192 {
6193 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6194 u8Data |= 0x01; //bit1=1
6195 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6196 //printf("CMD=MS_TRUE==============================\n");
6197 }
6198
6199 MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + 0x60*2, &u8Data);
6200 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, &u8Data);
6201 u8Data &= 0xF0;
6202 u8Data |= 0x01;
6203 MDrv_SYS_DMD_VD_MBX_WriteReg(TOP_REG_BASE + 0x60*2, u8Data);
6204 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6205 MsOS_DelayTask(500);
6206
6207 //status &= MDrv_SYS_DMD_VD_MBX_ReadDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, &u8Data);
6208 u8Data &= 0x80; //Read bit7
6209 if (u8Data == 0x80)
6210 {
6211 u8Data = 0x00;
6212 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6213 u8Data = 0x00;
6214 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6215 return TRUE;
6216 }
6217 else
6218 {
6219 u8Data = 0x00;
6220 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_90, u8Data);
6221 u8Data = 0x00;
6222 //status &= MDrv_SYS_DMD_VD_MBX_WriteDSPReg(E_DMD_S2_MB_TOP_WR_DBG_91, u8Data);
6223 return FALSE;
6224 }
6225 }
6226
6227 //------------------------------------------------------------------
6228 // END DiSEqc Function
6229 //------------------------------------------------------------------
6230 //------------------------------------------------------------------
6231 // R/W Function
6232 //------------------------------------------------------------------
INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr,MS_U16 u16Data)6233 MS_BOOL INTERN_DVBS_WriteReg2bytes(MS_U16 u16Addr, MS_U16 u16Data)
6234 {
6235 MS_BOOL bRet= TRUE;
6236 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, (MS_U8)u16Data&0x00ff);
6237 bRet &= MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr + 0x0001, (MS_U8)(u16Data>>8)&0x00ff);
6238 return bRet;
6239 }
6240
INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr,MS_U16 * pu16Data)6241 MS_BOOL INTERN_DVBS_ReadReg2bytes(MS_U16 u16Addr, MS_U16 *pu16Data)
6242 {
6243 MS_BOOL bRet= TRUE;
6244 MS_U8 u8Data =0;
6245 MS_U16 u16Data =0;
6246
6247 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr + 0x0001, &u8Data);
6248 u16Data = u8Data;
6249 bRet &= MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, &u8Data);
6250 *pu16Data = (u16Data<<8)|u8Data;
6251
6252 return bRet;
6253 }
6254
6255 //Frontend Freeze
INTERN_DVBS_DTV_FrontendSetFreeze(void)6256 MS_BOOL INTERN_DVBS_DTV_FrontendSetFreeze(void)
6257 {
6258 MS_BOOL bRet= TRUE;
6259 MS_U16 u16Address;
6260 MS_U16 u16Data=0;
6261
6262 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6263 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6264 u16Data|=(FRONTEND_FREEZE_DUMP&0xffff);
6265 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6266
6267 return bRet;
6268 }
6269
INTERN_DVBS_DTV_FrontendUnFreeze(void)6270 MS_BOOL INTERN_DVBS_DTV_FrontendUnFreeze(void)
6271 {
6272 MS_BOOL bRet= TRUE;
6273 MS_U16 u16Address;
6274 MS_U16 u16Data=0;
6275
6276 u16Address = (FRONTEND_FREEZE_DUMP>>16)&0xffff;
6277 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6278 u16Data&=~(FRONTEND_FREEZE_DUMP&0xffff);
6279 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6280
6281 return bRet;
6282 }
6283
6284 //Inner Freeze
INTERN_DVBS_DTV_InnerSetFreeze(void)6285 MS_BOOL INTERN_DVBS_DTV_InnerSetFreeze(void)
6286 {
6287 MS_BOOL bRet= TRUE;
6288 MS_U16 u16Address;
6289 MS_U16 u16Data=0;
6290
6291 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6292 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6293 u16Data|=(INNER_FREEZE_DUMP&0xffff);
6294 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6295
6296 return bRet;
6297 }
6298
INTERN_DVBS_DTV_InnerUnFreeze(void)6299 MS_BOOL INTERN_DVBS_DTV_InnerUnFreeze(void)
6300 {
6301 MS_BOOL bRet= TRUE;
6302 MS_U16 u16Address;
6303 MS_U16 u16Data=0;
6304
6305 u16Address = (INNER_FREEZE_DUMP>>16)&0xffff;
6306 bRet &= INTERN_DVBS_ReadReg2bytes(u16Address, &u16Data);
6307 u16Data&=~(INNER_FREEZE_DUMP&0xffff);
6308 bRet &= INTERN_DVBS_WriteReg2bytes(u16Address, u16Data);
6309
6310 return bRet;
6311 }
6312 //------------------------------------------------------------------
6313 // END R/W Function
6314 //------------------------------------------------------------------
6315
6316
6317 /***********************************************************************************
6318 Subject: read register
6319 Function: MDrv_1210_IIC_Bypass_Mode
6320 Parmeter:
6321 Return:
6322 Remark:
6323 ************************************************************************************/
6324 //void MDrv_1210_IIC_Bypass_Mode(MS_BOOL enable)
6325 //{
6326 // UNUSED(enable);
6327 // if (enable)
6328 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x10); // IIC by-pass mode on
6329 // else
6330 // MDrv_SYS_DMD_VD_MBX_WriteReg(0x8010, 0x00); // IIC by-pass mode off
6331 //}
6332
6333