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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _INTERN_DVBC_H_ 96 #define _INTERN_DVBC_H_ 97 98 #ifdef _INTERN_DVBT_C_ 99 #define EXTSEL 100 #else 101 #define EXTSEL extern 102 #endif 103 104 #define NEW_TR_MODULE 105 //-------------------------------------------------------------------- 106 107 // #define DEMOD_DYNAMIC_SLAVE_ID_1 0x32 108 // #define DEMOD_DYNAMIC_SLAVE_ID_2 0x72 109 // #define DEMOD_DYNAMIC_SLAVE_ID_3 0xB2 110 // #define DEMOD_DYNAMIC_SLAVE_ID_4 0xF2 111 112 #define DEMOD_ADDR_H 0x00 113 #define DEMOD_ADDR_L 0x01 114 #define DEMOD_WRITE_REG 0x02 115 #define DEMOD_WRITE_REG_EX 0x03 116 #define DEMOD_READ_REG 0x04 117 #define DEMOD_RAM_CONTROL 0x05 118 119 #if 0//DTV_SCAN_AUTO_FINE_TUNE_ENABLE 120 //INTERN_DVBT_ Capture Range fix to 500K 121 #define DEMOD_CAPTURE_RANGE_500_K 500 122 #define DEMOD_CAPTURE_RANGE_SIZE DEMOD_CAPTURE_RANGE_500_K 123 #endif 124 125 #define MDrv_ReadByte(x) HAL_DMD_RIU_ReadByte(x) 126 #define MDrv_WriteByte(x,y) HAL_DMD_RIU_WriteByte(x,y) 127 128 #if 1 129 #define U8 MAPI_U8 130 #define U16 MAPI_U16 131 #define U32 MAPI_U32 132 #define BOOL MAPI_BOOL 133 #define BOOLEAN MAPI_BOOL 134 #if 0 135 #define BIT0 0x01 136 #define BIT1 0x02 137 #define BIT2 0x04 138 #define BIT3 0x08 139 #define BIT4 0x10 140 #define BIT5 0x20 141 #define BIT6 0x40 142 #define BIT7 0x80 143 #endif 144 #define BYTE MAPI_U8 145 146 #define WORD MAPI_WORD 147 #define E_RESULT_SUCCESS MAPI_TRUE 148 #define E_RESULT_FAILURE MAPI_FALSE 149 #define FUNCTION_RESULT MAPI_BOOL 150 151 152 153 154 #define INTERN_DVBC_TS_SERIAL_INVERSION 0 155 #define INTERN_DVBC_TS_PARALLEL_INVERSION 1 156 #define INTERN_DVBC_DTV_DRIVING_LEVEL 1 157 #define INTERN_DVBC_WEAK_SIGNAL_PICTURE_FREEZE_ENABLE 1 158 159 //#define SUPPORT_ADAPTIVE_TS_CLK 160 161 #endif 162 163 typedef enum 164 { 165 E_RF_QAM_MODE_16QAM = 0x00, ///< 16QAM 166 E_RF_QAM_MODE_32QAM = 0x01, ///< 32QAM 167 E_RF_QAM_MODE_64QAM = 0x02, ///< 64QAM 168 E_RF_QAM_MODE_128QAM = 0x03, ///< 128QAM 169 E_RF_QAM_MODE_256QAM = 0x04, ///< 256QAM 170 E_RF_QAM_MODE_INVALID ///< Invalid 171 } RF_CHANNEL_QAM_MODE; 172 173 #if 0 174 typedef enum 175 { 176 COFDM_FEC_LOCK, 177 COFDM_PSYNC_LOCK, 178 COFDM_TPS_LOCK, 179 COFDM_DCR_LOCK, 180 COFDM_AGC_LOCK, 181 COFDM_MODE_DET, 182 183 } COFDM_LOCK_STATUS; 184 185 //-------------------------------------------------------------------- 186 typedef enum 187 { 188 E_SYS_UNKOWN = -1, 189 E_SYS_DVBT, 190 E_SYS_DVBC, 191 E_SYS_ATSC, 192 E_SYS_VIF, 193 194 E_SYS_NUM 195 }E_SYSTEM; 196 197 typedef enum 198 { 199 CMD_SYSTEM_INIT = 0, 200 CMD_DAC_CALI, 201 CMD_DVBT_CONFIG, 202 CMD_DVBC_CONFIG, 203 CMD_VIF_CTRL, 204 CMD_FSM_CTRL, 205 CMD_INDIR_RREG, 206 CMD_INDIR_WREG, 207 CMD_GET_INFO, 208 CMD_TS_CTRL, 209 CMD_TUNED_VALUE, 210 211 CMD_MAX_NUM 212 }E_CMD_CODE; 213 214 typedef enum 215 { 216 pc_op_code = 0, 217 pc_if_freq, 218 pc_sound_sys, 219 pc_vif_vga_maximum_l, 220 pc_vif_vga_maximum_h, 221 pc_scan_mode, 222 pc_vif_top, 223 pc_gain_distribution_thr_l, 224 pc_gain_distribution_thr_h, 225 226 VIF_PARAM_MAX_NUM 227 }E_VIF_PARAM; 228 229 typedef enum 230 { 231 pc_system = 0, 232 233 SYS_PARAM_MAX_NUM 234 }E_SYS_PARAM; 235 236 typedef enum 237 { 238 SET_IF_FREQ = 0, 239 SET_SOUND_SYS, 240 VIF_INIT, 241 SET_VIF_HANDLER, 242 VIF_TOP_ADJUST, 243 244 VIF_CMD_MAX_NUM 245 }E_VIF_CMD; 246 247 typedef enum 248 { 249 TS_PARALLEL = 0, 250 TS_SERIAL = 1, 251 252 TS_MODE_MAX_NUM 253 }E_TS_MODE; 254 255 typedef enum 256 { 257 dac_op_code = 0, 258 dac_idac_ch0, 259 dac_idac_ch1, 260 261 DAC_PARAM_MAX_NUM 262 } 263 E_DAC_PARAM; 264 265 typedef enum 266 { 267 DAC_RUN_CALI = 0, 268 DAC_IDAC_ASSIGN, 269 270 DAC_CMD_MAX_NUM 271 } 272 E_DAC_CMD; 273 274 typedef enum 275 { 276 agc_ref_small, 277 agc_ref_large, 278 agc_ref_aci, 279 ripple_switch_th_l, 280 ripple_switch_th_h, 281 282 TUNED_PARAM_MAX_NUM 283 }E_TUNED_PARAM; 284 285 //@@++ Arki 20100125 286 typedef enum 287 { 288 TS_MODUL_MODE, 289 TS_FFX_VALUE, 290 TS_GUARD_INTERVAL, 291 TS_CODE_RATE, 292 293 TS_PARAM_MAX_NUM 294 }E_SIGNAL_TYPE; 295 //@@-- Arki 20100125 296 297 typedef struct 298 { 299 MS_U8 cmd_code; 300 MS_U8 param[64]; 301 } S_CMDPKTREG; 302 303 typedef enum 304 { 305 E_RF_QAM_MODE_16QAM = 0x00, ///< 16QAM 306 E_RF_QAM_MODE_32QAM = 0x01, ///< 32QAM 307 E_RF_QAM_MODE_64QAM = 0x02, ///< 64QAM 308 E_RF_QAM_MODE_128QAM = 0x03, ///< 128QAM 309 E_RF_QAM_MODE_256QAM = 0x04, ///< 256QAM 310 E_RF_QAM_MODE_INVALID ///< Invalid 311 } RF_CHANNEL_QAM_MODE; 312 313 typedef enum 314 { 315 S0_entry_num, 316 S10_PSYNC_fail_num, 317 S10_TPS_invalid_num, 318 S8_TPS_invalid_num, 319 S6_TPS_unlock_num, 320 S4_Mode_CP_unlock_num, 321 CCI_Tracking_lock_num, 322 CCI_Tracking_lock_p1_num, 323 CCI_Tracking_lock_p2_num, 324 S11_PSYNC_FAIL_LOCKED_num, 325 S11_PSYNC_FAIL_SEARCH_num, 326 lock_time_l, 327 lock_time_h, 328 hw_channel_length_l, 329 hw_channel_length_h, 330 sw_channel_length_l, 331 sw_channel_length_h, 332 sw_offset_SA_l, 333 sw_offset_SA_h, 334 sw_oneshot_peak_num, 335 CI_Indicator, 336 ACI_Indicator, 337 FD_coeff, 338 TD_coeff, 339 SNR_Select, 340 FsaMode, 341 InGI, 342 Fsa_Stop_Track, 343 short_echo_Det, 344 345 DBG_LIST_NUM 346 }DBG_table_type; 347 #endif 348 349 /* 350 // Move to Tuner_SSI.h 351 typedef enum 352 { 353 _QPSK = 0x0, 354 _16QAM = 0x1, 355 _64QAM = 0x2, 356 }E_CONSTEL; 357 358 typedef enum 359 { 360 _CR1Y2 = 0x0, 361 _CR2Y3 = 0x1, 362 _CR3Y4 = 0x2, 363 _CR5Y6 = 0x3, 364 _CR7Y8 = 0x4, 365 }E_CODERATE; 366 367 368 typedef struct 369 { 370 U8 constel; 371 U8 code_rate; 372 float cn_ref; 373 }S_SQI_CN_NORDIGP1_INTERN_DVBT; 374 375 typedef struct 376 { 377 float power_db; 378 U8 sar3_val; 379 }S_INTERN_DVBT_RFAGC_SSI; 380 381 typedef struct 382 { 383 float power_db; 384 U8 agc_val; 385 }S_INTERN_DVBT_IFAGC_SSI; 386 387 typedef struct 388 { 389 U8 constel; 390 U8 code_rate; 391 float p_ref; 392 }S_INTERN_DVBT_SSI_PREF; 393 394 typedef struct 395 { 396 float attn_db; 397 U8 agc_err; 398 }S_INTERN_DVBT_IFAGC_ERR; 399 */ 400 //-------------------------------------------------------------------- 401 typedef struct 402 { 403 MS_U8 cmd_code; 404 MS_U8 param[64]; 405 } S_CMDPKTREG; 406 407 typedef enum 408 { 409 TS_MODUL_MODE, 410 TS_FFX_VALUE, 411 TS_GUARD_INTERVAL, 412 TS_CODE_RATE, 413 414 TS_PARAM_MAX_NUM 415 }E_SIGNAL_TYPE; 416 417 typedef enum 418 { 419 CMD_SYSTEM_INIT = 0, 420 CMD_DAC_CALI, 421 CMD_DVBT_CONFIG, 422 CMD_DVBC_CONFIG, 423 CMD_VIF_CTRL, 424 CMD_FSM_CTRL, 425 CMD_INDIR_RREG, 426 CMD_INDIR_WREG, 427 CMD_GET_INFO, 428 CMD_TS_CTRL, 429 CMD_TUNED_VALUE, 430 431 CMD_MAX_NUM 432 }E_CMD_CODE; 433 434 typedef enum 435 { 436 TS_PARALLEL = 0, 437 TS_SERIAL = 1, 438 439 TS_MODE_MAX_NUM 440 }E_TS_MODE; 441 442 typedef enum 443 { 444 E_SYS_UNKOWN = -1, 445 E_SYS_DVBT, 446 E_SYS_DVBC, 447 E_SYS_ATSC, 448 E_SYS_VIF, 449 450 E_SYS_NUM 451 }E_SYSTEM; 452 //-------------------------------------------------------------------- 453 MS_BOOL INTERN_DVBC_Reset ( void ); 454 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable); 455 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt); 456 MS_BOOL INTERN_DVBC_Exit ( void ); 457 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize); 458 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size); 459 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk); 460 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num); 461 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable); 462 463 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, MS_U32 u32CurrRFPowerDbm, MS_U32 u32NoChannelRFPowerDbm, MS_U32 u32TimeInterval); 464 //waiting add 465 MS_BOOL INTERN_DVBC_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err); 466 //MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue); 467 //MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue); 468 MS_BOOL INTERN_DVBC_GetPostViterbiBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg); 469 470 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr); 471 472 MS_BOOL INTERN_DVBC_GetSNR(MS_U16 *snr_reg); 473 474 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id); 475 // MS_BOOL INTERN_DVBC_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType); 476 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver); 477 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate); 478 MS_BOOL INTERN_DVBC_Get_FreqOffset(MS_U32 *config_Fc_reg, MS_U32 *Fc_over_Fs_reg, MS_U16 *Cfo_offset_reg, MS_U8 u8BW); 479 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode); 480 481 482 MS_BOOL INTERN_DVBC_ActiveDmdSwitch(MS_U8 demod_no); 483 void INTERN_DVBC_InitClkgen(MS_BOOL bRFAGCTristateEnable); 484 MS_BOOL INTERN_DVBC_DMD51_Individual_Initialization(const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize); 485 486 #ifdef UFO_DEMOD_DVBC_SUPPORT_DMD_INT 487 MS_BOOL INTERN_DVBC_DEMOD_INTERRUPT_MONITOR(MS_U8* pu8IntType); 488 #endif 489 490 #ifdef SUPPORT_ADAPTIVE_TS_CLK 491 MS_BOOL INTERN_DVBC_Adaptive_TS_CLK(MS_U8 demod_index); 492 MS_BOOL INTERN_DVBC_Locked_Task(MS_U8 u8_demod_index); 493 #endif 494 #ifdef UFO_DEMOD_DVBC_GET_AGC_INFO 495 MS_BOOL INTERN_DVBC_AGC_Info(MS_U8 u8dbg_mode, MS_U16* pu16Data); 496 #endif 497 //-------------------------------------------------------------------- 498 499 #define INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY 500 501 #undef EXTSEL 502 #endif 503 504