1 //<MStar Software>
2 //******************************************************************************
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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_ISDBT.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_ISDBT_CHIP_EULER 0x00
112 #define DMD_ISDBT_CHIP_NUGGET 0x01
113 #define DMD_ISDBT_CHIP_KAPPA 0x02
114 #define DMD_ISDBT_CHIP_EINSTEIN 0x03
115 #define DMD_ISDBT_CHIP_NAPOLI 0x04
116 #define DMD_ISDBT_CHIP_MONACO 0x05
117 #define DMD_ISDBT_CHIP_MIAMI 0x06
118 #define DMD_ISDBT_CHIP_MUJI 0x07
119 #define DMD_ISDBT_CHIP_MANHATTAN 0x08
120 #define DMD_ISDBT_CHIP_MULAN 0x09
121 #define DMD_ISDBT_CHIP_MESSI 0x0A
122 #define DMD_ISDBT_CHIP_MASERATI 0x0B
123 #define DMD_ISDBT_CHIP_KIWI 0x0C
124 #define DMD_ISDBT_CHIP_MACAN 0x0D
125 #define DMD_ISDBT_CHIP_MUSTANG 0x0E
126 #define DMD_ISDBT_CHIP_MAXIM 0x0F
127 #if defined(CHIP_EULER)
128 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
129 #elif defined(CHIP_NUGGET)
130 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NUGGET
131 #elif defined(CHIP_KAPPA)
132 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KAPPA
133 #elif defined(CHIP_EINSTEIN)
134 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EINSTEIN
135 #elif defined(CHIP_NAPOLI)
136 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NAPOLI
137 #elif defined(CHIP_MIAMI)
138 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MIAMI
139 #elif defined(CHIP_MUJI)
140 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUJI
141 #elif defined(CHIP_MANHATTAN)
142 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MANHATTAN
143 #elif defined(CHIP_MULAN)
144 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MULAN
145 #elif defined(CHIP_MESSI)
146 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MESSI
147 #elif defined(CHIP_MASERATI)
148 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MASERATI
149 #elif defined(CHIP_KIWI)
150 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KIWI
151 #elif defined(CHIP_MACAN)
152 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MACAN
153 #elif defined(CHIP_MUSTANG)
154 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUSTANG
155 #elif defined(CHIP_MAXIM)
156 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MAXIM
157 #else
158 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
159 #endif
160
161 //-------------------------------------------------------------------------------------------------
162 // Local Defines
163 //-------------------------------------------------------------------------------------------------
164 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN)
165 #define DMD_ISDBT_TBVA_EN 1
166 #else
167 #define DMD_ISDBT_TBVA_EN 0
168 #endif
169 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr) ) )
170 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr), val) )
171
172 #define HAL_INTERN_ISDBT_DBINFO(y) //y
173 #ifndef MBRegBase
174 #define MBRegBase 0x112600UL
175 #endif
176 #ifndef MBRegBase_DMD1
177 #define MBRegBase_DMD1 0x112400UL
178 #endif
179 #ifndef DMDMcuBase
180 #define DMDMcuBase 0x103480UL
181 #endif
182
183 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_MESSI) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_KIWI)
184 #define REG_ISDBT_LOCK_STATUS 0x11F5
185 #define ISDBT_TDP_REG_BASE 0x1400
186 #define ISDBT_FDP_REG_BASE 0x1500
187 #define ISDBT_FDPEXT_REG_BASE 0x1600
188 #define ISDBT_OUTER_REG_BASE 0x1700
189 #else
190 #define REG_ISDBT_LOCK_STATUS 0x36F5
191 #define ISDBT_TDP_REG_BASE 0x3700
192 #define ISDBT_FDP_REG_BASE 0x3800
193 #define ISDBT_FDPEXT_REG_BASE 0x3900
194 #define ISDBT_OUTER_REG_BASE 0x3A00
195 #endif
196
197 //-------------------------------------------------------------------------------------------------
198 // Local Variables
199 //-------------------------------------------------------------------------------------------------
200
201 const MS_U8 INTERN_ISDBT_table[] = {
202 #include "DMD_INTERN_ISDBT.dat"
203 };
204
205 #ifndef UTPA2
206 static const float _LogApproxTableX[80] =
207 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
208 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
209 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
210 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
211 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
212 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
213 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
214 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
215 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
216 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
217 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
218 456767058.24, 593797175.72, 771936328.43, 1003517226.96
219 };
220
221 static const float _LogApproxTableY[80] =
222 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
223 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
224 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
225 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
226 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
227 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
228 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
229 };
230 #endif
231
232 //-------------------------------------------------------------------------------------------------
233 // Global Variables
234 //-------------------------------------------------------------------------------------------------
235
236 extern MS_U8 u8DMD_ISDBT_DMD_ID;
237
238 extern DMD_ISDBT_ResData *psDMD_ISDBT_ResData;
239
240 //-------------------------------------------------------------------------------------------------
241 // Local Functions
242 //-------------------------------------------------------------------------------------------------
243 #ifndef UTPA2
244
245 #ifndef MSOS_TYPE_LINUX
Log10Approx(float flt_x)246 static float Log10Approx(float flt_x)
247 {
248 MS_U8 indx = 0;
249
250 do {
251 if (flt_x < _LogApproxTableX[indx])
252 break;
253 indx++;
254 }while (indx < 79); //stop at indx = 80
255
256 return _LogApproxTableY[indx];
257 }
258 #endif
259
_CALCULATE_SQI(float fber)260 static MS_U16 _CALCULATE_SQI(float fber)
261 {
262 float flog_ber;
263 MS_U16 u16SQI;
264
265 #ifdef MSOS_TYPE_LINUX
266 flog_ber = (float)log10((double)fber);
267 #else
268 if (fber != 0.0)
269 flog_ber = (float)(-1.0*Log10Approx((double)(1.0 / fber)));
270 else
271 flog_ber = -8.0;//when fber=0 means u16SQI=100
272 #endif
273
274 //printf("dan fber = %f\n", fber);
275 //printf("dan flog_ber = %f\n", flog_ber);
276 // Part 2: transfer ber value to u16SQI value.
277 if (flog_ber <= ( - 7.0))
278 {
279 u16SQI = 100; //*quality = 100;
280 }
281 else if (flog_ber < -6.0)
282 {
283 u16SQI = (90+((( - 6.0) - flog_ber) / (( - 6.0) - ( - 7.0))*(100-90)));
284 }
285 else if (flog_ber < -5.5)
286 {
287 u16SQI = (80+((( - 5.5) - flog_ber) / (( - 5.5) - ( - 6.0))*(90-80)));
288 }
289 else if (flog_ber < -5.0)
290 {
291 u16SQI = (70+((( - 5.0) - flog_ber) / (( - 5.0) - ( - 5.5))*(80-70)));
292 }
293 else if (flog_ber < -4.5)
294 {
295 u16SQI = (60+((( - 4.5) - flog_ber) / (( -4.5) - ( - 5.0))*(70-50)));
296 }
297 else if (flog_ber < -4.0)
298 {
299 u16SQI = (50+((( - 4.0) - flog_ber) / (( - 4.0) - ( - 45))*(60-50)));
300 }
301 else if (flog_ber < -3.5)
302 {
303 u16SQI = (40+((( - 3.5) - flog_ber) / (( - 3.5) - ( - 4.0))*(50-40)));
304 }
305 else if (flog_ber < -3.0)
306 {
307 u16SQI = (30+((( - 3.0) - flog_ber) / (( - 3.0) - ( - 3.5))*(40-30)));
308 }
309 else if (flog_ber < -2.5)
310 {
311 u16SQI = (20+((( - 2.5) - flog_ber) / (( - 2.5) - ( -3.0))*(30-20)));
312 }
313 else if (flog_ber < -2.0)
314 {
315 u16SQI = (0+((( - 2.0) - flog_ber) / (( - 2.0) - ( - 2.5))*(20-0)));
316 }
317 else
318 {
319 u16SQI = 0;
320 }
321
322 return u16SQI;
323 }
324 #endif
325
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)326 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
327 {
328 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
329 }
330
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)331 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
332 {
333 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
334 }
335
_HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)336 static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
337 {
338 _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
339 }
340
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)341 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
342 {
343 MS_U8 u8CheckCount;
344 MS_U8 u8CheckFlag = 0xFF;
345 MS_U32 u32MBRegBase = MBRegBase;
346
347 if (u8DMD_ISDBT_DMD_ID == 0)
348 u32MBRegBase = MBRegBase;
349 else if (u8DMD_ISDBT_DMD_ID == 1)
350 u32MBRegBase = MBRegBase_DMD1;
351
352 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
353 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
354 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x10, u8Data);
355 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x01);
356
357 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
358 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
359
360 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
361 {
362 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
363 if ((u8CheckFlag&0x01)==0)
364 break;
365 MsOS_DelayTask(1);
366 }
367
368 if (u8CheckFlag&0x01)
369 {
370 printf("ERROR: ATSC INTERN DEMOD MBX WRITE TIME OUT!\n");
371 return FALSE;
372 }
373
374 return TRUE;
375 }
376
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)377 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
378 {
379 MS_U8 u8CheckCount;
380 MS_U8 u8CheckFlag = 0xFF;
381 MS_U32 u32MBRegBase = MBRegBase;
382
383 if (u8DMD_ISDBT_DMD_ID == 0)
384 u32MBRegBase = MBRegBase;
385 else if (u8DMD_ISDBT_DMD_ID == 1)
386 u32MBRegBase = MBRegBase_DMD1;
387
388 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
389 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
390 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x02);
391
392 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
393 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
394
395 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
396 {
397 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
398 if ((u8CheckFlag&0x02)==0)
399 {
400 *u8Data = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x10);
401 break;
402 }
403 MsOS_DelayTask(1);
404 }
405
406 if (u8CheckFlag&0x02)
407 {
408 printf("ERROR: ATSC INTERN DEMOD MBX READ TIME OUT!\n");
409 return FALSE;
410 }
411
412 return TRUE;
413 }
414
415
416
417 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER)
_HAL_INTERN_ISDBT_InitClk(void)418 static void _HAL_INTERN_ISDBT_InitClk(void)
419 {
420 printf("--------------DMD_ISDBT_CHIP_EULER--------------\n");
421
422 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
423
424 // Init by HKMCU
425 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
426 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
427 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
428 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
429 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
430 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
431 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
432
433 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
434 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
435 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
436 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
437 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
438 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
439 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
440 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
441 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
442 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
443 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
444 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
445 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
446 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
447 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
448 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
449 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
450 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
451 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
452 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
453 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
454 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
455 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
456
457 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
458 }
459 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET)
_HAL_INTERN_ISDBT_InitClk(void)460 static void _HAL_INTERN_ISDBT_InitClk(void)
461 {
462 MS_U8 u8Val = 0;
463
464 printf("--------------DMD_ISDBT_CHIP_NUGGET--------------\n");
465
466 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
467
468 // Init by HKMCU
469 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
470 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
471 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
472 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
473 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
474 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
475 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
476 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
477 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
478
479 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
480 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
481 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
482 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
483 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
484 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
485 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
486 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
487 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
488 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
489 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
490 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
491 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
492 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
493 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
494 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
495 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
496 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
497 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
498 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
499 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
500 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
501 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
502 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
503
504 u8Val = _HAL_DMD_RIU_ReadByte(0x1006F5);
505 _HAL_DMD_RIU_WriteByte(0x1006F5, (u8Val & ~0x03));
506
507 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
508 }
509 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
_HAL_INTERN_ISDBT_InitClk(void)510 static void _HAL_INTERN_ISDBT_InitClk(void)
511 {
512 printf("--------------DMD_ISDBT_CHIP_KAPPA--------------\n");
513
514 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
515
516 // Init by HKMCU
517 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
518 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
519 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
520 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
521 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
522 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
523 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
524
525 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
526 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
527 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
528 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
529 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
530 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
531 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
532 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
533 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
534 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
535 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
536 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
537 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
538 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
539 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
540 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
541 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
542 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
543 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
544 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
545 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
546 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
547 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
548
549 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
550 }
551 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN)
_HAL_INTERN_ISDBT_InitClk(void)552 static void _HAL_INTERN_ISDBT_InitClk(void)
553 {
554 MS_U8 u8Val = 0;
555
556 printf("--------------DMD_ISDBT_CHIP_EINSTEIN--------------\n");
557
558 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
559
560 // Init by HKMCU
561 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
562 u8Val &= ~0x01;
563 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
564
565 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
566 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
567 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
568 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
569 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
570 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
571 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
572 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
573 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
574
575 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
576 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
577 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
578 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
579 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
580 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
581 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
582 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
583 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
584 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
585 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
586 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
587 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
588 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
589 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
590 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
591 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
592 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
593 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
594 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
595 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
596 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
597 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
598 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
599
600 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
601 }
602 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI)
_HAL_INTERN_ISDBT_InitClk(void)603 static MS_BOOL _HAL_INTERN_ISDBT_InitClk(void) /* Ok */
604 {
605 MS_U8 u8Val = 0;
606
607 printf("--------------DMD_ISDBT_CHIP_NAPOLI--------------\n");
608
609 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
610
611 // Init by HKMCU
612 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
613 u8Val &= ~0x01;
614 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
615
616 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
617 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
618 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
619 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
620 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
621 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
622 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
623 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
624 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
625
626 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
627 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
628 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
629 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
630 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
631 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
632 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
633 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
634 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
635 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
636 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
637 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
638 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
639 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
640 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
641 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
642 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
643 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
644 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
645 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
646 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
647 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
648 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
649 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
650
651 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
652 }
653 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO)
_HAL_INTERN_ISDBT_InitClk(void)654 static void _HAL_INTERN_ISDBT_InitClk(void)
655 {
656 MS_U8 u8Val = 0;
657
658 printf("--------------DMD_ISDBT_CHIP_MONACO--------------\n");
659
660 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
661
662 // Init by HKMCU
663 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
664 u8Val &= ~0x01;
665 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
666
667 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
668 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
669 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
670 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
671 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
672 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
673 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
674 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
675
676 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
677 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
678 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
679 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
680 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
681 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
682 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
683 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
684 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
685 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
686 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
687 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
688 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
689 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
690 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
691 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
692 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
693 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
694 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
695 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
696 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
697 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
698 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
699 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
700 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
701 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
702 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
703 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
704
705 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
706 }
707 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI)
_HAL_INTERN_ISDBT_InitClk(void)708 static void _HAL_INTERN_ISDBT_InitClk(void)
709 {
710 printf("--------------DMD_ISDBT_CHIP_MIAMI--------------\n");
711
712 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
713
714 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
715 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
716 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
717 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
718 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
719 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
720 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
721 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
722
723 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
724 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
725 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
726 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
727 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
728 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
729 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
730 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
731 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
732 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
733 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
734 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
735 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
736 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
737 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
738 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
739 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
740 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
741 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
742 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
743 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
744 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
745 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
746 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
747 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
748 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
749 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
750 _HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
751
752 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
753 }
754 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI)
_HAL_INTERN_ISDBT_InitClk(void)755 static void _HAL_INTERN_ISDBT_InitClk(void)
756 {
757 printf("--------------DMD_ISDBT_CHIP_MUJI--------------\n");
758
759 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
760
761 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
762 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
763 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
764 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
765 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
766 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
767 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
768 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
769 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
770
771 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
772 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
773 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
774 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
775 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
776 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
777 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
778 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
779 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
780 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
781 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
782 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
783 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
784 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
785 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
786 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
787 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
788 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
789 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
790 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
791 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
792 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
793 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
794 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
795 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
796 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
797 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
798 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
799 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
800 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
801 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
802 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
803 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
804 _HAL_DMD_RIU_WriteByte(0x112091, 0x46);
805 _HAL_DMD_RIU_WriteByte(0x112090, 0x00);
806
807 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
808 }
809 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MANHATTAN)
_HAL_INTERN_ISDBT_InitClk(void)810 static void _HAL_INTERN_ISDBT_InitClk(void)
811 {
812 printf("--------------DMD_ISDBT_CHIP_MANHATTAN--------------\n");
813
814 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
815
816 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
817 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
818 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
819 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
820 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
821 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
822 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
823 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
824 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
825
826 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
827 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
828 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
829 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
830 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
831 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
832 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
833 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
834 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
835 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
836 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
837 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
838 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
839 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
840 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
841 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
842 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
843 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
844 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
845 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
846 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
847 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
848 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
849 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
850 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
851 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
852 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
853 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
854 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
855 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
856 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
857 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
858 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
859 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
860 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
861 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
862 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
863 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
864 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
865 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
866 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
867
868 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
869 }
870 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MULAN)
_HAL_INTERN_ISDBT_InitClk(void)871 static void _HAL_INTERN_ISDBT_InitClk(void)
872 {
873 printf("--------------DMD_ISDBT_CHIP_MULAN--------------\n");
874
875 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
876
877 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
878 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
879 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
880 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
881 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
882 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
883 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
884 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
885 _HAL_DMD_RIU_WriteByte(0x103302, 0x01); //reset ts divider
886
887 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
888 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
889 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
890 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
891 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
892 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
893 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
894 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
895 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
896 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
897 _HAL_DMD_RIU_WriteByte(0x111f24, 0x05);
898 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
899 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
900 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
901 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
902 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
903 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
904 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
905 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
906 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
907 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
908 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
909 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
910 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
911 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
912 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
913 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
914 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
915 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
916 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
917 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
918 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
919 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
920 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
921 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
922 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
923 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
924 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
925 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
926 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
927 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
928 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
929 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
930 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x88);
931 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
932 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
933 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
934 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
935 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
936 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
937
938 _HAL_DMD_RIU_WriteByte(0x103302, 0x00); //reset ts divider
939
940 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
941 }
942 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI)
_HAL_INTERN_ISDBT_InitClk(void)943 static void _HAL_INTERN_ISDBT_InitClk(void)
944 {
945 printf("--------------DMD_ISDBT_CHIP_MESSI--------------\n");
946
947 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
948
949 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
950 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
951 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
952 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
953 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
954 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
955 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
956 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
957 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
958
959 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
960 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
961 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
962 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
963 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
964 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
965 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
966 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
967 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
968 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
969 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
970 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
971 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
972 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
973 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
974 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
975 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
976 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
977 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
978 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
979 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
980 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
981 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
982 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
983 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
984 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
985 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
986 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
987 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
988 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
989 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
990 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x0C);
991 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
992 _HAL_DMD_RIU_WriteByte(0x111f51, 0x48);
993 _HAL_DMD_RIU_WriteByte(0x111f50, 0x44);
994 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
995 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
996 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
997 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
998 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
999 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
1000 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
1001 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
1002 _HAL_DMD_RIU_WriteByte(0x111f89, 0x44);
1003 _HAL_DMD_RIU_WriteByte(0x111f88, 0x44);
1004 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1005 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x44);
1006 _HAL_DMD_RIU_WriteByte(0x111f8d, 0x18);
1007 _HAL_DMD_RIU_WriteByte(0x111f8c, 0x44);
1008 _HAL_DMD_RIU_WriteByte(0x111f8f, 0x00);
1009 _HAL_DMD_RIU_WriteByte(0x111f8e, 0x44);
1010
1011 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1012 }
1013
1014 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MASERATI)
_HAL_INTERN_ISDBT_InitClk(void)1015 static void _HAL_INTERN_ISDBT_InitClk(void)
1016 {
1017 printf("--------------DMD_ISDBT_CHIP_MASERATI--------------\n");
1018
1019 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1020
1021 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1022 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1023 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1024 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1025 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1026 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1027 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1028 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1029 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1030
1031 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1032 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1033 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1034 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1035 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1036 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1037 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1038 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1039 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1040 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1041 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1042 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1043 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1044 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1045 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1046 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1047 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1048 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1049 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1050 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1051 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1052 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1053 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1054 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1055 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1056 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1057 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1058 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1059 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1060 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1061 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1062 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1063 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1064 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1065 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1066 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1067 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1068 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1069 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1070 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1071 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1072 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1073 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1074 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1075 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1076 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1077 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1078 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1079 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1080 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1081 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1082 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1083 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1084 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1085 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1086 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1087 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1088 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1089 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1090 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1091 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1092 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1093 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1094
1095 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1096 }
1097 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MACAN)
_HAL_INTERN_ISDBT_InitClk(void)1098 static void _HAL_INTERN_ISDBT_InitClk(void)
1099 {
1100 printf("--------------DMD_ISDBT_CHIP_MACAN--------------\n");
1101
1102 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1103
1104 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1105 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1106 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1107 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1108 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1109 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1110 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1111 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1112 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1113
1114 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1115 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1116 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1117 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1118 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1119 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1120 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1121 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1122 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1123 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1124 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1125 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1126 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1127 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1128 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1129 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1130 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1131 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1132 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1133 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1134 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1135 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1136 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1137 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1138 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1139 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1140 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1141 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1142 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1143 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1144 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1145 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1146 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1147 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1148 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1149 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1150 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1151 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1152 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1153 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1154 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1155 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1156 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1157 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1158 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1159 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1160 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1161 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1162 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1163 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1164 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1165 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1166 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1167 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1168 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1169 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1170 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1171 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1172 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1173 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1174 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1175 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1176 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1177
1178 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1179 }
1180 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG)
_HAL_INTERN_ISDBT_InitClk(void)1181 static void _HAL_INTERN_ISDBT_InitClk(void)
1182 {
1183 printf("--------------DMD_ISDBT_CHIP_MUSTANG--------------\n");
1184
1185 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1186
1187 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1188 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1189 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1190 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1191 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1192 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1193 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1194 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1195 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1196
1197 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1198 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1199 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1200 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1201 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1202 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1203 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1204 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1205 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1206 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1207 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1208 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1209 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1210 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1211 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1212 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1213 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1214 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1215 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1216 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1217 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1218 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1219 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1220 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1221 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1222 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1223 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1224 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1225 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1226 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1227 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1228 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1229 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1230 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1231 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1232 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1233 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1234 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1235 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1236 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1237 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1238 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1239 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1240 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1241 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1242 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1243 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1244 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1245 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1246 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1247 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1248 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1249 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1250 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1251 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1252 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1253 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1254 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1255 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1256 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1257 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1258 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1259 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1260
1261 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1262 }
1263 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MAXIM)
_HAL_INTERN_ISDBT_InitClk(void)1264 static void _HAL_INTERN_ISDBT_InitClk(void)
1265 {
1266 printf("--------------DMD_ISDBT_CHIP_MAXIM--------------\n");
1267
1268 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1269
1270 _HAL_DMD_RIU_WriteByte(0x1128e5, 0x01); // DMD_ANA_ADC_SYNC CLK_W
1271 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x01); // DMD_ANA_ADC_SYNC CLK_W
1272
1273 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1274 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1275 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1276 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1277 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1278 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1279 //_HAL_DMD_RIU_WriteByte(0x103315, 0x00); //ADC SYNC FLOW
1280 //_HAL_DMD_RIU_WriteByte(0x103314, 0x00); //ADC SYNC FLOW
1281 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1282 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1283
1284 //_HAL_DMD_RIU_WriteByte(0x103321, 0x00); //Add in MAXIM //ADC SYNC FLOW
1285 //_HAL_DMD_RIU_WriteByte(0x103320, 0x00); //Add in MAXIM //ADC SYNC FLOW
1286
1287 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1288 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1289
1290 _HAL_DMD_RIU_WriteByte(0x103321, 0x00); //ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1291 _HAL_DMD_RIU_WriteByte(0x103320, 0x00); //ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1292
1293 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x00); // DMD_ANA_ADC_SYNC CLK_W
1294
1295 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1296 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1297 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1298 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1299 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1300 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1301 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1302 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1303 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1304 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1305 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1306 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1307 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1308 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1309 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1310 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1311 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1312 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1313 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1314 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1315 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1316 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1317 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1318 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1319 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1320 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1321 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1322 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1323 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1324 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1325 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1326 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1327 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1328 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1329 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1330 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1331 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1332 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1333 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1334 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1335 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1336 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1337 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1338 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1339 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1340 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1341 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1342 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1343 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1344 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1345 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1346 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1347 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1348 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1349 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1350 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1351 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1352 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1353
1354 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1355 //_HAL_DMD_RIU_WriteByteMask(0x103480, 0x00, 0x02);
1356 }
1357 #else
_HAL_INTERN_ISDBT_InitClk(void)1358 static void _HAL_INTERN_ISDBT_InitClk(void)
1359 {
1360 printf("--------------DMD_ISDBT_CHIP_NONE--------------\n");
1361 }
1362 #endif
1363
_HAL_INTERN_ISDBT_Ready(void)1364 static MS_BOOL _HAL_INTERN_ISDBT_Ready(void)
1365 {
1366 MS_U8 udata = 0x00;
1367
1368 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1369
1370 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1371 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1372
1373 MsOS_DelayTask(1);
1374
1375 udata = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1376
1377 if (udata) return FALSE;
1378
1379 return TRUE;
1380 }
1381
_HAL_INTERN_ISDBT_Download(void)1382 static MS_BOOL _HAL_INTERN_ISDBT_Download(void)
1383 {
1384 DMD_ISDBT_ResData *pRes = psDMD_ISDBT_ResData + u8DMD_ISDBT_DMD_ID;
1385
1386 MS_U8 udata = 0x00;
1387 MS_U16 i = 0;
1388 MS_U16 fail_cnt = 0;
1389 MS_U8 u8TmpData;
1390 MS_U16 u16AddressOffset;
1391 const MS_U8 *ISDBT_table;
1392 MS_U16 u16Lib_size;
1393
1394 if (pRes->sDMD_ISDBT_PriData.bDownloaded)
1395 {
1396 if (_HAL_INTERN_ISDBT_Ready())
1397 {
1398 #if DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG
1399 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x02, 0x02); // reset RIU remapping
1400 #endif
1401 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset VD_MCU
1402 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x03);
1403
1404 MsOS_DelayTask(20);
1405 return TRUE;
1406 }
1407 }
1408
1409 ISDBT_table = &INTERN_ISDBT_table[0];
1410 u16Lib_size = sizeof(INTERN_ISDBT_table);
1411
1412 #if DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG
1413 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x02, 0x02); // reset RIU remapping
1414 #endif
1415 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset VD_MCU
1416 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1417
1418 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x01); // release MCU, madison patch
1419
1420 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1421 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1422 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1423 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1424
1425 //// Load code thru VDMCU_IF ////
1426 HAL_INTERN_ISDBT_DBINFO(printf(">Load Code...\n"));
1427
1428 for (i = 0; i < u16Lib_size; i++)
1429 {
1430 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ISDBT_table[i]); // write data to VD MCU 51 code sram
1431 }
1432
1433 //// Content verification ////
1434 HAL_INTERN_ISDBT_DBINFO(printf(">Verify Code...\n"));
1435
1436 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1437 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1438
1439 for (i = 0; i < u16Lib_size; i++)
1440 {
1441 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1442
1443 if (udata != ISDBT_table[i])
1444 {
1445 HAL_INTERN_ISDBT_DBINFO(printf(">fail add = 0x%x\n", i));
1446 HAL_INTERN_ISDBT_DBINFO(printf(">code = 0x%x\n", INTERN_ISDBT_table[i]));
1447 HAL_INTERN_ISDBT_DBINFO(printf(">data = 0x%x\n", udata));
1448
1449 if (fail_cnt++ > 10)
1450 {
1451 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode fail!"));
1452 return FALSE;
1453 }
1454 }
1455 }
1456
1457 u16AddressOffset = (ISDBT_table[0x400] << 8)|ISDBT_table[0x401];
1458
1459 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1460 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1461
1462 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16IF_KHZ;
1463 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1464 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16IF_KHZ >> 8);
1465 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1466 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.bIQSwap;
1467 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1468 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue;
1469 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1470 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue >> 8);
1471 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1472 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u32TdiStartAddr;
1473 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1474 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 8);
1475 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1476 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 16);
1477 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1478 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 24);
1479 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1480
1481 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1482 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1483
1484 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset MCU, madison patch
1485
1486 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1487 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x03); // release VD_MCU
1488
1489 pRes->sDMD_ISDBT_PriData.bDownloaded = true;
1490
1491 MsOS_DelayTask(20);
1492
1493 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode done."));
1494
1495 return TRUE;
1496 }
1497
_HAL_INTERN_ISDBT_FWVERSION(void)1498 static void _HAL_INTERN_ISDBT_FWVERSION(void)
1499 {
1500 MS_U8 data1 = 0;
1501 MS_U8 data2 = 0;
1502 MS_U8 data3 = 0;
1503
1504 _MBX_ReadReg(0x20C4, &data1);
1505 _MBX_ReadReg(0x20C5, &data2);
1506 _MBX_ReadReg(0x20C6, &data3);
1507
1508 printf("INTERN_ISDBT_FW_VERSION:%x.%x.%x\n", data1, data2, data3);
1509 }
1510
_HAL_INTERN_ISDBT_Exit(void)1511 static MS_BOOL _HAL_INTERN_ISDBT_Exit(void)
1512 {
1513 MS_U8 u8CheckCount = 0;
1514
1515 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1516
1517 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1518 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1519
1520 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1521 {
1522 MsOS_DelayTaskUs(10);
1523
1524 if (u8CheckCount++ == 0xFF)
1525 {
1526 printf(">> ISDBT Exit Fail!\n");
1527 return FALSE;
1528 }
1529 }
1530
1531 printf(">> ISDBT Exit Ok!\n");
1532
1533 return TRUE;
1534 }
1535
_HAL_INTERN_ISDBT_SoftReset(void)1536 static MS_BOOL _HAL_INTERN_ISDBT_SoftReset(void)
1537 {
1538 MS_U8 u8Data = 0;
1539
1540 //Reset FSM
1541 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1542
1543 while (u8Data!=0x02)
1544 {
1545 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1546 }
1547
1548 return TRUE;
1549 }
1550
_HAL_INTERN_ISDBT_SetACICoef(void)1551 static MS_BOOL _HAL_INTERN_ISDBT_SetACICoef(void)
1552 {
1553 return TRUE;
1554 }
1555
_HAL_INTERN_ISDBT_SetIsdbtMode(void)1556 static MS_BOOL _HAL_INTERN_ISDBT_SetIsdbtMode(void)
1557 {
1558 if (_MBX_WriteReg(0x20C2, 0x04)==FALSE) return FALSE;
1559 return _MBX_WriteReg(0x20C0, 0x04);
1560 }
1561
_HAL_INTERN_ISDBT_SetModeClean(void)1562 static MS_BOOL _HAL_INTERN_ISDBT_SetModeClean(void)
1563 {
1564 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1565 return _MBX_WriteReg(0x20C0, 0x00);
1566 }
1567
_HAL_INTERN_ISDBT_Check_FEC_Lock(void)1568 static MS_BOOL _HAL_INTERN_ISDBT_Check_FEC_Lock(void)
1569 {
1570 MS_BOOL bCheckPass = FALSE;
1571 MS_U8 u8Data = 0;
1572
1573 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1574
1575 if ((u8Data & 0x02) != 0x00) // Check FEC Lock Flag
1576 bCheckPass = TRUE;
1577
1578 return bCheckPass;
1579 }
1580
_HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)1581 static MS_BOOL _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)
1582 {
1583 MS_BOOL bCheckPass = FALSE;
1584 MS_U8 u8Data = 0;
1585
1586 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1587
1588 if ((u8Data & 0x01) != 0x00) // Check FSA Track Lock Flag
1589 bCheckPass = TRUE;
1590
1591 return bCheckPass;
1592 }
1593
_HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)1594 static MS_BOOL _HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)
1595 {
1596 MS_BOOL bCheckPass = FALSE;
1597 MS_U8 u8Data = 0;
1598
1599 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1600
1601 if ((u8Data & 0x04) != 0x00) // Check Psync Lock Flag
1602 bCheckPass = TRUE;
1603
1604 return bCheckPass;
1605 }
1606
_HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)1607 static MS_BOOL _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)
1608 {
1609 MS_BOOL bCheckPass = FALSE;
1610 MS_U8 u8Data = 0;
1611
1612 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1613
1614 if ((u8Data & 0x80) != 0x00) // Check Psync Lock Flag
1615 bCheckPass = TRUE;
1616
1617 return bCheckPass;
1618 }
1619
_HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CODE_RATE * peIsdbtCodeRate)1620 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CODE_RATE *peIsdbtCodeRate)
1621 {
1622 MS_BOOL bRet = TRUE;
1623 MS_U8 u8Data = 0;
1624 MS_U8 u8CodeRate = 0;
1625
1626 switch (eLayerIndex)
1627 {
1628 case E_ISDBT_Layer_A:
1629 // [10:8] reg_tmcc_cur_convolution_code_rate_a
1630 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1631 u8CodeRate = u8Data & 0x07;
1632 break;
1633 case E_ISDBT_Layer_B:
1634 // [10:8] reg_tmcc_cur_convolution_code_rate_b
1635 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1636 u8CodeRate = u8Data & 0x07;
1637 break;
1638 case E_ISDBT_Layer_C:
1639 // [10:8] reg_tmcc_cur_convolution_code_rate_c
1640 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1641 u8CodeRate = u8Data & 0x07;
1642 break;
1643 default:
1644 u8CodeRate = 15;
1645 break;
1646 }
1647
1648 switch (u8CodeRate)
1649 {
1650 case 0:
1651 *peIsdbtCodeRate = E_ISDBT_CODERATE_1_2;
1652 break;
1653 case 1:
1654 *peIsdbtCodeRate = E_ISDBT_CODERATE_2_3;
1655 break;
1656 case 2:
1657 *peIsdbtCodeRate = E_ISDBT_CODERATE_3_4;
1658 break;
1659 case 3:
1660 *peIsdbtCodeRate = E_ISDBT_CODERATE_5_6;
1661 break;
1662 case 4:
1663 *peIsdbtCodeRate = E_ISDBT_CODERATE_7_8;
1664 break;
1665 default:
1666 *peIsdbtCodeRate = E_ISDBT_CODERATE_INVALID;
1667 break;
1668 }
1669
1670 return bRet;
1671 }
1672
_HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL * peIsdbtGI)1673 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL *peIsdbtGI)
1674 {
1675 MS_BOOL bRet = TRUE;
1676 MS_U8 u8Data = 0;
1677 MS_U8 u8CP = 0;
1678
1679 // [7:6] reg_mcd_out_cp
1680 // output cp -> 00: 1/4
1681 // 01: 1/8
1682 // 10: 1/16
1683 // 11: 1/32
1684 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1685
1686 u8CP = (u8Data >> 6) & 0x03;
1687
1688 switch (u8CP)
1689 {
1690 case 0:
1691 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_4;
1692 break;
1693 case 1:
1694 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_8;
1695 break;
1696 case 2:
1697 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_16;
1698 break;
1699 case 3:
1700 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_32;
1701 break;
1702 }
1703
1704 return bRet;
1705 }
1706
_HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_TIME_INTERLEAVING * peIsdbtTDI)1707 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_TIME_INTERLEAVING *peIsdbtTDI)
1708 {
1709 MS_BOOL bRet = TRUE;
1710 MS_U8 u8Data = 0;
1711 MS_U8 u8Mode = 0;
1712 MS_U8 u8Tdi = 0;
1713
1714 // [5:4] reg_mcd_out_mode
1715 // output mode -> 00: 2k
1716 // 01: 4k
1717 // 10: 8k
1718 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1719
1720 u8Mode = (u8Data >> 4) & 0x03;
1721
1722 switch (eLayerIndex)
1723 {
1724 case E_ISDBT_Layer_A:
1725 // [14:12] reg_tmcc_cur_interleaving_length_a
1726 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1727 u8Tdi = (u8Data >> 4) & 0x07;
1728 break;
1729 case E_ISDBT_Layer_B:
1730 // [14:12] reg_tmcc_cur_interleaving_length_b
1731 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1732 u8Tdi = (u8Data >> 4) & 0x07;
1733 break;
1734 case E_ISDBT_Layer_C:
1735 // [14:12] reg_tmcc_cur_interleaving_length_c
1736 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1737 u8Tdi = (u8Data >> 4) & 0x07;
1738 break;
1739 default:
1740 u8Tdi = 15;
1741 break;
1742 }
1743
1744 // u8Tdi+u8Mode*4
1745 // => 0~3: 2K
1746 // => 4~7: 4K
1747 // => 8~11:8K
1748 switch (u8Tdi+u8Mode*4)
1749 {
1750 case 0:
1751 *peIsdbtTDI = E_ISDBT_2K_TDI_0;
1752 break;
1753 case 1:
1754 *peIsdbtTDI = E_ISDBT_2K_TDI_4;
1755 break;
1756 case 2:
1757 *peIsdbtTDI = E_ISDBT_2K_TDI_8;
1758 break;
1759 case 3:
1760 *peIsdbtTDI = E_ISDBT_2K_TDI_16;
1761 break;
1762 case 4:
1763 *peIsdbtTDI = E_ISDBT_4K_TDI_0;
1764 break;
1765 case 5:
1766 *peIsdbtTDI = E_ISDBT_4K_TDI_2;
1767 break;
1768 case 6:
1769 *peIsdbtTDI = E_ISDBT_4K_TDI_4;
1770 break;
1771 case 7:
1772 *peIsdbtTDI = E_ISDBT_4K_TDI_8;
1773 break;
1774 case 8:
1775 *peIsdbtTDI = E_ISDBT_8K_TDI_0;
1776 break;
1777 case 9:
1778 *peIsdbtTDI = E_ISDBT_8K_TDI_1;
1779 break;
1780 case 10:
1781 *peIsdbtTDI = E_ISDBT_8K_TDI_2;
1782 break;
1783 case 11:
1784 *peIsdbtTDI = E_ISDBT_8K_TDI_4;
1785 break;
1786 default:
1787 *peIsdbtTDI = E_ISDBT_TDI_INVALID;
1788 break;
1789 }
1790
1791 return bRet;
1792 }
1793
_HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL * peIsdbtFFT)1794 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL *peIsdbtFFT)
1795 {
1796 MS_BOOL bRet = TRUE;
1797 MS_U8 u8Data = 0;
1798 MS_U8 u8Mode = 0;
1799
1800 // [5:4] reg_mcd_out_mode
1801 // output mode -> 00: 2k
1802 // 01: 4k
1803 // 10: 8k
1804 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
1805
1806 u8Mode = (u8Data >> 4) & 0x03;
1807
1808 switch (u8Mode)
1809 {
1810 case 0:
1811 *peIsdbtFFT = E_ISDBT_FFT_2K;
1812 break;
1813 case 1:
1814 *peIsdbtFFT = E_ISDBT_FFT_4K;
1815 break;
1816 case 2:
1817 *peIsdbtFFT = E_ISDBT_FFT_8K;
1818 break;
1819 default:
1820 *peIsdbtFFT = E_ISDBT_FFT_INVALID;
1821 break;
1822 }
1823
1824 return bRet;
1825 }
1826
_HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CONSTEL_TYPE * peIsdbtConstellation)1827 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CONSTEL_TYPE *peIsdbtConstellation)
1828 {
1829 MS_BOOL bRet = TRUE;
1830 MS_U8 u8Data = 0;
1831 MS_U8 u8QAM = 0;
1832
1833 switch(eLayerIndex)
1834 {
1835 case E_ISDBT_Layer_A:
1836 // [6:4] reg_tmcc_cur_carrier_modulation_a
1837 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2, &u8Data);
1838 u8QAM = (u8Data >> 4) & 0x07;
1839 break;
1840 case E_ISDBT_Layer_B:
1841 // [6:4] reg_tmcc_cur_carrier_modulation_b
1842 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2, &u8Data);
1843 u8QAM = (u8Data >> 4) & 0x07;
1844 break;
1845 case E_ISDBT_Layer_C:
1846 // [6:4] reg_tmcc_cur_carrier_modulation_c
1847 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2, &u8Data);
1848 u8QAM = (u8Data >> 4) & 0x07;
1849 break;
1850 default:
1851 u8QAM = 15;
1852 break;
1853 }
1854
1855 switch(u8QAM)
1856 {
1857 case 0:
1858 *peIsdbtConstellation = E_ISDBT_DQPSK;
1859 break;
1860 case 1:
1861 *peIsdbtConstellation = E_ISDBT_QPSK;
1862 break;
1863 case 2:
1864 *peIsdbtConstellation = E_ISDBT_16QAM;
1865 break;
1866 case 3:
1867 *peIsdbtConstellation = E_ISDBT_64QAM;
1868 break;
1869 default:
1870 *peIsdbtConstellation = E_ISDBT_QAM_INVALID;
1871 break;
1872 }
1873
1874 return bRet;
1875 }
1876
_HAL_INTERN_ISDBT_ReadIFAGC(void)1877 static MS_U8 _HAL_INTERN_ISDBT_ReadIFAGC(void)
1878 {
1879 MS_U8 data = 0;
1880
1881 _MBX_ReadReg(0x28FD, &data);
1882
1883 return data;
1884 }
1885
1886 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 * pFFT_Mode,MS_S32 * pTdCfoRegValue,MS_S32 * pFdCfoRegValue,MS_S16 * pIcfoRegValue)1887 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 *pFFT_Mode, MS_S32 *pTdCfoRegValue, MS_S32 *pFdCfoRegValue, MS_S16 *pIcfoRegValue)
1888 #else
1889 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(float *pFreqOff)
1890 #endif
1891 {
1892 MS_BOOL bRet = TRUE;
1893 MS_U8 u8Data = 0;
1894 MS_S32 s32TdCfoRegValue = 0;
1895 MS_S32 s32FdCfoRegValue = 0;
1896 MS_S16 s16IcfoRegValue = 0;
1897 #ifndef UTPA2
1898 float fTdCfoFreq = 0.0;
1899 float fICfoFreq = 0.0;
1900 float fFdCfoFreq = 0.0;
1901 #endif
1902
1903 //Get TD CFO
1904 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
1905 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data|0x01));
1906
1907 //read td_freq_error
1908 //Read <29,38>
1909 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8A, &u8Data); //0x45 * 2
1910 s32TdCfoRegValue = u8Data;
1911 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8B, &u8Data); //0x45 * 2 + 1
1912 s32TdCfoRegValue |= u8Data << 8;
1913 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8C, &u8Data); //0x46 * 2
1914 s32TdCfoRegValue = u8Data << 16;
1915 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8D, &u8Data); //0x46 * 2 + 1
1916 s32TdCfoRegValue |= u8Data << 24;
1917
1918 if (u8Data >= 0x10)
1919 s32TdCfoRegValue = 0xE0000000 | s32TdCfoRegValue;
1920
1921 s32TdCfoRegValue >>=4;
1922
1923 //TD_cfo_Hz = RegCfoTd * fb
1924 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
1925 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data&~0x01));
1926
1927 #ifndef UTPA2
1928 fTdCfoFreq = ((float)s32TdCfoRegValue) / 17179869184.0; //<25,34>
1929 fTdCfoFreq = fTdCfoFreq * 8126980.0;
1930 #endif
1931
1932 //Get FD CFO
1933 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
1934 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
1935 //load
1936 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
1937 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
1938
1939 //read CFO_KI
1940 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5E, &u8Data); //0x2F * 2
1941 s32FdCfoRegValue = u8Data;
1942 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5F, &u8Data); //0x2F * 2 + 1
1943 s32FdCfoRegValue |= u8Data << 8;
1944 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x60, &u8Data); //0x30 * 2
1945 s32FdCfoRegValue |= u8Data << 16;
1946 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x61, &u8Data); //0x30 * 2
1947 s32FdCfoRegValue |= u8Data << 24;
1948
1949 if(u8Data >= 0x01)
1950 s32FdCfoRegValue = 0xFE000000 | s32FdCfoRegValue;
1951
1952 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
1953 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
1954 //load
1955 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
1956 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
1957
1958 #ifndef UTPA2
1959 fFdCfoFreq = ((float)s32FdCfoRegValue) / 17179869184.0;
1960 fFdCfoFreq = fFdCfoFreq * 8126980.0;
1961 #endif
1962
1963 //Get ICFO
1964 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5C, &u8Data); //0x2E * 2
1965 s16IcfoRegValue = u8Data;
1966 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5D, &u8Data); //0x2E * 2 + 1
1967 s16IcfoRegValue |= u8Data << 8;
1968 s16IcfoRegValue = (s16IcfoRegValue >> 4) & 0x07FF;
1969
1970 if(s16IcfoRegValue >= 0x400)
1971 s16IcfoRegValue = s16IcfoRegValue | 0xFFFFF800;
1972
1973 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x68, &u8Data); //0x34 * 2
1974
1975 #ifdef UTPA2
1976 *pFFT_Mode = u8Data;
1977 *pTdCfoRegValue = s32TdCfoRegValue;
1978 *pFdCfoRegValue = s32TdCfoRegValue;
1979 *pIcfoRegValue = s16IcfoRegValue;
1980 #else
1981 if((u8Data & 0x30) == 0x0000) // 2k
1982 fICfoFreq = (float)s16IcfoRegValue*250000.0/63.0;
1983 else if((u8Data & 0x0030) == 0x0010) // 4k
1984 fICfoFreq = (float)s16IcfoRegValue*125000.0/63.0;
1985 else //if(u16data & 0x0030 == 0x0020) // 8k
1986 fICfoFreq = (float)s16IcfoRegValue*125000.0/126.0;
1987
1988 *pFreqOff = fTdCfoFreq + fFdCfoFreq + fICfoFreq;
1989
1990 HAL_INTERN_ISDBT_DBINFO(printf("Total CFO value = %f\n", *pFreqOff));
1991 #endif
1992
1993 return bRet;
1994 }
1995
1996 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)1997 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
1998 #else
1999 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
2000 #endif
2001 {
2002 MS_BOOL bRet = TRUE;
2003 MS_U8 u8Data = 0;
2004 MS_U16 u16BerValue = 0;
2005 MS_U32 u32BerPeriod = 0;
2006
2007 // reg_rd_freezeber
2008 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
2009 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, u8Data|0x08);
2010
2011 if (eLayerIndex == E_ISDBT_Layer_A)
2012 {
2013 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x90, &u8Data); //0x48 * 2
2014 u16BerValue=u8Data;
2015 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x91, &u8Data); //0x48 * 2+1
2016 u16BerValue |= (u8Data << 8);
2017 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x76, &u8Data); //0x3b * 2
2018 u32BerPeriod = (u8Data&0x3F);
2019 u32BerPeriod <<= 16;
2020 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2
2021 u32BerPeriod |= u8Data;
2022 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2 +1
2023 u32BerPeriod |= (u8Data << 8);
2024 }
2025 else if (eLayerIndex == E_ISDBT_Layer_B)
2026 {
2027 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x92, &u8Data); //0x49 * 2
2028 u16BerValue=u8Data;
2029 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x93, &u8Data); //0x49 * 2+1
2030 u16BerValue |= (u8Data << 8);
2031 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x77, &u8Data); //0x3b * 2 + 1
2032 u32BerPeriod = (u8Data&0x3F);
2033 u32BerPeriod <<= 16;
2034 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x72, &u8Data); //0x39 * 2
2035 u32BerPeriod |= u8Data;
2036 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x73, &u8Data); //0x39 * 2 +1
2037 u32BerPeriod |= (u8Data << 8);
2038 }
2039 else if (eLayerIndex == E_ISDBT_Layer_C)
2040 {
2041 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x94, &u8Data); //0x4A * 2
2042 u16BerValue=u8Data;
2043 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x95, &u8Data); //0x4A * 2+1
2044 u16BerValue |= (u8Data << 8);
2045 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x78, &u8Data); //0x3C
2046 u32BerPeriod = (u8Data&0x003F);
2047 u32BerPeriod <<= 16;
2048 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x74, &u8Data); //0x3A * 2
2049 u32BerPeriod |= u8Data;
2050 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x75, &u8Data); //0x3A * 2 +1
2051 u32BerPeriod |= (u8Data << 8);
2052 }
2053 else
2054 {
2055 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
2056 bRet = FALSE;
2057 }
2058
2059 // reg_rd_freezeber
2060 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
2061 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, (u8Data&~0x08));
2062
2063 u32BerPeriod <<= 8; // *256
2064
2065 if(u32BerPeriod == 0) u32BerPeriod = 1;
2066
2067 #ifdef UTPA2
2068 *pBerPeriod = u32BerPeriod;
2069 *pBerValue = u16BerValue;
2070 #else
2071 *pfber = (float)u16BerValue/u32BerPeriod;
2072 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Pre-Ber = %e\n", eLayerIndex, *pfber));
2073 #endif
2074
2075 return bRet;
2076 }
2077
2078 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)2079 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
2080 #else
2081 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
2082 #endif
2083 {
2084 MS_BOOL bRet = TRUE;
2085 MS_U8 u8Data = 0;
2086 MS_U8 u8FrzData = 0;
2087 MS_U32 u32BerValue = 0;
2088 MS_U16 u16BerPeriod = 0;
2089
2090 // reg_rd_freezeber
2091 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2092 u8Data = u8FrzData | 0x01;
2093 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2094
2095 if (eLayerIndex == E_ISDBT_Layer_A)
2096 {
2097 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x14, &u8Data); //0x0A * 2
2098 u32BerValue = u8Data;
2099 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x15, &u8Data); //0x0A * 2+1
2100 u32BerValue |= u8Data << 8;
2101 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x16, &u8Data); //0x0B * 2
2102 u32BerValue |= u8Data << 16;
2103 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x17, &u8Data); //0x0B * 2+1
2104 u32BerValue |= u8Data << 24;
2105
2106 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0A, &u8Data); //0x05 * 2
2107 u16BerPeriod = u8Data;
2108 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0B, &u8Data); //0x05 * 2+1
2109 u16BerPeriod |= u8Data << 8;
2110 }
2111 else if (eLayerIndex == E_ISDBT_Layer_B)
2112 {
2113 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x46, &u8Data); //0x23 * 2
2114 u32BerValue = u8Data;
2115 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x47, &u8Data); //0x23 * 2+1
2116 u32BerValue |= u8Data << 8;
2117 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x48, &u8Data); //0x24 * 2
2118 u32BerValue |= u8Data << 16;
2119 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x49, &u8Data); //0x24 * 2+1
2120 u32BerValue |= u8Data << 24;
2121
2122 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3A, &u8Data); //0x1d * 2
2123 u16BerPeriod = u8Data;
2124 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3B, &u8Data); //0x1d * 2+1
2125 u16BerPeriod |= u8Data << 8;
2126 }
2127 else if (eLayerIndex == E_ISDBT_Layer_C)
2128 {
2129 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x88, &u8Data); //0x44 * 2
2130 u32BerValue = u8Data;
2131 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x89, &u8Data); //0x44 * 2+1
2132 u32BerValue |= u8Data << 8;
2133 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8A, &u8Data); //0x45 * 2
2134 u32BerValue |= u8Data << 16;
2135 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8B, &u8Data); //0x45 * 2+1
2136 u32BerValue |= u8Data << 24;
2137
2138 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3E, &u8Data); //0x1f * 2
2139 u16BerPeriod = u8Data;
2140 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3F, &u8Data); //0x1d * 2+1
2141 u16BerPeriod |= u8Data << 8;
2142 }
2143 else
2144 {
2145 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
2146 bRet = FALSE;
2147 }
2148
2149 // reg_rd_freezeber
2150 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2151
2152 if(u16BerPeriod == 0) u16BerPeriod = 1;
2153
2154 #ifdef UTPA2
2155 *pBerPeriod = u16BerPeriod;
2156 *pBerValue = u32BerValue;
2157 #else
2158 *pfber = (float)u32BerValue/u16BerPeriod/(128.0*188.0*8.0);
2159 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Post-Ber = %e\n", eLayerIndex, *pfber));
2160 #endif
2161 return bRet;
2162 }
2163
2164 #ifndef UTPA2
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)2165 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)
2166 {
2167 float fber;
2168 MS_BOOL bRet = TRUE;
2169 EN_ISDBT_Layer eLayerIndex;
2170 MS_U16 u16SQI;
2171
2172 // Tmp solution
2173 eLayerIndex = E_ISDBT_Layer_A;
2174
2175 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2176 {
2177 //printf("Dan Demod unlock!!!\n");
2178 u16SQI = 0;
2179 }
2180 else
2181 {
2182 // Part 1: get ber value from demod.
2183 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2184
2185 u16SQI = _CALCULATE_SQI(fber);
2186 }
2187
2188 //printf("dan SQI = %d\n", SQI);
2189 return u16SQI;
2190 }
2191
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)2192 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)
2193 {
2194 float fber;
2195 MS_BOOL bRet = TRUE;
2196 EN_ISDBT_Layer eLayerIndex;
2197 MS_U16 u16SQI;
2198
2199 // Tmp solution
2200 eLayerIndex = E_ISDBT_Layer_B;
2201
2202 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2203 {
2204 //printf("Dan Demod unlock!!!\n");
2205 u16SQI = 0;
2206 }
2207 else
2208 {
2209 // Part 1: get ber value from demod.
2210 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2211
2212 u16SQI = _CALCULATE_SQI(fber);
2213 }
2214
2215 //printf("dan SQI = %d\n", SQI);
2216 return u16SQI;
2217 }
2218
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)2219 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)
2220 {
2221 float fber;
2222 MS_BOOL bRet = TRUE;
2223 EN_ISDBT_Layer eLayerIndex;
2224 MS_U16 u16SQI;
2225
2226 // Tmp solution
2227 eLayerIndex = E_ISDBT_Layer_C;
2228
2229 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2230 {
2231 //printf("Dan Demod unlock!!!\n");
2232 u16SQI = 0;
2233 }
2234 else
2235 {
2236 // Part 1: get ber value from demod.
2237 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2238
2239 u16SQI = _CALCULATE_SQI(fber);
2240 }
2241
2242 //printf("dan SQI = %d\n", SQI);
2243 return u16SQI;
2244 }
2245
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)2246 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)
2247 {
2248 MS_S8 s8LayerAValue = 0, s8LayerBValue = 0, s8LayerCValue = 0;
2249 MS_U16 u16SQI;
2250 EN_ISDBT_Layer eLayerIndex;
2251 EN_ISDBT_CONSTEL_TYPE eIsdbtConstellationA, eIsdbtConstellationB, eIsdbtConstellationC;
2252
2253 //Get modulation of each layer
2254 eLayerIndex = E_ISDBT_Layer_A;
2255 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationA);
2256 eLayerIndex = E_ISDBT_Layer_B;
2257 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationB);
2258 eLayerIndex = E_ISDBT_Layer_C;
2259 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationC);
2260
2261 if (eIsdbtConstellationA != E_ISDBT_QAM_INVALID)
2262 s8LayerAValue = (MS_S8)eIsdbtConstellationA;
2263 else
2264 s8LayerAValue = -1;
2265
2266 if (eIsdbtConstellationB != E_ISDBT_QAM_INVALID)
2267 s8LayerBValue = (MS_S8)eIsdbtConstellationB;
2268 else
2269 s8LayerBValue = -1;
2270
2271 if (eIsdbtConstellationC != E_ISDBT_QAM_INVALID)
2272 s8LayerCValue = (MS_S8)eIsdbtConstellationC;
2273 else
2274 s8LayerCValue = -1;
2275
2276 //printf("Layer info A:%d, B:%d, C:%d\n", s8LayerAValue, s8LayerBValue, s8LayerCValue);
2277 if (s8LayerAValue >= s8LayerBValue)
2278 {
2279 if (s8LayerCValue >= s8LayerAValue)
2280 {
2281 //Get Layer C u16SQI
2282 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2283 //printf("dan u16SQI Layer C1: %d\n", u16SQI);
2284 }
2285 else //A>C
2286 {
2287 //Get Layer A u16SQI
2288 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2289 //printf("dan u16SQI Layer A: %d\n", u16SQI);
2290 }
2291 }
2292 else // B >= A
2293 {
2294 if (s8LayerCValue >= s8LayerBValue)
2295 {
2296 //Get Layer C u16SQI
2297 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2298 //printf("dan u16SQI Layer C2: %d\n", u16SQI);
2299 }
2300 else //B>C
2301 {
2302 //Get Layer B u16SQI
2303 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2304 //printf("dan u16SQI Layer B: %d\n", u16SQI);
2305 }
2306 }
2307
2308 return u16SQI;
2309 }
2310 #endif
2311
2312 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetSNR(MS_U32 * pRegSNR,MS_U16 * pRegSnrObsNum)2313 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(MS_U32 *pRegSNR, MS_U16 *pRegSnrObsNum)
2314 #else
2315 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(float *pf_snr)
2316 #endif
2317 {
2318 MS_BOOL bRet = TRUE;
2319 MS_U8 u8Data = 0;
2320 MS_U32 u32RegSNR = 0;
2321 MS_U16 u16RegSnrObsNum = 0;
2322 #ifndef UTPA2
2323 float fSNRAvg = 0.0;
2324 #endif
2325
2326 //set freeze
2327 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2328 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
2329 //load
2330 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2331 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2332
2333 // ==============Average SNR===============//
2334 // [26:0] reg_snr_accu
2335 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2+1, &u8Data);
2336 u32RegSNR = u8Data&0x07;
2337 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2, &u8Data);
2338 u32RegSNR = (u32RegSNR<<8) | u8Data;
2339 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2+1, &u8Data);
2340 u32RegSNR = (u32RegSNR<<8) | u8Data;
2341 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2, &u8Data);
2342 u32RegSNR = (u32RegSNR<<8) | u8Data;
2343
2344 // [12:0] reg_snr_observe_sum_num
2345 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2+1, &u8Data);
2346 u16RegSnrObsNum = u8Data&0x1f;
2347 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2, &u8Data);
2348 u16RegSnrObsNum = (u16RegSnrObsNum<<8) | u8Data;
2349
2350 //release freeze
2351 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2352 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
2353 //load
2354 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2355 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2356
2357 if (u16RegSnrObsNum == 0)
2358 u16RegSnrObsNum = 1;
2359
2360
2361 #ifdef UTPA2
2362 *pRegSNR = u32RegSNR;
2363 *pRegSnrObsNum = u16RegSnrObsNum;
2364 #else
2365 fSNRAvg = (float)u32RegSNR/u16RegSnrObsNum;
2366 if (fSNRAvg == 0) //protect value 0
2367 fSNRAvg = 0.01;
2368
2369 #ifdef MSOS_TYPE_LINUX
2370 *pf_snr = 10.0f*(float)log10f((double)fSNRAvg/2);
2371 #else
2372 *pf_snr = 10.0f*(float)Log10Approx((double)fSNRAvg/2);
2373 #endif
2374 HAL_INTERN_ISDBT_DBINFO(printf("SNR value = %f\n", *pf_snr));
2375 #endif
2376
2377 return bRet;
2378 }
2379
_HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex,MS_U16 * pu16PacketErr)2380 static MS_BOOL _HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex, MS_U16 *pu16PacketErr)
2381 {
2382 MS_U8 bRet = true;
2383 MS_U8 u8Data = 0;
2384 MS_U8 u8FrzData = 0;
2385 MS_U16 u16PacketErrA = 0xFFFF, u16PacketErrB = 0xFFFF, u16PacketErrC = 0xFFFF;
2386 #if DMD_ISDBT_TBVA_EN
2387 MS_U8 bTbvaBypass = 0;
2388 MS_U8 u8TbvaLayer = 0;
2389 #endif
2390 // Read packet errors of three layers
2391 // OUTER_FUNCTION_ENABLE
2392 // [8] reg_biterr_num_pcktprd_freeze
2393 // Freeze Packet error
2394 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2395 u8Data = u8FrzData | 0x01;
2396 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2397 #if DMD_ISDBT_TBVA_EN
2398 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x10*2, &u8Data);
2399 bTbvaBypass = u8Data & 0x01;
2400 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x11*2, &u8Data);
2401 u8TbvaLayer = u8Data & 0x03;
2402 switch(eLayerIndex)
2403 {
2404 case E_ISDBT_Layer_A:
2405 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2406 if (!bTbvaBypass && u8TbvaLayer == 0)
2407 {
2408 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2409 u16PacketErrA = u8Data << 8;
2410 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2411 u16PacketErrA = u16PacketErrA | u8Data;
2412 *pu16PacketErr = u16PacketErrA;
2413 }
2414 else
2415 {
2416 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2417 u16PacketErrA = u8Data << 8;
2418 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2419 u16PacketErrA = u16PacketErrA | u8Data;
2420 *pu16PacketErr = u16PacketErrA;
2421 }
2422 break;
2423 case E_ISDBT_Layer_B:
2424 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2425 if (!bTbvaBypass && u8TbvaLayer == 1)
2426 {
2427 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2428 u16PacketErrB = u8Data << 8;
2429 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2430 u16PacketErrB = u16PacketErrB | u8Data;
2431 *pu16PacketErr = u16PacketErrB;
2432 }
2433 else
2434 {
2435 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2436 u16PacketErrB = u8Data << 8;
2437 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2438 u16PacketErrB = u16PacketErrB | u8Data;
2439 *pu16PacketErr = u16PacketErrB;
2440 }
2441 break;
2442 case E_ISDBT_Layer_C:
2443 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2444 if (!bTbvaBypass && u8TbvaLayer == 2)
2445 {
2446 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2447 u16PacketErrC = u8Data << 8;
2448 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2449 u16PacketErrC = u16PacketErrC | u8Data;
2450 *pu16PacketErr = u16PacketErrC;
2451 }
2452 else
2453 {
2454 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2455 u16PacketErrC = u8Data << 8;
2456 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2457 u16PacketErrC = u16PacketErrC | u8Data;
2458 *pu16PacketErr = u16PacketErrC;
2459 }
2460 break;
2461 default:
2462 *pu16PacketErr = 0xFFFF;
2463 break;
2464 }
2465 #else
2466 switch(eLayerIndex)
2467 {
2468 case E_ISDBT_Layer_A:
2469 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2470 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2471 u16PacketErrA = u8Data << 8;
2472 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2473 u16PacketErrA = u16PacketErrA | u8Data;
2474 *pu16PacketErr = u16PacketErrA;
2475 break;
2476 case E_ISDBT_Layer_B:
2477 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2478 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2479 u16PacketErrB = u8Data << 8;
2480 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2481 u16PacketErrB = u16PacketErrB | u8Data;
2482 *pu16PacketErr = u16PacketErrB;
2483 break;
2484 case E_ISDBT_Layer_C:
2485 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2486 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2487 u16PacketErrC = u8Data << 8;
2488 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2489 u16PacketErrC = u16PacketErrC | u8Data;
2490 *pu16PacketErr = u16PacketErrC;
2491 break;
2492 default:
2493 *pu16PacketErr = 0xFFFF;
2494 break;
2495 }
2496 #endif
2497 // Unfreeze Packet error
2498 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2499
2500 return bRet;
2501 }
2502
_HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)2503 static MS_BOOL _HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
2504 {
2505 return _MBX_ReadReg(u16Addr, pu8Data);
2506 }
2507
_HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr,MS_U8 u8Data)2508 static MS_BOOL _HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
2509 {
2510 return _MBX_WriteReg(u16Addr, u8Data);
2511 }
2512
2513 //-------------------------------------------------------------------------------------------------
2514 // Global Functions
2515 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd,void * pArgs)2516 MS_BOOL HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd, void *pArgs)
2517 {
2518 MS_BOOL bResult = TRUE;
2519
2520 switch(eCmd)
2521 {
2522 case DMD_ISDBT_HAL_CMD_Exit:
2523 bResult = _HAL_INTERN_ISDBT_Exit();
2524 break;
2525 case DMD_ISDBT_HAL_CMD_InitClk:
2526 _HAL_INTERN_ISDBT_InitClk();
2527 break;
2528 case DMD_ISDBT_HAL_CMD_Download:
2529 bResult = _HAL_INTERN_ISDBT_Download();
2530 break;
2531 case DMD_ISDBT_HAL_CMD_FWVERSION:
2532 _HAL_INTERN_ISDBT_FWVERSION();
2533 break;
2534 case DMD_ISDBT_HAL_CMD_SoftReset:
2535 bResult = _HAL_INTERN_ISDBT_SoftReset();
2536 break;
2537 case DMD_ISDBT_HAL_CMD_SetACICoef:
2538 bResult = _HAL_INTERN_ISDBT_SetACICoef();
2539 break;
2540 case DMD_ISDBT_HAL_CMD_SetISDBTMode:
2541 bResult = _HAL_INTERN_ISDBT_SetIsdbtMode();
2542 break;
2543 case DMD_ISDBT_HAL_CMD_SetModeClean:
2544 bResult = _HAL_INTERN_ISDBT_SetModeClean();
2545 break;
2546 case DMD_ISDBT_HAL_CMD_Active:
2547 break;
2548 case DMD_ISDBT_HAL_CMD_Check_FEC_Lock:
2549 bResult = _HAL_INTERN_ISDBT_Check_FEC_Lock();
2550 break;
2551 case DMD_ISDBT_HAL_CMD_Check_FSA_TRACK_Lock:
2552 bResult = _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock();
2553 break;
2554 case DMD_ISDBT_HAL_CMD_Check_PSYNC_Lock:
2555 bResult = _HAL_INTERN_ISDBT_Check_PSYNC_Lock();
2556 break;
2557 case DMD_ISDBT_HAL_CMD_Check_ICFO_CH_EXIST_Lock:
2558 bResult = _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock();
2559 break;
2560 case DMD_ISDBT_HAL_CMD_GetSignalCodeRate:
2561 bResult = _HAL_INTERN_ISDBT_GetSignalCodeRate((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eCodeRate));
2562 break;
2563 case DMD_ISDBT_HAL_CMD_GetSignalGuardInterval:
2564 bResult = _HAL_INTERN_ISDBT_GetSignalGuardInterval((EN_ISDBT_GUARD_INTERVAL *)pArgs);
2565 break;
2566 case DMD_ISDBT_HAL_CMD_GetSignalTimeInterleaving:
2567 bResult = _HAL_INTERN_ISDBT_GetSignalTimeInterleaving((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eTimeInterleaving));
2568 break;
2569 case DMD_ISDBT_HAL_CMD_GetSignalFFTValue:
2570 bResult = _HAL_INTERN_ISDBT_GetSignalFFTValue((EN_ISDBT_FFT_VAL *)pArgs);
2571 break;
2572 case DMD_ISDBT_HAL_CMD_GetSignalModulation:
2573 bResult = _HAL_INTERN_ISDBT_GetSignalModulation((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eConstellation));
2574 break;
2575 case DMD_ISDBT_HAL_CMD_ReadIFAGC:
2576 *((MS_U16 *)pArgs) = _HAL_INTERN_ISDBT_ReadIFAGC();
2577 break;
2578 case DMD_ISDBT_HAL_CMD_GetFreqOffset:
2579 #ifdef UTPA2
2580 bResult = _HAL_INTERN_ISDBT_GetFreqOffset(&((*((DMD_ISDBT_CFO_DATA*)pArgs)).FFT_Mode), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).TdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).FdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).IcfoRegValue));
2581 #else
2582 bResult = _HAL_INTERN_ISDBT_GetFreqOffset((float *)pArgs);
2583 #endif
2584 break;
2585 case DMD_ISDBT_HAL_CMD_GetSignalQuality:
2586 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerA:
2587 #ifndef UTPA2
2588 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2589 #endif
2590 break;
2591 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerB:
2592 #ifndef UTPA2
2593 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2594 #endif
2595 break;
2596 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerC:
2597 #ifndef UTPA2
2598 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2599 #endif
2600 break;
2601 case DMD_ISDBT_HAL_CMD_GetSignalQualityCombine:
2602 #ifndef UTPA2
2603 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine();
2604 #endif
2605 break;
2606 case DMD_ISDBT_HAL_CMD_GetSNR:
2607 #ifdef UTPA2
2608 bResult = _HAL_INTERN_ISDBT_GetSNR(&((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSNR), &((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSnrObsNum));
2609 #else
2610 bResult = _HAL_INTERN_ISDBT_GetSNR((float *)pArgs);
2611 #endif
2612 break;
2613 case DMD_ISDBT_HAL_CMD_GetPreViterbiBer:
2614 #ifdef UTPA2
2615 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2616 #else
2617 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2618 #endif
2619 break;
2620 case DMD_ISDBT_HAL_CMD_GetPostViterbiBer:
2621 #ifdef UTPA2
2622 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2623 #else
2624 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2625 #endif
2626 break;
2627 case DMD_ISDBT_HAL_CMD_Read_PKT_ERR:
2628 bResult = _HAL_INTERN_ISDBT_Read_PKT_ERR((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).u16PacketErr));
2629 break;
2630 case DMD_ISDBT_HAL_CMD_TS_INTERFACE_CONFIG:
2631 break;
2632 case DMD_ISDBT_HAL_CMD_IIC_Bypass_Mode:
2633 break;
2634 case DMD_ISDBT_HAL_CMD_SSPI_TO_GPIO:
2635 break;
2636 case DMD_ISDBT_HAL_CMD_GPIO_GET_LEVEL:
2637 break;
2638 case DMD_ISDBT_HAL_CMD_GPIO_SET_LEVEL:
2639 break;
2640 case DMD_ISDBT_HAL_CMD_GPIO_OUT_ENABLE:
2641 break;
2642 case DMD_ISDBT_HAL_CMD_GET_REG:
2643 bResult = _HAL_INTERN_ISDBT_GetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data));
2644 break;
2645 case DMD_ISDBT_HAL_CMD_SET_REG:
2646 bResult = _HAL_INTERN_ISDBT_SetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, (*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data);
2647 break;
2648 default:
2649 break;
2650 }
2651
2652 return bResult;
2653 }
2654
MDrv_DMD_ISDBT_Initial_Hal_Interface(void)2655 MS_BOOL MDrv_DMD_ISDBT_Initial_Hal_Interface(void)
2656 {
2657 return TRUE;
2658 }
2659
2660