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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvAVD.c
98 /// @brief AVD Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106 // Common Definition
107 #include <string.h>
108 #include "MsCommon.h"
109 #include "MsVersion.h"
110 #include "MsOS.h"
111
112 // Internal Definition
113 //#include "regCHIP.h"
114 //#include "regAVD.h"
115 //#include "mapi_tuner.h"
116 #include "drvSYS.h"
117 //#include "drvDMD_VD_MBX.h"
118 #include "drvDMD_EXTERN_MSB123xc.h"
119 #include "include/drvDMD_common.h"
120 #include "include/drvSAR.h"
121 //-------------------------------------------------------------------------------------------------
122 // Driver Compiler Options
123 //-------------------------------------------------------------------------------------------------
124 #ifdef MS_DEBUG
125 #define ERR_DOMOD_MSB(x) x
126 #define DBG_DOMOD_MSB(x) x
127 #define DBG_DOMOD_FLOW(x) x
128 #define DBG_GET_SIGNAL(x) // x
129 #define DBG_DEMOD_LOAD_I2C(x) x
130 #define DBG_DEMOD_CHECKSUM(x) // x
131 #define DBG_FLASH_WP(x) // x
132 #endif
133
134 //-------------------------------------------------------------------------------------------------
135 // Local Defines
136 //-------------------------------------------------------------------------------------------------
137 #define LOAD_CODE_I2C_BLOCK_NUM 0x80
138 #define REG_MB_CNTL 0x0C00
139 #define REG_MB_ADDR_L 0x0C02
140 #define REG_MB_ADDR_H 0x0C03
141 #define REG_MB_DATA 0x0C04
142
143 #define resetDemodTime 50
144 #define waitFlashTime 50
145
146 #define SDRAM_DATA_CHECK 0//1
147 #define SDRAM_BASE 0x5000
148 #define SDRAM_WINDOW_SIZE 0x1000
149 #define SPI_DEVICE_BUFFER_SIZE 256
150 #define MAX_MSB123xc_LIB_LEN 131072
151
152 #define MSB123xc_BOOT 0x01
153 #define MSB123xc_DVBT2 0x02
154 #define MSB123xc_DVBT 0x04
155 #define MSB123xc_DVBC 0x08
156 #define MSB123xc_ALL 0x0F
157
158 #define EDINBURGH_BOOT_START_ADDR 0x00000
159 #define EDINBURGH_BOOT_END_ADDR 0x00FFF
160 #define EDINBURGH_DVBT2_P1_START_ADDR 0x01000
161 #define EDINBURGH_DVBT2_P1_END_ADDR 0x08FFF
162 #define EDINBURGH_DVBT2_P2_START_ADDR 0x09000
163 #define EDINBURGH_DVBT2_P2_END_ADDR 0x0FFFF
164 #define EDINBURGH_DVBT_START_ADDR 0x10000
165 #define EDINBURGH_DVBT_END_ADDR 0x17FFF
166 #define EDINBURGH_DVBC_START_ADDR 0x18000
167 #define EDINBURGH_DVBC_END_ADDR 0x1FFFF
168
169 #define EDINBURGH_WINDOWS_BASE 0x100
170 #define EDINBURGH_BOOT_WINDOWS_OFFSET EDINBURGH_WINDOWS_BASE
171 #define EDINBURGH_DVBT2_P2_WINDOWS_OFFSET (EDINBURGH_WINDOWS_BASE + 0x08)
172 #define EDINBURGH_DVBT2_P1_WINDOWS_OFFSET (EDINBURGH_DVBT2_P2_WINDOWS_OFFSET + 0x08)
173 #define EDINBURGH_DVBT_WINDOWS_OFFSET (EDINBURGH_DVBT2_P1_WINDOWS_OFFSET + 0x08)
174 #define EDINBURGH_DVBC_WINDOWS_OFFSET (EDINBURGH_DVBT_WINDOWS_OFFSET + 0x08)
175
176 #define MSB123xc_MAX_FLASH_ON_RETRY_NUM 3
177
178
179 /////////////// CONSTANT /////////////////
180 #define PAGE_WRITE_SIZE 256
181 #define VERSION_CODE_ADDR 0xFC0
182 #define VERSION_CODE_SIZE 32
183 //-------------------------------------------------------------------------------------------------
184 // Local Structurs
185 //-------------------------------------------------------------------------------------------------
186
187 //-------------------------------------------------------------------------------------------------
188 // Global Variables
189 //-------------------------------------------------------------------------------------------------
190 #define DMD_LOCK() \
191 do{ \
192 MS_ASSERT(MsOS_In_Interrupt() == FALSE); \
193 if (eDMD_MSB123xc_DbgLevel == E_DMD_MSB123xc_DBGLV_DEBUG) printf("%s lock mutex\n", __FUNCTION__);\
194 MsOS_ObtainMutex(_s32DMD_Mutex, MSOS_WAIT_FOREVER);\
195 }while(0)
196
197 #define DMD_UNLOCK() \
198 do{ \
199 MsOS_ReleaseMutex(_s32DMD_Mutex);\
200 if (eDMD_MSB123xc_DbgLevel == E_DMD_MSB123xc_DBGLV_DEBUG) printf("%s unlock mutex\n", __FUNCTION__); \
201 }while(0)
202
203 //-------------------------------------------------------------------------------------------------
204 // Local Variables
205 //-------------------------------------------------------------------------------------------------
206 #if 1
207 static MSIF_Version _drv_dmd_msb123xc_extern_version =
208 {
209 .MW = { DMD_MSB123xc_EXTERN_VER, },
210 };
211 #else
212 static MSIF_Version _drv_dmd_msb123x_extern_version;
213 #endif
214 static MS_BOOL bDMD_MSB123xc_Power_init_en = FALSE;
215 static MS_U8 u8DMD_MSB123xc_PowerOnInitialization_Flow = 0;
216 static MS_U8 u8DMD_MSB123xc_Sdram_Code = 0x0;
217 static MS_U8 u8DMD_MSB123xc_Sram_Code = 0x0;
218 static sDMD_MSB123xc_InitData _sDMD_MSB123xc_InitData;
219 static eDMD_MSB123xc_DbgLv eDMD_MSB123xc_DbgLevel=E_DMD_MSB123xc_DBGLV_NONE;
220 static eDMD_MSB123xc_DemodulatorType eDMD_MSB123xc_CurrentDemodulatorType=E_DMD_MSB123xc_DEMOD_DVBT;
221 static MS_S32 _s32DMD_Mutex=-1;
222 static MS_BOOL bDemodRest = TRUE;
223
224 MS_U8 MSB123xc_LIB[]=
225 {
226 #include "msb123xc_dvbt.dat"
227 };
228 //--------------------------------------------------------------------- for DVB-T
229 //operation
230 #define RFAGC_EN 0x00
231 #define HUMDET_EN 0x00
232 #define DCR_EN 0x01
233 #define IIS_EN 0x01
234 #define CCI_EN 0x01
235 #define ACI_EN 0x01
236 #define IQB_EN 0x00
237 #define AUTO_IQ_SWAP 0x01
238 #define AUTO_RFMAX 0x00
239 #define AUTO_ACI 0x00
240 #define MODE_CP_FORCED 0x00
241 #define TPS_FORCED 0x00
242 #define AUTO_SCAN 0x00
243 #define RSV_0D 0x00
244 #define RSV_0E 0x00
245 #define RSV_0F 0x00
246
247 //configure
248 #define RSSI 0x00
249 #define ZIF 0x00
250 #define FREQ 0x00
251 #define FC_L 0x88
252 #define FC_H 0x13
253 #define FS_L 0x80
254 #define FS_H 0x70
255 #define BW 0x03
256 #define MODE 0x01
257 #define CP 0x03
258 #define LP_SEL 0x00
259 #define CSTL 0x00
260 #define HIER 0x00
261 #define HPCR 0x00
262 #define LPCR 0x00
263 #define IQ_SWAP 0x00
264 #define RFMAX 0x01
265 #define ATV_SYSTEM 0x01
266 #define ICFO_RANGE 0x01
267 #define RFAGC_REF 0x64
268 #define IFAGC_REF_2K 0x4B
269 #define IFAGC_REF_8K 0x4B
270 #define IFAGC_REF_ACI 0x4B
271 #define IFAGC_REF_IIS_2K 0xA0
272 #define IFAGC_REF_IIS_8K 0xA0
273 #define IFAGC_ACI_DET_TH_L 0x9A
274 #define IFAGC_ACI_DET_TH_H 0x01
275 #define SERIAL_TS 0x00
276 #define TS_CLK_SEL 0x06
277 #define TS_OUT_INV 0x01
278 #define TS_DATA_SWAP 0x00
279 #define SFO_2K_H 0x00
280 #define SFO_2K_L 0xC8
281 #define SFO_8K_H 0x00
282 #define SFO_8K_L 0xC8
283 #define CHECK_CHANNEL 0x00
284 #define SNR_POS 0x00
285 #define CCI_KP 0x00
286 #define CCI_FSWEEP 0x00
287 #define TS_CLK_RATE_AUTO 0x00
288 #define DVBT_IF_INV_PWM_OUT_EN 0x00
289 #define DVBT_CRC 0x00
290
291
292 MS_U8 MSB123xc_DVBT_DSPREG_TABLE[] = // andy 2009-12-15 3:55:03 TW model
293 {
294 RFAGC_EN, HUMDET_EN, DCR_EN, IIS_EN, CCI_EN, ACI_EN,
295 IQB_EN, AUTO_IQ_SWAP, AUTO_RFMAX, AUTO_ACI, MODE_CP_FORCED, TPS_FORCED,
296 AUTO_SCAN, RSV_0D, RSV_0E, RSV_0F,
297 RSSI, ZIF, FREQ, FC_L, FC_H, FS_L, FS_H,
298 BW, MODE, CP, LP_SEL, CSTL, HIER, HPCR,
299 LPCR, IQ_SWAP, RFMAX, ATV_SYSTEM, ICFO_RANGE, RFAGC_REF,
300 IFAGC_REF_2K, IFAGC_REF_8K, IFAGC_REF_ACI, IFAGC_REF_IIS_2K, IFAGC_REF_IIS_8K, IFAGC_ACI_DET_TH_L,
301 IFAGC_ACI_DET_TH_H, SERIAL_TS, TS_CLK_SEL, TS_OUT_INV, TS_DATA_SWAP,
302 SFO_2K_H, SFO_2K_L, SFO_8K_H, SFO_8K_L, CHECK_CHANNEL, SNR_POS,
303 CCI_KP, CCI_FSWEEP , TS_CLK_RATE_AUTO, DVBT_IF_INV_PWM_OUT_EN, DVBT_CRC
304 };
305
306 //--------------------------------------------------------------------- for DVB-C
307 #define SR0_H_AUTO 0x0F
308 #define SR0_L_AUTO 0xA0
309 #define SR0_H 0x1A
310 #define SR0_L 0xDB
311 /*
312 #define REAGC_EN 0x00 //0x20
313 #define HUMDET_EN_C 0x00
314 #define DCR_EN 0x01
315 #define IQB_EN 0x00
316 #define AUTO_IQ 0x01
317 #define AUTO_RFMAX 0x00
318 #define AUTO_ACI 0x01
319 */
320 #define AUTO_SCAN 0x00
321 #define AUTO_SCAN_SYM_RATE 0x00 //0x28
322 #define AUTO_SCAN_QAM 0x00
323 #define ATV_DET_EN 0x01 //0x2A
324 /*
325 #define RSV_0B 0x00
326 #define RSV_0C 0x00
327 #define RSV_0D 0x00
328 #define RSV_0E 0x00
329 #define RSV_0F 0x00
330 */
331 #define RSSI 0x00 //0x30
332 //#define ZIF 0x00
333 #define FREQ 0x00
334 //#define FC_L 0xE0
335 //#define FC_H 0x2E
336 //#define FS_L 0x80
337 //#define FS_H 0xBB
338 #define BW_L 0xDB
339 #define BW_H 0x1A
340 #define BW1_L 0xF4
341 #define BW1_H 0x1A
342 #define BW2_L 0xDB
343 #define BW2_H 0x1A
344 #define BW3_L 0xDB
345 #define BW3_H 0x1A
346 //#define RSV_0x1F 0x00
347 //#define RFMAX 0x00 //0x40
348 #define QAM 0x02
349 #define IQ_SWAP_C 0x01
350 #define CCI 0x00
351 #define SERIAL_TS 0x00 //0: parallel 1:serial
352 //#define TS_SERIAL_CLK 0x05
353 #define TS_OUT_INV 0x01 //
354 #define TS_DATA_SWAP 0x00
355
356 MS_U8 MSB123xc_DVBC_DSPREG_TABLE[] =
357 {
358 00, 00, 01, 00, 01, 00, 01, AUTO_SCAN,
359 AUTO_SCAN_SYM_RATE, AUTO_SCAN_QAM, ATV_DET_EN, 00, 00, 00, 00, 00,
360 00, 00, 00, FC_L, FC_H, FS_L, FS_H,
361 BW_L, BW_H, BW1_L, BW1_H, BW2_L, BW2_H, BW3_L, BW3_H, 00,
362 00, QAM, IQ_SWAP_C, CCI, SERIAL_TS, 05,
363 TS_OUT_INV, TS_DATA_SWAP
364 };
365
366 //configure
367 //--------------------------------------------------------------------- for DVB-T2
368 // BW: 0->1.7M, 1->5M, 2->6M, 3->7M, 4->8M, 5->10M
369 #define T2_BW_VAL 0x04
370
371 // FC: FC = FS = 4800 = 0x12C0 (4.80MHz IF)
372 #define T2_FC_L_VAL 0xC0 // 4.80M
373 #define T2_FC_H_VAL 0x12
374 #define T2_TS_SERIAL_VAL 0x00
375 #define T2_TS_CLK_RATE_VAL 0x06
376 #define T2_TS_OUT_INV_VAL 0x01
377 #define T2_TS_DATA_SWAP_VAL 0x00
378 #define T2_TS_ERR_POL_VAL 0x00
379
380 MS_U8 MSB123xc_DVBT2_DSPREG_TABLE[] =
381 {
382 T2_BW_VAL, T2_FC_L_VAL, T2_FC_H_VAL, T2_TS_SERIAL_VAL, T2_TS_CLK_RATE_VAL,
383 T2_TS_OUT_INV_VAL, T2_TS_DATA_SWAP_VAL, T2_TS_ERR_POL_VAL
384 };
385
386
387
388
389 //-------------------------------------------------------------------------------------------------
390 // Debug Functions
391 //-------------------------------------------------------------------------------------------------
392 #ifdef MS_DEBUG
393 #define DMD_DBG(x) (x)
394 #else
395 #define DMD_DBG(x) //(x)
396 #endif
397 //-------------------------------------------------------------------------------------------------
398 // Local Functions
399 //-------------------------------------------------------------------------------------------------
400
401
402 //-------------------------------------------------------------------------------------------------
403 // Global Functions
404 //-------------------------------------------------------------------------------------------------
MDrv_DMD_MSB123xc_Init(sDMD_MSB123xc_InitData * pDMD_MSB123xc_InitData,MS_U32 u32InitDataLen)405 MS_BOOL MDrv_DMD_MSB123xc_Init(sDMD_MSB123xc_InitData *pDMD_MSB123xc_InitData, MS_U32 u32InitDataLen)
406 {
407 //char pDMD_MSB123xc_MutexString[16], pDMD_MSB123xc_MutexString_RegRW[16], pDMD_MSB123xc_MutexString_DSPRegRW[16];
408 char pDMD_MSB123xc_MutexString[16];
409
410 if (_s32DMD_Mutex != -1)
411 {
412 DMD_DBG(printf("MDrv_DMD_MSB123xc_Init more than once\n"));
413 return FALSE;
414 }
415
416 if (NULL == strncpy(pDMD_MSB123xc_MutexString,"Mutex DMD DVB",16))
417 {
418 DMD_DBG(printf("MDrv_DMD_MSB123xc_Init strcpy Fail\n"));
419 return FALSE;
420 }
421 _s32DMD_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, pDMD_MSB123xc_MutexString, MSOS_PROCESS_SHARED);
422 if (_s32DMD_Mutex == -1)
423 {
424 DMD_DBG(printf("MDrv_DMD_MSB123xc_Init Create Mutex Fail\n"));
425 return FALSE;
426 }
427
428 DMD_LOCK();
429 if ( sizeof(_sDMD_MSB123xc_InitData) == u32InitDataLen)
430 {
431 memcpy(&_sDMD_MSB123xc_InitData, pDMD_MSB123xc_InitData, u32InitDataLen);
432 }
433 else
434 {
435 DMD_DBG(printf("MDrv_DMD_MSB123xc_Init input data structure incorrect\n"));
436 DMD_UNLOCK();
437 return FALSE;
438 }
439
440 if (_sDMD_MSB123xc_InitData.pDVBC_DSP_REG!= NULL)
441 {
442 printf("MDrv_DMD_MSB123xc_Init Init DVBC DSP Table By Device Driver ... \n");
443
444 memcpy (&MSB123xc_DVBC_DSPREG_TABLE[0],_sDMD_MSB123xc_InitData.pDVBC_DSP_REG ,sizeof(MSB123xc_DVBC_DSPREG_TABLE));
445 }
446 else
447 {
448 printf("MDrv_DMD_MSB123xc_Init Init DVBC DSP Table By Device Driver ... \n");
449 }
450
451 if (_sDMD_MSB123xc_InitData.pDVBT_DSP_REG!= NULL)
452 {
453 printf("MDrv_DMD_MSB123xc_Init Init DVBT DSP Table By Device Driver ... \n");
454
455 memcpy (&MSB123xc_DVBT_DSPREG_TABLE[0],_sDMD_MSB123xc_InitData.pDVBT_DSP_REG ,sizeof(MSB123xc_DVBT_DSPREG_TABLE));
456 }
457 else
458 {
459 printf("MDrv_DMD_MSB123xc_Init Init DVBT DSP Table By Device Driver ... \n");
460 }
461
462 if (_sDMD_MSB123xc_InitData.pDVBT2_DSP_REG!= NULL)
463 {
464 printf("MDrv_DMD_MSB123xc_Init Init DVBT2 DSP Table By Device Driver ... \n");
465
466 memcpy (&MSB123xc_DVBT2_DSPREG_TABLE[0],_sDMD_MSB123xc_InitData.pDVBT2_DSP_REG ,sizeof(MSB123xc_DVBT2_DSPREG_TABLE));
467 }
468 else
469 {
470 printf("MDrv_DMD_MSB123xc_Init Init DVBT2 DSP Table By Device Driver ... \n");
471 }
472
473 if (_sDMD_MSB123xc_InitData.bEnableSPILoadCode && _sDMD_MSB123xc_InitData.fpMSB123xc_SPIPAD_En != NULL)
474 {
475 if (!MDrv_DMD_SSPI_Init(0))
476 {
477 printf("MDrv_DMD_MSB123xc_Init Init MDrv_DMD_SSPI_Init Fail \n");
478 }
479 }
480 else
481 {
482 _sDMD_MSB123xc_InitData.bEnableSPILoadCode = FALSE;
483 }
484
485 //eDMD_MSB123xc_DbgLevel = E_DMD_MSB123xc_DBGLV_DEBUG;
486 #ifdef MS_DEBUG
487 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_INFO)
488 {
489 printf("MDrv_DMD_MSB123xc_Init\n");
490 }
491 #endif
492
493 DMD_UNLOCK();
494 return TRUE;
495 }
496
MDrv_DMD_MSB123xc_Exit(void)497 MS_BOOL MDrv_DMD_MSB123xc_Exit(void)
498 {
499 #ifdef MS_DEBUG
500 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
501 {
502 printf("MDrv_DMD_MSB123xc_Exit \n");
503 }
504 #endif
505
506 MsOS_DeleteMutex(_s32DMD_Mutex);
507 //MsOS_DeleteMutex(_s32DMD_Mutex_Reg_RW);
508 //MsOS_DeleteMutex(_s32DMD_Mutex_DSPReg_RW);
509 _s32DMD_Mutex= -1;
510 //_s32DMD_Mutex_Reg_RW= -1;
511 //_s32DMD_Mutex_DSPReg_RW= -1;
512
513 bDMD_MSB123xc_Power_init_en = FALSE;
514 u8DMD_MSB123xc_PowerOnInitialization_Flow = 0;
515 u8DMD_MSB123xc_Sdram_Code = 0x0;
516 u8DMD_MSB123xc_Sram_Code = 0x0;
517 bDemodRest = TRUE;
518
519 return TRUE;
520 }
521
MDrv_DMD_MSB123xc_SetDbgLevel(eDMD_MSB123xc_DbgLv u8DbgLevel)522 MS_BOOL MDrv_DMD_MSB123xc_SetDbgLevel(eDMD_MSB123xc_DbgLv u8DbgLevel)
523 {
524 DMD_LOCK();
525 eDMD_MSB123xc_DbgLevel = u8DbgLevel;
526 DMD_UNLOCK();
527 return TRUE;
528 }
529
530
MDrv_DMD_MSB123xc_GetLibVer(const MSIF_Version ** ppVersion)531 MS_BOOL MDrv_DMD_MSB123xc_GetLibVer(const MSIF_Version **ppVersion)
532 {
533 DMD_LOCK();
534 if (!ppVersion)
535 {
536 DMD_UNLOCK();
537 return FALSE;
538 }
539
540 *ppVersion = &_drv_dmd_msb123xc_extern_version;
541 DMD_UNLOCK();
542 return TRUE;
543 }
544
MDrv_DMD_MSB123xc_GetFWVer(MS_U16 * ver)545 MS_BOOL MDrv_DMD_MSB123xc_GetFWVer(MS_U16 *ver)
546 {
547
548 MS_BOOL bRet=TRUE;
549
550 DMD_LOCK();
551 //printf("MDrv_DMD_DVBT_GetFWVer %x\n",*ver);
552 DMD_UNLOCK();
553
554 return bRet;
555
556 }
557
_MDrv_DMD_MSB123xc_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)558 static MS_BOOL _MDrv_DMD_MSB123xc_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
559 {
560 MS_BOOL bRet=TRUE;
561 MS_U8 u8MsbData[6];
562
563 u8MsbData[0] = 0x10;
564 u8MsbData[1] = 0x00;
565 u8MsbData[2] = 0x00;
566 u8MsbData[3] = (u16Addr >> 8) &0xff;
567 u8MsbData[4] = u16Addr & 0xff;
568
569 u8MsbData[0] = 0x35;
570 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
571
572 u8MsbData[0] = 0x10;
573 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
574 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 0, NULL, 1, pu8Data);
575
576 u8MsbData[0] = 0x34;
577 bRet=(*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
578
579 #ifdef MS_DEBUG
580 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
581 {
582 printf("_MDrv_DMD_MSB123xc_GetReg %x %x\n", u16Addr, *pu8Data);
583 }
584 #endif
585
586 return bRet;
587 }
588
MDrv_DMD_MSB123xc_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)589 MS_BOOL MDrv_DMD_MSB123xc_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
590 {
591 MS_BOOL bRet=TRUE;
592
593 DMD_LOCK();
594 bRet = _MDrv_DMD_MSB123xc_GetReg(u16Addr, pu8Data);
595 DMD_UNLOCK();
596
597 return bRet;
598 }
599
_MDrv_DMD_MSB123xc_SetReg(MS_U16 u16Addr,MS_U8 u8Data)600 static MS_BOOL _MDrv_DMD_MSB123xc_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
601 {
602 MS_BOOL bRet=TRUE;
603 MS_U8 u8MsbData[6];
604
605 #ifdef MS_DEBUG
606 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
607 {
608 printf("_MDrv_DMD_MSB123xc_SetReg %x %x\n", u16Addr, u8Data);
609 }
610 #endif
611
612 u8MsbData[0] = 0x10;
613 u8MsbData[1] = 0x00;
614 u8MsbData[2] = 0x00;
615 u8MsbData[3] = (u16Addr >> 8) &0xff;
616 u8MsbData[4] = u16Addr &0xff;
617 u8MsbData[5] = u8Data;
618
619 u8MsbData[0] = 0x35;
620 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
621
622 u8MsbData[0] = 0x10;
623 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
624
625 u8MsbData[0] = 0x34;
626 bRet=(*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
627 return bRet;
628 }
629
MDrv_DMD_MSB123xc_SetReg(MS_U16 u16Addr,MS_U8 u8Data)630 MS_BOOL MDrv_DMD_MSB123xc_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
631 {
632 MS_BOOL bRet=TRUE;
633
634 DMD_LOCK();
635 bRet = _MDrv_DMD_MSB123xc_SetReg(u16Addr, u8Data);
636 DMD_UNLOCK();
637
638 return bRet;
639 }
640
641
_MDrv_DMD_MSB123xc_SetRegs(MS_U16 u16Addr,MS_U8 * u8pData,MS_U16 data_size)642 static MS_BOOL _MDrv_DMD_MSB123xc_SetRegs(MS_U16 u16Addr, MS_U8* u8pData, MS_U16 data_size)
643 {
644 MS_BOOL bRet=TRUE;
645 MS_U8 u8MsbDataValue[LOAD_CODE_I2C_BLOCK_NUM + 5];
646 MS_U16 idx = 0;
647
648 #ifdef MS_DEBUG
649 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
650 {
651 printf("_MDrv_DMD_MSB123xc_SetRegs %x %x\n", u16Addr, data_size);
652 }
653 #endif
654
655 u8MsbDataValue[0] = 0x10;
656 u8MsbDataValue[1] = 0x00;
657 u8MsbDataValue[2] = 0x00;
658 u8MsbDataValue[3] = (u16Addr >> 8) &0xff;
659 u8MsbDataValue[4] = u16Addr & 0xff;
660 // u8MsbDataValue[5] = 0x00;
661
662 for(idx = 0; idx < data_size ; idx++)
663 {
664 u8MsbDataValue[5+idx] = u8pData[idx];
665 }
666
667 u8MsbDataValue[0] = 0x35;
668 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbDataValue);
669
670 u8MsbDataValue[0] = 0x10;
671 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5 + data_size, u8MsbDataValue);
672
673 u8MsbDataValue[0] = 0x34;
674 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbDataValue);
675
676 return bRet;
677 }
678
MDrv_DMD_MSB123xc_SetRegs(MS_U16 u16Addr,MS_U8 * u8pData,MS_U16 data_size)679 MS_BOOL MDrv_DMD_MSB123xc_SetRegs(MS_U16 u16Addr, MS_U8* u8pData, MS_U16 data_size)
680 {
681 MS_BOOL bRet=TRUE;
682
683 DMD_LOCK();
684 bRet = _MDrv_DMD_MSB123xc_SetRegs(u16Addr, u8pData, data_size);
685 DMD_UNLOCK();
686
687 return bRet;
688 }
689
_MDrv_DMD_MSB123xc_SetReg2Bytes(MS_U16 u16Addr,MS_U16 u16Data)690 static MS_BOOL _MDrv_DMD_MSB123xc_SetReg2Bytes(MS_U16 u16Addr, MS_U16 u16Data)
691 {
692 MS_BOOL bRet=TRUE;
693
694 #ifdef MS_DEBUG
695 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
696 {
697 printf("_MDrv_DMD_MSB123xc_SetReg2Bytes %x %x\n", u16Addr, u16Data);
698 }
699 #endif
700
701 bRet &= _MDrv_DMD_MSB123xc_SetReg(u16Addr, (MS_U8)u16Data&0x00ff);
702 bRet &= _MDrv_DMD_MSB123xc_SetReg(u16Addr + 0x0001, (MS_U8)(u16Data>>8)&0x00ff);
703
704 return bRet;
705 }
706
MDrv_DMD_MSB123xc_SetReg2Bytes(MS_U16 u16Addr,MS_U16 u16Data)707 MS_BOOL MDrv_DMD_MSB123xc_SetReg2Bytes(MS_U16 u16Addr, MS_U16 u16Data)
708 {
709 MS_BOOL bRet=TRUE;
710
711 DMD_LOCK();
712 bRet = _MDrv_DMD_MSB123xc_SetReg2Bytes(u16Addr, u16Data);
713 DMD_UNLOCK();
714
715 return bRet;
716 }
717
718
_MDrv_DMD_MSB123xc_GetDSPReg(MS_U16 u16Addr,MS_U8 * pu8Data)719 MS_BOOL _MDrv_DMD_MSB123xc_GetDSPReg(MS_U16 u16Addr, MS_U8 *pu8Data)
720 {
721 MS_BOOL bRet=TRUE;
722 MS_U8 u8Cntl = 0x00;
723 MS_U16 u16Cntr = 0x00;
724
725 bRet &= _MDrv_DMD_MSB123xc_SetReg(REG_MB_ADDR_H, (MS_U8)(u16Addr >> 8));
726 bRet &= _MDrv_DMD_MSB123xc_SetReg(REG_MB_ADDR_L, (MS_U8)(u16Addr));
727 bRet &= _MDrv_DMD_MSB123xc_SetReg(REG_MB_CNTL, 0x03);
728
729 do
730 {
731 bRet &= _MDrv_DMD_MSB123xc_GetReg(REG_MB_CNTL, &u8Cntl);
732 if (u16Cntr++ > 0x7ff)
733 {
734 #ifdef MS_DEBUG
735 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
736 {
737 printf("MSB123xc_MB_READ_FAILURE\n");
738 }
739 #endif
740 return FALSE;
741 }
742 }
743 while(u8Cntl != 0xff);
744
745 bRet &= _MDrv_DMD_MSB123xc_GetReg(REG_MB_DATA, pu8Data);
746
747 #ifdef MS_DEBUG
748 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
749 {
750 printf("MDrv_DMD_MSB123xc_GetDSPReg %x %x\n", u16Addr, *pu8Data);
751 }
752 #endif
753
754 return bRet;
755 }
756
MDrv_DMD_MSB123xc_GetDSPReg(MS_U16 u16Addr,MS_U8 * pu8Data)757 MS_BOOL MDrv_DMD_MSB123xc_GetDSPReg(MS_U16 u16Addr, MS_U8 *pu8Data)
758 {
759 MS_BOOL bRet=TRUE;
760
761 DMD_LOCK();
762 bRet = _MDrv_DMD_MSB123xc_GetDSPReg(u16Addr, pu8Data);
763 DMD_UNLOCK();
764
765 return bRet;
766 }
767
_MDrv_DMD_MSB123xc_SetDSPReg(MS_U16 u16Addr,MS_U8 u8Data)768 MS_BOOL _MDrv_DMD_MSB123xc_SetDSPReg(MS_U16 u16Addr, MS_U8 u8Data)
769 {
770 MS_BOOL bRet=TRUE;
771 MS_U8 u8Cntl = 0x00;
772 MS_U16 u16Cntr = 0x00;
773
774 #ifdef MS_DEBUG
775 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
776 {
777 printf("MDrv_DMD_MSB123xc_SetDSPReg %x %x\n", u16Addr, u8Data);
778 }
779 #endif
780
781 bRet &= _MDrv_DMD_MSB123xc_SetReg(REG_MB_DATA, u8Data);
782 bRet &= _MDrv_DMD_MSB123xc_SetReg(REG_MB_ADDR_H, (MS_U8)(u16Addr >> 8));
783 bRet &= _MDrv_DMD_MSB123xc_SetReg(REG_MB_ADDR_L, (MS_U8)(u16Addr));
784 bRet &= _MDrv_DMD_MSB123xc_SetReg(REG_MB_CNTL, 0x04);
785
786 do
787 {
788 bRet &= _MDrv_DMD_MSB123xc_GetReg(REG_MB_CNTL, &u8Cntl);
789 if (u16Cntr++ > 0x7ff)
790 {
791 #ifdef MS_DEBUG
792 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
793 {
794 printf("MSB123xc_MB_WRITE_FAILURE\n");
795 }
796 #endif
797 return false;
798 }
799 }
800 while(u8Cntl != 0xff);
801 return bRet;
802 }
803
MDrv_DMD_MSB123xc_SetDSPReg(MS_U16 u16Addr,MS_U8 u8Data)804 MS_BOOL MDrv_DMD_MSB123xc_SetDSPReg(MS_U16 u16Addr, MS_U8 u8Data)
805 {
806 MS_BOOL bRet=TRUE;
807
808 DMD_LOCK();
809 bRet = _MDrv_DMD_MSB123xc_SetDSPReg(u16Addr, u8Data);
810 DMD_UNLOCK();
811
812 return bRet;
813 }
814
_MSB123xc_I2C_CH_Reset(MS_U8 ch_num)815 static MS_BOOL _MSB123xc_I2C_CH_Reset(MS_U8 ch_num)
816 {
817 MS_BOOL bRet=TRUE;
818 //MAPI_U8 addr[4] = {0x00, 0x00, 0x00, 0x00};
819 MS_U8 u8data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
820
821 #ifdef MS_DEBUG
822 printf("[msb123xc][beg]I2C_CH_Reset, CH=0x%x\n",ch_num);
823 #endif
824 //DMD_LOCK_REG_RW();
825
826 // 8'hb2(SRID)->8,h53(PWD1)->8,h45(PWD2)->8,h52(PWD3)->8,h44(PWD4)->8,h42(PWD5)
827 //u8data[0] = 0x53;
828 //bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8data);
829 if (bDemodRest)
830 {
831 bDemodRest = FALSE;
832 // 8'hb2(SRID)->8,h53(PWD1)->8,h45(PWD2)->8,h52(PWD3)->8,h44(PWD4)->8,h42(PWD5)
833 u8data[0] = 0x53;
834 // Don't check Ack because this passward only ack one time for the first time.
835 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8data);
836 }
837 // 8'hb2(SRID)->8,h71(CMD) //TV.n_iic_
838 u8data[0] = 0x71;
839 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
840
841 // 8'hb2(SRID)->8,h81(CMD) //TV.n_iic_sel_b0
842 u8data[0] = ((ch_num & 0x01) != 0)? 0x81 : 0x80;
843 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
844
845 // 8'hb2(SRID)->8,h83(CMD) //TV.n_iic_sel_b1
846 u8data[0] = ((ch_num & 0x02) != 0)? 0x83 : 0x82;
847 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
848
849 // 8'hb2(SRID)->8,h84(CMD) //TV.n_iic_sel_b2
850 u8data[0] = ((ch_num & 0x04) != 0)? 0x85 : 0x84;
851 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
852
853 // 8'hb2(SRID)->8,h53(CMD) //TV.n_iic_ad_byte_en2, 32bit read/write
854 u8data[0] = 0x53;
855 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
856
857 // 8'hb2(SRID)->8,h7f(CMD) //TV.n_iic_sel_use_cfg
858 u8data[0] = 0x7f;
859 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
860
861 /*
862 // 8'hb2(SRID)->8,h35(CMD) //TV.n_iic_use
863 data[0] = 0x35;
864 iptr->WriteBytes(0, NULL, 1, data);
865
866 // 8'hb2(SRID)->8,h71(CMD) //TV.n_iic_Re-shape
867 data[0] = 0x71;
868 iptr->WriteBytes(0, NULL, 1, data);
869 */
870 //DMD_UNLOCK_REG_RW();
871 #ifdef MS_DEBUG
872 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]I2C_CH_Reset, CH=0x%x\n",ch_num));
873 #endif
874 return bRet;
875 }
876
_MSB123xc_HW_init(void)877 static MS_BOOL _MSB123xc_HW_init(void)
878 {
879 MS_BOOL bRet = true;
880 MS_U8 u8_tmp = 0;
881 MS_U8 u8_timeout = 0;
882
883 #ifdef MS_DEBUG
884 printf("[msb123xc][beg]MSB123xc_HW_init\n");
885 #endif
886 //DMD_LOCK();
887
888 // ASIC INIT for EDB DVB-T2
889 {
890 // Reset MCU
891 // wreg 11 0x19 0x0003 // don't do this in MCU firmware!
892 // -------------------------------------------------------------------
893 // Initialize DMD_ANA_MISC
894 // -------------------------------------------------------------------
895 // [1:0] reg_mpll_loop_div_first feedback divider 00:div by 1 01:div by 2 10:div by 4 11:div by 8
896 // [15:8] reg_mpll_loop_div_second feedback divider, div by binary data number
897 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h33, 2'b11, 16'h2400); // Loop divider ; VCO = 24*(2^2)*9 = 864
898 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x33)*2, 0x2400);
899
900 // [2:0] reg_mpll_ictrl charge pump current control
901 // [3] reg_mpll_in_sel 1.8V or 3.3V reference clock domain select (1'b0=0==>3.3 V reference clock domain)
902 // [4] reg_mpll_xtal2adc_sel select the XTAL clock bypass to MPLL_ADC_CLK
903 // [5] reg_mpll_xtal2next_pll_sel crystal clock bypass to next PLL select
904 // [6] reg_mpll_vco_offset set VCO initial offset frequency
905 // [7] reg_mpll_pd gated reference clock and power down PLL analog_3v: 1=power down
906 // [8] reg_xtal_en XTAL enable register; 1: enable
907 // [10:9] reg_xtal_sel XTAL driven strength select.
908 // [11] reg_mpll_porst MPLL input power on reset, connect to reg as MPLL_RESET
909 // [12] reg_mpll_reset PLL software reset; 1:reset
910 // [13] reg_pd_dmpll_clk XTAL to MPLL clock reference power down
911 // [14] reg_pd_3p3_1 XTAL to CLK_24M_3P3_1 power down
912 // [15] reg_pd_3p3_2 XTAL to CLK_24M_3P3_2 power down
913 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x35)*2, 0x1804);
914 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x35)*2, 0x0004);
915
916 // [15:0] reg_mpll_test
917 // [14] mpll reset
918 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x34)*2, 0x4000);
919 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x34)*2, 0x0000);
920
921 // [0] reg_mpll_clk_dp_pd dummy
922 // [1] reg_adc_clk_pd ADC output clock power down
923 // [2] reg_mpll_div2_pd MPLL_DIV2 power down
924 // [3] reg_mpll_div3_pd MPLL_DIV3 power down
925 // [4] reg_mpll_div4_pd MPLL_DIV4 power down
926 // [5] reg_mpll_div8_pd MPLL_DIV8 power down
927 // [6] reg_mpll_div10_pd MPLL_DIV10 power down
928 // [13:8] reg_mpll_adc_div_sel select the ADC clock divide ratio,ADC clk=XTAL_IN * (LOOP_DIV_FIRST*LOOP_DIV_SECOND)/div_ratio
929 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h30, 2'b11, 16'h1e00); // divide ADC clock to 28.8Mhz = 24*36/30
930 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x30)*2, 0x1e00);
931
932
933 // --------------------------------------
934 // Initialize ADC I/Q");
935 // --------------------------------------
936 // Set IMUXS QMUXS
937 // [0] Q channel ADC power down
938 // [1] I channel ADC power down
939 // [2] Q channel clamp enable. 0:enable, 1:disable
940 // [3] I channel clamp enable. 0:enable, 1:disable
941 // [6:4] I channel input mux control;
942 // 3'b000=I channel ADC calibration mode input
943 // 3'b001=VIF signal from VIFPGA
944 // 3'b100=DVB or ATSC mode input from PAD_I(Q)P(M)
945 // all the other combination are only for test mode, don't use without understanding.
946 // [10:8] Q channel input mux control;
947 // 3'b000=Q channel ADC calibration mode input
948 // 3'b001=VIF signal from VIFPGA 3'b010 = SSIF signal from PAD_SIFP(M)
949 // 3'b100=DVB or ATSC mode input from PAD_I(Q)P(M)
950 // all the other combination are only for test mode, don't use without understanding.
951 // [12] ADC I,Q swap enable; 1: swap
952 // [13] ADC clock out select; 1: ADC_CLKQ
953 // [14] ADC linear calibration bypass enable; 1:enable
954 // [15] ADC internal 1.2v regulator control always 0 in T3
955 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x01)*2, 0x0440);
956
957 // Set enable ADC clock
958 // [0] Channel I ADC power down: 1=power dwon
959 // [1] Channel Q ADC power down: 1=power dwon
960 // [2] power down clamp buffer for test mode
961 // [3] change ADC reference voltage for SSIF
962 // [6:4] ADC source bias current control
963 // [9:8] XTAL receiver amp gain
964 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x0c)*2, 0x0000);
965
966 // Disable PWDN_REF
967 // [3:0] clamp voltage control
968 // 3'b000 = 0.7v
969 // 3'b001 = 0.75v
970 // 3'b010 = 0.5v
971 // 3'b011 = 0.4v
972 // 3'b100 = 0.8v
973 // 3'b101 = 0.9v
974 // 3'b110 = 0.65v
975 // 3'b111 = 0.60v
976 // [4] REFERENCE power down
977 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x20)*2, 0x0000);
978
979 // Set ADC gain is 1
980 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x0b)*2, 0x0009);
981
982 // Disable ADC Sign bit
983 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x2e)*2, 0x0000);
984
985 // ADC I channel offset
986 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x2a)*2, 0x0c00);
987
988 // ADC Q channel offset
989 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x2b)*2, 0x0c00);
990
991 // [2:0]reg_acl_ref
992 // [5:4]reg_acl_isel
993 // [8] reg_xtal_pm_isel
994 // [9] reg_bond_mode
995 // [10] reg_clk_bond_mode
996 // [11] reg_clk_usb_3p3_en
997 // [13:12] reg_iq_ctrl = 2'd1
998 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x19)*2, 0x1e00);
999
1000 // [ 4:0]reg_ckg_bist[4:0]
1001 // [11:8]reg_ckg_adcd_d2[3:0]
1002 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x1c)*2, 0x0000);
1003
1004 // [ 4:0]reg_ckg_dvbtm_sram_t11x_t22x[4:0]
1005 // [12:8]reg_ckg_dvbtm_sram_t11x_t24x[4:0]
1006 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x1e)*2, 0x0000);
1007
1008 // [15:0] reg_mpll_test
1009 // [4] mpll lock detector enable
1010 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0A00+(0x34)*2, 0x0010);
1011
1012 // -------------------------------------------------------------------
1013 // Release clock gating
1014 // -------------------------------------------------------------------
1015
1016 // [0] reg_xtal_en
1017 // [9:8] reg_clk_pd_iic
1018 // [10] reg_clk_pd_all
1019 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x09)*2, 0x0101);
1020
1021 // [3:0] reg_ckg_adcd
1022 // [7:4] reg_ckg_sadc
1023 // [11:8] reg_ckg_iicm
1024 // [13:12] reg_ckg_sbus
1025 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x0a)*2, 0x0000);
1026
1027 // [5:0] reg_ckg_mcu
1028 // [6] reg_ckg_live
1029 // [11:8] reg_ckg_inner
1030 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x0b)*2, 0x0030);
1031
1032 // @0x0910
1033 // [3:0] reg_ckg_dvbtm_adc
1034 // [6:4] reg_ckg_dvbt_inner1x
1035 // [10:8] reg_ckg_dvbt_inner2x
1036 // [14:12] reg_ckg_dvbt_inner4x
1037 //DVBT2
1038 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x10)*2, 0x1110);
1039
1040 // @0x0911
1041 // [2:0] reg_ckg_dvbt_outer1x
1042 // [6:4] reg_ckg_dvbt_outer2x
1043 // [11:8] reg_ckg_dvbtc_outer2x
1044 //DVBT2
1045 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x11)*2, 0x0111);
1046
1047 // @0x0912
1048 // [3:0] reg_ckg_dvbtm_ts
1049 // [4] reg_dvbtm_ts_out_mode
1050 // [5] reg_dvbtm_ts_clk_pol
1051 // [15:8] reg_dvbtm_ts_clk_divnum
1052 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x12)*2, 0x0618);
1053
1054 // @0x0913
1055 // [5:0] reg_ckg_spi
1056 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x13)*2, 0x0020);
1057
1058 // @0x0914
1059 // [12:8] reg_ckg_dvbtm_sram_t1o2x_t22x
1060 //DVBT2
1061 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x14)*2, 0x0000);
1062 // `endif
1063
1064 // @0x0915
1065 // [3:0] reg_ckg_dvbc_inner
1066 // [6:4] reg_ckg_dvbc_eq
1067 // [10:8] reg_ckg_dvbc_eq8x
1068 //DVBT2
1069 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x15)*2, 0x0111);
1070
1071 // @0x0916
1072 // [3:0] reg_ckg_dvbtm_adc_2x_4x
1073 // [8:4] reg_ckg_dvbtm_sram_adc_t22x
1074 //DVBT2
1075 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x16)*2, 0x0001);
1076 // `endif
1077
1078 // @0x0917
1079 // [4:0] reg_ckg_dvbtm_sram_t12x_t22x
1080 // [12:8] reg_ckg_dvbtm_sram_t12x_t24x
1081 //DVBT2
1082 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x17)*2, 0x0000);
1083
1084 // @0x0918
1085 // [4:0] reg_ckg_dvbtm_sram_t14x_t24x
1086 // [12:8] reg_ckg_dvbtm_ts_in
1087 //DVBT2
1088 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x18)*2, 0x1000);
1089 // `endif
1090
1091 // @0x0919
1092 // [2:0] reg_ckg_tdp_jl_inner1x
1093 // [6:4] reg_ckg_tdp_jl_inner4x
1094 // [15:8] reg_ckg_miu
1095 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x19)*2, 0x3c00);
1096
1097 // @0x091a
1098 // [6:4] reg_ckg_dvbt2_inner1x
1099 // [10:8] reg_ckg_dvbt2_inner2x
1100 // [14:12] reg_ckg_dvbt2_inner4x
1101 //DVBT2
1102 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x1a)*2, 0x0000);
1103
1104 // @0x091b
1105 // [2:0] reg_ckg_dvbt2_outer1x
1106 // [6:4] reg_ckg_dvbt2_outer2x
1107 // [10:8] reg_ckg_syn_miu
1108 // [14:12] reg_ckg_syn_ts
1109 //DVBT2
1110 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x1b)*2, 0x0000);
1111
1112
1113 // @0x091c
1114 // [4:0] reg_ckg_bist
1115 // [11:8] reg_ckg_adcd_d2
1116 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x1c)*2, 0x0000);
1117
1118
1119 // [1:0] reg_iicm_pad_sel
1120 // [4] reg_i2c_sbpm_en
1121 // [12:8] reg_i2c_sbpm_idle_num
1122 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x08)*2, 0x0a01);
1123
1124 // [8] reg_turn_off_pad
1125 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x28)*2, 0x0000);
1126
1127 // [15:0] reg_synth_set[15: 0]
1128 // [ 7:0] reg_synth_set[23:16]
1129 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x51)*2, 0x0000);
1130 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x52)*2, 0x0020);
1131
1132
1133 // [0] reg_synth_reset
1134 // [1] reg_synth_ssc_en
1135 // [2] reg_synth_ssc_mode
1136 // [4] reg_synth_sld
1137 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x50)*2, 0x0010);
1138
1139 // [1:0] reg_apll_loop_div_first
1140 // [15:8] reg_apll_loop_div_second
1141 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x57)*2, 0x0003);
1142
1143
1144 // [0] reg_apll_pd
1145 // [1] reg_apll_reset
1146 // [2] reg_apll_porst
1147 // [3] reg_apll_vco_offset
1148 // [4] reg_apll_en_ts
1149 // [5] reg_apll_endcc
1150 // [6] reg_apll_clkin_sel
1151 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x55)*2, 0x0006);
1152 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x55)*2, 0x0010);
1153
1154 // [16:0] reg_apll_test
1155 // [4] lock detector enable
1156 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x59)*2, 0x0010);
1157
1158 // 0x0920
1159 // [3:0] reg_ckg_ts_apll_div[2:0]
1160 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x20)*2, 0x0004);
1161
1162 // -------------------------------------------------------------------
1163 // initialize MIU
1164 // -------------------------------------------------------------------
1165 // $display("--------------------------------------");
1166 // $display("Initialize MIU ");
1167 // $display("--------------------------------------");
1168
1169 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x0f)*2, 0x0000);
1170 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x0f)*2, 0x0000);
1171 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x0f)*2, 0x0000);
1172 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c01);
1173 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c00);
1174 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x11)*2, 0x0052);
1175
1176 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x10)*2, 0x352b); // 0x29a378 = 166MHz, 0x352b52 = 130MHz
1177 //execute reset and porst
1178 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x11)*2, 0x6052);
1179 //exit reset and porst
1180 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x11)*2, 0x0052);
1181
1182 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x12)*2, 0xc000);
1183 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x13)*2, 0x0000);
1184 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x16)*2, 0x0030);
1185 //bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x1c)*2, 0x0080);
1186 // 2012/12/06 add best MIU phase by jason-bf.huang
1187 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x1c)*2, 0x00a0);
1188 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x1b)*2, 0x0067);
1189
1190
1191 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x01)*2, 0x8100);
1192 // cke : [0]
1193 // reg_self_refresh : [1]
1194 // reg_dynamic_cke : [2]
1195 // reg_dynamic_ck_odt : [3]
1196 // reg_dram_bus : [5:4] 00: 16b, 01: 32b, 10: 64b
1197 // reg_dram_type : [7:6] 00: sdr, 01: ddr, 10: ddr2
1198 // reg_4ba : [8] 0: 2bk, 1: 4bk
1199 // reg_col_size : [10:9]
1200 // reg_cke_oenz : [12]
1201 // reg_dq_oenz : [13]
1202 // reg_adr_oenz : [14]
1203 // reg_cs_z : [15]
1204 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x01)*2, 0xe100);
1205 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x01)*2, 0x8100);
1206 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x02)*2, 0x0360);
1207 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x03)*2, 0x0030);
1208 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x04)*2, 0x33c9);
1209 // reg_tRAS : [3:0] 9
1210 // reg_tRC : [7:4] c
1211 // reg_tRCD : [11:8] 3
1212 // reg_tRP : [15:12] 3
1213 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x05)*2, 0x4232);
1214 // reg_tRRD : [3:0] 2
1215 // tWR : [7:4] 3
1216 // reg_tMRD : [11:8] 2
1217 // reg_tRTP : [15:12] 4
1218 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x06)*2, 0x5532);
1219 // reg_w2r_dly(tWTR) : [3:0] 2
1220 // reg_w2r_oen_dly : [7:4] 3
1221 // reg_r2w_dly(tRTW) : [11:8] 5
1222 // reg_r2w_oen_dly : [15:12] 5
1223 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x07)*2, 0x400c);
1224 // tRFC : [5:0] c
1225 // reg_tRAS[4] : [6] 0
1226 // reg_tRC[4] : [7] 0
1227 // reg_write_latency : [10:8] 0
1228 // reg_tCCD : [15:14] 1
1229 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x0e)*2, 0x1800);
1230
1231 //mask other request
1232 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x23)*2, 0x7ffe);
1233
1234 //reg_rq0_round_robin : [0]
1235 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x20)*2, 0xc001);
1236
1237 MsOS_DelayTaskUs(1000);
1238
1239 //miu software reset
1240 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c01);
1241 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c00);
1242 //miu software reset
1243 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c01);
1244 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c00);
1245
1246 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x01)*2, 0x010d);
1247
1248 // --------Initial DRAM start here!!!-------
1249 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x00)*2, 0x0001);
1250
1251 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x1201, &u8_tmp);
1252 u8_timeout = 0;
1253 while( (u8_tmp&0x80) != 0x80)
1254 {
1255 if(u8_timeout++>200)
1256 {
1257 printf("[msb1233c][err]MIU init failure...\n");
1258 return FALSE;
1259 }
1260 // 10us delay
1261 MsOS_DelayTaskUs(10);
1262 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x1201, &u8_tmp);
1263 }
1264 // --------Initial Done-------
1265
1266 //turn on report counter : [0]
1267 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x08)*2, 0x0001);
1268
1269 // -- miu self test start --
1270 //base
1271 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x71)*2, 0x0000);
1272 //length
1273 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x72)*2, 0x0010);
1274 //test data
1275 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x74)*2, 0x5aa5);
1276 //reg_test_en : [0]
1277 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x70)*2, 0x0001);
1278 // reg_test_mode : [2:1] 00 : address,
1279 // 01 : test data
1280 // 10 : shift data
1281 // reg_inv_data : [3]
1282 // reg_test_loop : [4]
1283 // reg_force_out : [5]
1284 // reg_force_in : [6]
1285 // reg_read_only : [8]
1286 // reg_write_only : [9]
1287
1288 MsOS_DelayTaskUs(1000);
1289
1290 //wait test_finish
1291 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x12E1, &u8_tmp);
1292 u8_timeout = 0;
1293 while( (u8_tmp&0x80) != 0x80)
1294 {
1295 if(u8_timeout++>200)
1296 {
1297 printf("[msb1233c][err]MIU self test Phase1 failure...\n");
1298 return FALSE;
1299 }
1300 // 10us delay
1301 MsOS_DelayTaskUs(10);
1302 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x12E1, &u8_tmp);
1303 }
1304
1305 MsOS_DelayTaskUs(1000);
1306
1307 // MIU self test FAIL let program stuck in this while loop
1308 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x12E1, &u8_tmp);
1309 u8_timeout = 0;
1310 while( (u8_tmp&0x40) != 0x00)
1311 {
1312 if(u8_timeout++>200)
1313 {
1314 printf("[msb1233c][err]MIU self test Phase2 failure...\n");
1315 return FALSE;
1316 }
1317 // 10us delay
1318 MsOS_DelayTaskUs(10);
1319 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x12E1, &u8_tmp);
1320 }
1321
1322 //reg_rq0_mask
1323 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1200+(0x23)*2, 0x0000);
1324
1325
1326 // -------------------------------------------------------------------
1327 // initialize MIU finish
1328 // -------------------------------------------------------------------
1329
1330 // -------------------------------------------------------------------
1331 // Turn on pads
1332 // -------------------------------------------------------------------
1333
1334 // ------Turn off all pad in
1335 // [0] reg_set_pad_low
1336 // [1] reg_set_pad_high
1337 // [2] reg_set_i2cs_pad_low
1338 // [3] reg_set_i2cs_pad_high
1339 // [8] reg_turn_off_pad
1340 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x28)*2, 0x0000);
1341
1342 // ------I2CM pad on
1343 // [1:0] reg_iicm_pad_sel[1:0] 1:iicm enable 2:UART enable
1344 // [4] reg_i2c_sbpm_en 1: enable I2CS bypass to I2CM function
1345 // [12:8] reg_i2c_sbpm_idle_num[4:0] a: default
1346 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x08)*2, 0x0a01);
1347
1348 // ------Transport Stream pad on (except TS ERR pad)
1349 // [15:0] reg_en_ts_pad[15:0] 0x00ff:normal TS location 0xff00:reverse TS location
1350 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x2d)*2, 0x00ff);
1351
1352 // ------Transport Stream pad on (TS ERR pad)
1353 // [0] reg_en_ts_err_pad 1: enable
1354 // [4] reg_ts_err_pol 1: inverse 0:normal
1355 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900+(0x2e)*2, 0x0001);
1356
1357 // ------AGC pad on
1358 // [4] reg_ifagc_enable Tuner IF AGC enable. 1:enable
1359 // [5] reg_ifagc_odmode 1: inverse IF AGC
1360 // [6] reg_ifagc_data_sel IFAGC data select 0: IF AGC 1: RF AGC
1361 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0a00+(0x18)*2, 0x0010);
1362 }
1363
1364 //DMD_UNLOCK();
1365 #ifdef MS_DEBUG
1366 printf("[msb123xc][end]MSB123xc_HW_init, bRet=0x%x\n",bRet);
1367 #endif
1368 return bRet;
1369 }
1370
_Load2Sdram(MS_U8 * u8_ptr,MS_U16 data_length,MS_U16 sdram_win_offset_base)1371 static MS_BOOL _Load2Sdram(MS_U8 *u8_ptr, MS_U16 data_length, MS_U16 sdram_win_offset_base)
1372 {
1373 MS_BOOL bRet = true;
1374 MS_U16 sdram_win_offset = sdram_win_offset_base;
1375 MS_U16 x_data_offset = 0;
1376 MS_U16 y_cir_addr = 0;
1377 #ifdef MS_DEBUG
1378 MS_U32 u32tmm_3 = 0, u32tmm_4 = 0;
1379 #endif
1380
1381 #ifdef MS_DEBUG
1382 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1383 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]Load2Sdram, len=0x%x, win_offset=0x%x\n",data_length,sdram_win_offset_base));
1384 u32tmm_3 = MsOS_GetSystemTime();
1385 #endif
1386
1387 if (_sDMD_MSB123xc_InitData.bEnableSPILoadCode)
1388 {
1389 MS_U32 u32Addr = 0;
1390
1391 u32Addr = (MS_U32)sdram_win_offset_base * 0x1000; // unit: 4K
1392 bRet &= MDrv_DMD_SSPI_MIU_Writes(u32Addr, u8_ptr, data_length);
1393 #ifdef MS_DEBUG
1394 DBG_DEMOD_LOAD_I2C(printf("[msb123xc]u32Addr=%08lx\n",u32Addr));
1395 #endif
1396
1397 #if (SDRAM_DATA_CHECK == 1)
1398 #ifdef MS_DEBUG
1399 DBG_DEMOD_LOAD_I2C(printf("[msb123xc]SDRAM data check...\n"));
1400 #endif
1401 MS_U16 i = 0, j = 0, index = 0;
1402 MS_U8 buf[SPI_DEVICE_BUFFER_SIZE]= {0};
1403
1404 if((data_length % SPI_DEVICE_BUFFER_SIZE) == 0)
1405 index = data_length / SPI_DEVICE_BUFFER_SIZE;
1406 else
1407 index = data_length / SPI_DEVICE_BUFFER_SIZE + 1;
1408
1409 for (i=0; i<index; i++)
1410 {
1411 memset(buf, 0x00, SPI_DEVICE_BUFFER_SIZE);
1412
1413 bRet &= MDrv_DMD_SSPI_MIU_Reads(u32Addr+SPI_DEVICE_BUFFER_SIZE*i, buf, SPI_DEVICE_BUFFER_SIZE);
1414 for (j=0; j<SPI_DEVICE_BUFFER_SIZE; j++)
1415 {
1416 if (buf[j] != u8_ptr[SPI_DEVICE_BUFFER_SIZE*i+j])
1417 {
1418 printf("[msb123xc]error, u32Addr=0x%08lx, y=0x%x, x=0x%x\n",u32Addr+j, buf[j] , u8_ptr[j]);
1419 }
1420 }
1421 }
1422 #ifdef MS_DEBUG
1423 DBG_DEMOD_LOAD_I2C(printf("[msb123xc]SDRAM data check...Done\n"));
1424 #endif
1425 #endif
1426 }
1427 else
1428 {
1429 if ( _MSB123xc_I2C_CH_Reset(0) == FALSE)
1430 {
1431 printf(">>>MSB123xc CH0 Reset:Fail\n");
1432 return FALSE;
1433 }
1434 else
1435 {
1436
1437 // set xData map upper and low bound for 64k DRAM window
1438 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x2B00+(0x63)*2, 0x3F24);
1439
1440 // set xData map offset for 64k DRAM window, 64kbytes alignment
1441 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x2B00+(0x64)*2, 0x0000);
1442
1443 // set xData map upper and low bound for 4k DRAM window
1444 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x2B00+(0x65)*2, 0x2014);
1445
1446 // set xData map offset for 4k DRAM window, 4kbytes alignment
1447 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x2B00+(0x66)*2, sdram_win_offset++);
1448
1449 // enable xData map for DRAM
1450 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x2B00+(0x62)*2, 0x0007);
1451
1452 for(x_data_offset = 0, y_cir_addr = SDRAM_BASE; x_data_offset < data_length;)
1453 {
1454 if (y_cir_addr == (SDRAM_BASE+SDRAM_WINDOW_SIZE))
1455 {
1456 //set xData map offset for 4k DRAM window, 4kbytes alignment
1457 // 0x1000, 4096 bytes
1458 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x2B00+(0x66)*2, sdram_win_offset++);
1459 y_cir_addr = SDRAM_BASE;
1460 }
1461
1462 // max 0x200, error above.....
1463
1464 if((data_length - x_data_offset) >= LOAD_CODE_I2C_BLOCK_NUM)
1465 {
1466 bRet &= _MDrv_DMD_MSB123xc_SetRegs(y_cir_addr, (u8_ptr + x_data_offset),LOAD_CODE_I2C_BLOCK_NUM);
1467 y_cir_addr += LOAD_CODE_I2C_BLOCK_NUM;
1468 x_data_offset += LOAD_CODE_I2C_BLOCK_NUM;
1469 }
1470 else
1471 {
1472 bRet &= _MDrv_DMD_MSB123xc_SetRegs(y_cir_addr, (u8_ptr + x_data_offset),data_length - x_data_offset);
1473 y_cir_addr += (data_length - x_data_offset);
1474 x_data_offset += (data_length - x_data_offset);
1475 }
1476 }
1477
1478 #ifdef MS_DEBUG
1479 DBG_DEMOD_LOAD_I2C(printf("[msb123xc]x_data_offset=%d,y_cir_addr=%d,z_block_num=%d\n",x_data_offset,y_cir_addr,sdram_win_offset));
1480 #endif
1481 #if (SDRAM_DATA_CHECK == 1)
1482 // beg data check.
1483 #ifdef MS_DEBUG
1484 DBG_DEMOD_LOAD_I2C(printf("[msb123xc]SDRAM data check...\n"));
1485 #endif
1486
1487 sdram_win_offset = sdram_win_offset_base;
1488
1489 // set xData map offset for 4k DRAM window, 4kbytes alignment
1490 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x2B00+(0x66)*2, sdram_win_offset++);
1491
1492 for(x_data_offset = 0, y_cir_addr = SDRAM_BASE; x_data_offset < data_length;)
1493 {
1494 MS_U8 u8_tmp;
1495 if (y_cir_addr == (SDRAM_BASE+SDRAM_WINDOW_SIZE))
1496 {
1497 //set xData map offset for 4k DRAM window, 4kbytes alignment
1498 // 0x1000, 4096 bytes
1499 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x2B00+(0x66)*2, sdram_win_offset++);
1500 y_cir_addr = SDRAM_BASE;
1501 }
1502
1503 bRet &= _MDrv_DMD_MSB123xc_GetReg(y_cir_addr++, &u8_tmp);
1504 if(u8_tmp != *(u8_ptr + x_data_offset++))
1505 {
1506 printf("[msb123xc]error, idx=0x%x, y=0x%x, x=0x%x\n",y_cir_addr-1, u8_tmp, *(u8_ptr + x_data_offset-1));
1507 }
1508 }
1509
1510 #ifdef MS_DEBUG
1511 DBG_DEMOD_LOAD_I2C(printf("[msb123xc]SDRAM data check...Done\n"));
1512 #endif
1513
1514 // end data check
1515 #endif
1516 // Release xData map for SDRAM
1517 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x2B00+(0x62)*2, 0x0000);
1518
1519 // Channel changed from CH 0x00 to CH 0x03
1520 if (_MSB123xc_I2C_CH_Reset(3) == FALSE)
1521 {
1522 #ifdef MS_DEBUG
1523 ERR_DOMOD_MSB(printf(">>>MSB123xc CH3 Reset:Fail\n"));
1524 #endif
1525 return FALSE;
1526 }
1527 }
1528 }
1529 #ifdef MS_DEBUG
1530 u32tmm_4 = MsOS_GetSystemTime();
1531 printf("[tmm2]t4-t3 = %ld (%ld - %ld)\n",u32tmm_4-u32tmm_3,u32tmm_4,u32tmm_3);
1532 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]Load2Sdram, len=0x%x, win_offset=0x%x\n",data_length,sdram_win_offset_base));
1533 if (!bRet) printf("%s %d Error\n",__func__, __LINE__);
1534 #endif
1535
1536 return bRet;
1537 }
1538
_LoadDspCodeToSDRAM_Boot(void)1539 static MS_BOOL _LoadDspCodeToSDRAM_Boot(void)
1540 {
1541 MS_BOOL bRet = true;
1542 MS_U16 code_size, win_offset;
1543 MS_U8 *data_ptr;
1544
1545 #ifdef MS_DEBUG
1546 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1547 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]LoadDspCodeToSDRAM_Boot\n"));
1548 #endif
1549
1550 if(!(u8DMD_MSB123xc_Sdram_Code&MSB123xc_BOOT))
1551 {
1552 if(sizeof(MSB123xc_LIB) > EDINBURGH_BOOT_START_ADDR)
1553 {
1554 // boot code
1555 data_ptr = MSB123xc_LIB + EDINBURGH_BOOT_START_ADDR;
1556 code_size = EDINBURGH_BOOT_END_ADDR - EDINBURGH_BOOT_START_ADDR + 1;
1557 win_offset = EDINBURGH_BOOT_WINDOWS_OFFSET;
1558 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
1559 if(bRet == true)
1560 {
1561 u8DMD_MSB123xc_Sdram_Code |= MSB123xc_BOOT;
1562 }
1563 }
1564 else
1565 {
1566 printf("@msb123xc, boot code is unavailable!!!\n");
1567 }
1568 }
1569 #ifdef MS_DEBUG
1570 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]LoadDspCodeToSDRAM_Boot\n"));
1571 #endif
1572 return bRet;
1573 }
1574
_LoadDspCodeToSDRAM_dvbt2(void)1575 static MS_BOOL _LoadDspCodeToSDRAM_dvbt2(void)
1576 {
1577 MS_BOOL bRet = true;
1578 MS_U16 code_size, win_offset;
1579 MS_U8 *data_ptr;
1580
1581 #ifdef MS_DEBUG
1582 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1583 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]LoadDspCodeToSDRAM_dvbt2\n"));
1584 #endif
1585
1586 if( !(u8DMD_MSB123xc_Sdram_Code&MSB123xc_DVBT2) )
1587 {
1588 if(sizeof(MSB123xc_LIB) > EDINBURGH_DVBT2_P1_START_ADDR)
1589 {
1590 // dvbt2_p2
1591 data_ptr = MSB123xc_LIB + EDINBURGH_DVBT2_P2_START_ADDR;
1592 code_size = EDINBURGH_DVBT2_P2_END_ADDR - EDINBURGH_DVBT2_P2_START_ADDR + 1;
1593 win_offset = EDINBURGH_DVBT2_P2_WINDOWS_OFFSET;
1594 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
1595
1596 // dvbt2_p1
1597 data_ptr = MSB123xc_LIB + EDINBURGH_DVBT2_P1_START_ADDR;
1598 code_size = EDINBURGH_DVBT2_P1_END_ADDR - EDINBURGH_DVBT2_P1_START_ADDR + 1;
1599 win_offset = EDINBURGH_DVBT2_P1_WINDOWS_OFFSET;
1600 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
1601
1602 if(bRet == true)
1603 {
1604 u8DMD_MSB123xc_Sdram_Code |= MSB123xc_DVBT2;
1605 }
1606 }
1607 else
1608 {
1609 #ifdef MS_DEBUG
1610 ERR_DOMOD_MSB(printf("@msb123xc, dvbt2 code is unavailable!!!\n"));
1611 #endif
1612 }
1613 }
1614 #ifdef MS_DEBUG
1615 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]LoadDspCodeToSDRAM_dvbt2\n"));
1616 #endif
1617 return bRet;
1618 }
1619
_LoadDspCodeToSDRAM_dvbt(void)1620 static MS_BOOL _LoadDspCodeToSDRAM_dvbt(void)
1621 {
1622 MS_BOOL bRet = true;
1623 MS_U16 code_size, win_offset;
1624 MS_U8 *data_ptr;
1625
1626 #ifdef MS_DEBUG
1627 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1628 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]LoadDspCodeToSDRAM_dvbt\n"));
1629 #endif
1630
1631 if(!(u8DMD_MSB123xc_Sdram_Code&MSB123xc_DVBT))
1632 {
1633 // dvbt code
1634 if(sizeof(MSB123xc_LIB) > EDINBURGH_DVBT_START_ADDR)
1635 {
1636 data_ptr = MSB123xc_LIB + EDINBURGH_DVBT_START_ADDR;
1637 code_size = EDINBURGH_DVBT_END_ADDR - EDINBURGH_DVBT_START_ADDR + 1;
1638 win_offset = EDINBURGH_DVBT_WINDOWS_OFFSET;
1639 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
1640 if(bRet == true)
1641 {
1642 u8DMD_MSB123xc_Sdram_Code |= MSB123xc_DVBT;
1643 }
1644 }
1645 else
1646 {
1647 printf("@msb123xc, dvbt code is unavailable!!!\n");
1648 }
1649 }
1650 #ifdef MS_DEBUG
1651 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]LoadDspCodeToSDRAM_dvbt\n"));
1652 #endif
1653 return bRet;
1654 }
1655
_LoadDspCodeToSDRAM_dvbc(void)1656 static MS_BOOL _LoadDspCodeToSDRAM_dvbc(void)
1657 {
1658 MS_BOOL bRet = true;
1659 MS_U16 code_size, win_offset;
1660 MS_U8 *data_ptr;
1661
1662 #ifdef MS_DEBUG
1663 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1664 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]LoadDspCodeToSDRAM_dvbc\n"));
1665 #endif
1666
1667 if(!(u8DMD_MSB123xc_Sdram_Code&MSB123xc_DVBC))
1668 {
1669 // dvbc code
1670 if(sizeof(MSB123xc_LIB) > EDINBURGH_DVBC_START_ADDR)
1671 {
1672 data_ptr = MSB123xc_LIB + EDINBURGH_DVBC_START_ADDR;
1673 code_size = EDINBURGH_DVBC_END_ADDR - EDINBURGH_DVBC_START_ADDR + 1;
1674 win_offset = EDINBURGH_DVBC_WINDOWS_OFFSET;
1675 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
1676 if(bRet == true)
1677 {
1678 u8DMD_MSB123xc_Sdram_Code |= MSB123xc_DVBC;
1679 }
1680 }
1681 else
1682 {
1683 printf("@msb123xc, dvbc code is unavailable!!!\n");
1684 }
1685 }
1686 #ifdef MS_DEBUG
1687 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]LoadDspCodeToSDRAM_dvbc\n"));
1688 #endif
1689 return bRet;
1690 }
1691
_LoadDspCodeToSDRAM(MS_U8 code_n)1692 static MS_BOOL _LoadDspCodeToSDRAM(MS_U8 code_n)
1693 {
1694 MS_BOOL bRet = true;
1695 #ifdef MS_DEBUG
1696 MS_U32 u32tmm_7 = 0, u32tmm_8 = 0;
1697 #endif
1698
1699 #ifdef MS_DEBUG
1700 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1701 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]LoadDspCodeToSDRAM, code_n=0x%x\n",code_n));
1702 u32tmm_7 = MsOS_GetSystemTime();
1703 #endif
1704
1705 if (_sDMD_MSB123xc_InitData.bEnableSPILoadCode)
1706 {
1707 (*_sDMD_MSB123xc_InitData.fpMSB123xc_SPIPAD_En)(TRUE);
1708 // ------disable to use TS_PAD as SSPI_PAD after load code
1709 // [0:0] reg_en_sspi_pad
1710 // [1:1] reg_ts_sspi_en, 1: use TS_PAD as SSPI_PAD
1711 _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900 + (0x3b) * 2, 0x0002);
1712 }
1713
1714 switch(code_n)
1715 {
1716 case MSB123xc_BOOT:
1717 {
1718 // boot code
1719 bRet &= _LoadDspCodeToSDRAM_Boot();
1720 }
1721 break;
1722 case MSB123xc_DVBT2:
1723 {
1724 // dvbt2 code
1725 bRet &= _LoadDspCodeToSDRAM_dvbt2();
1726 }
1727 break;
1728 case MSB123xc_DVBT:
1729 {
1730 // dvbt
1731 bRet &= _LoadDspCodeToSDRAM_dvbt();
1732 }
1733 break;
1734 case MSB123xc_DVBC:
1735 {
1736 // dvbtc
1737 bRet &= _LoadDspCodeToSDRAM_dvbc();
1738 }
1739 break;
1740 case MSB123xc_ALL:
1741 default:
1742 {
1743 // boot+dvbt2+dvbt+dvbc
1744 // boot code
1745 bRet &= _LoadDspCodeToSDRAM_Boot();
1746 // dvbt2
1747 bRet &= _LoadDspCodeToSDRAM_dvbt2();
1748 // dvbt
1749 bRet &= _LoadDspCodeToSDRAM_dvbt();
1750 // dvbtc
1751 bRet &= _LoadDspCodeToSDRAM_dvbc();
1752 }
1753 break;
1754 }
1755
1756 if (_sDMD_MSB123xc_InitData.bEnableSPILoadCode)
1757 {
1758 // ------disable to use TS_PAD as SSPI_PAD after load code
1759 // [0:0] reg_en_sspi_pad
1760 // [1:1] reg_ts_sspi_en, 1: use TS_PAD as SSPI_PAD
1761 _MDrv_DMD_MSB123xc_SetReg2Bytes(0x0900 + (0x3b) * 2, 0x0001);
1762 (*_sDMD_MSB123xc_InitData.fpMSB123xc_SPIPAD_En)(FALSE);
1763 }
1764
1765 #ifdef MS_DEBUG
1766 u32tmm_8 = MsOS_GetSystemTime();
1767 printf("[tmm4]t8-t7 = %ld (%ld - %ld)\n",u32tmm_8-u32tmm_7,u32tmm_8,u32tmm_7);
1768 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]LoadDspCodeToSDRAM, code_n=0x%x, bRet=0x%x\n",code_n,bRet));
1769 #endif
1770
1771 return bRet;
1772 }
1773
_MSB123xc_MEM_switch(MS_U8 mem_type)1774 static MS_BOOL _MSB123xc_MEM_switch(MS_U8 mem_type)
1775 {
1776 MS_BOOL bRet = true;
1777 MS_U8 u8_tmp = 0;
1778 MS_U16 timeout = 0;
1779 #ifdef MS_DEBUG
1780 MS_U32 u32tmm_15 = 0, u32tmm_16 = 0;
1781 #endif
1782
1783 #ifdef MS_DEBUG
1784 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1785 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]MSB123xc_MEM_switch, mem_type=0x%x\n",mem_type));
1786 u32tmm_15 = MsOS_GetSystemTime();
1787 #endif
1788
1789 if(mem_type == 1)
1790 {
1791
1792 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x2B80,0x10);
1793
1794 // SRAM_START_ADDR 0x0000
1795 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1000,0x0000);
1796 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1004,0x0000);
1797
1798 // SRAM_END_ADDR 0x7FFF
1799 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1002,0x0000);
1800 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1006,0x7FFF);
1801
1802 // DRAM_START_ADDR 0x8000
1803 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1008,0x0000);
1804 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x100C,0x8000);
1805
1806
1807 // DRAM_END_ADDR 0xFFFF
1808 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x100A,0x0000);
1809 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x100E,0xFFFF);
1810
1811 // Enable SRAM&SDRAM memory map
1812 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1018,0x05);
1813
1814 // Wait memory map to be enabled
1815 do
1816 {
1817 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x1018,&u8_tmp);
1818 if(timeout++ > 500)
1819 {
1820 printf("@msb123xc, D+S memory mapping failure.!!!\n");
1821 return FALSE;
1822 }
1823 }
1824 while(u8_tmp != 0x05);
1825 }
1826 else if(mem_type == 0)
1827 {
1828 // Enable SRAM&SDRAM memory map
1829
1830 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x2B80,0x10);
1831
1832 // DRAM_START_ADDR 0x8000
1833 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x1008,0x0000);
1834 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x100C,0x0000);
1835
1836
1837 // DRAM_END_ADDR 0xFFFF
1838 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x100A,0x0000);
1839 bRet &= _MDrv_DMD_MSB123xc_SetReg2Bytes(0x100E,0x7FFF);
1840
1841 // Enable SRAM&SDRAM memory map
1842 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1018,0x04);
1843
1844 // Wait memory map to be enabled
1845 do
1846 {
1847 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x1018,&u8_tmp);
1848 if(timeout++ > 500)
1849 {
1850 printf("@msb123xc, D memory mapping failure.!!!\n");
1851 return FALSE;
1852 }
1853 }
1854 while(u8_tmp != 0x04);
1855 }
1856 else
1857 {
1858 printf("@msb123xc, invalid mem type mapping.\n");
1859 return FALSE;
1860 }
1861
1862 #ifdef MS_DEBUG
1863 u32tmm_16 = MsOS_GetSystemTime();
1864 printf("[tmm8]t16-t15 = %ld (%ld - %ld)\n",u32tmm_16-u32tmm_15,u32tmm_16,u32tmm_15);
1865 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]MSB123xc_MEM_switch, , mem_type=0x%x, bRet=0x%x\n",mem_type,bRet));
1866 #endif
1867
1868 return bRet;
1869 }
1870
_LoadSdram2Sram(MS_U8 CodeNum)1871 static MS_BOOL _LoadSdram2Sram(MS_U8 CodeNum)
1872 {
1873 MS_BOOL bRet = true;
1874 MS_U8 u8_tmp = 0;
1875 MS_U8 u8DoneFlag = 0;
1876 MS_U32 u32Timeout = 0;
1877 #ifdef MS_DEBUG
1878 MS_U32 u32tmm_17 = 0, u32tmm_18 = 0;
1879 #endif
1880
1881 #ifdef MS_DEBUG
1882 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1883 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]LoadSdram2Sram, g_sram_code=0x%x, codeNum=0x%x\n",u8DMD_MSB123xc_Sram_Code,CodeNum));
1884 u32tmm_17 = MsOS_GetSystemTime();
1885 #endif
1886
1887 if(CodeNum == u8DMD_MSB123xc_Sram_Code)
1888 {
1889 #ifdef MS_DEBUG
1890 printf("[msb123xc]LoadSdram2Sram, code is available.\n");
1891 #endif
1892 return bRet;
1893 }
1894
1895 bRet &= _MSB123xc_MEM_switch(0);
1896
1897 if(CodeNum == MSB123xc_DVBT2)
1898 u8_tmp = 1|0x10;
1899 else if(CodeNum == MSB123xc_DVBT)
1900 u8_tmp = 2|0x10;
1901 else if(CodeNum == MSB123xc_DVBC)
1902 u8_tmp = 3|0x10;
1903 else
1904 u8_tmp = 0|0x10;
1905
1906 // Assign f/w code type to load => 0x11: dvbt2, 0x12: dvbt, 0x13: dvbc
1907 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x0900+(0x4f)*2, u8_tmp);
1908
1909 // enable miu mask, miu, mcu, gdma
1910 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2 + 1,0x0f);
1911 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2,0xf0);
1912
1913 MsOS_DelayTaskUs(10);
1914 // enable mcu
1915 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x0b00+(0x19)*2, 0x00);
1916
1917 do
1918 {
1919 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x4f)*2, &u8DoneFlag);
1920
1921 if (u32Timeout++ > 500)
1922 {
1923 printf("@msb123xc, LoadSdram2Sram boot move code fail.!!!\n");
1924 return FALSE;
1925 }
1926 MsOS_DelayTaskUs(1*1000);
1927
1928 }
1929 while(u8DoneFlag != 0xaa);
1930
1931 // mask miu access of mcu
1932 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2,0xf2);
1933
1934 // 10us delay
1935 MsOS_DelayTaskUs(10);
1936
1937 // Disable MCU
1938 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x0b00+(0x19)*2, 0x03);
1939
1940 // enable miu mask, miu, mcu, gdma
1941 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2 + 1,0x0f);
1942 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2,0xf0);
1943
1944 bRet &= _MSB123xc_MEM_switch(1);
1945
1946 if(bRet == FALSE)
1947 {
1948 u8DMD_MSB123xc_Sram_Code = 0x00;
1949 }
1950 else
1951 {
1952 u8DMD_MSB123xc_Sram_Code = CodeNum;
1953 }
1954
1955 #ifdef MS_DEBUG
1956 u32tmm_18 = MsOS_GetSystemTime();
1957 printf("[tmm9]t18-t17 = %ld (%ld - %ld)\n",u32tmm_18-u32tmm_17,u32tmm_18,u32tmm_17);
1958 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]LoadSdram2Sram, codeNum=0x%x, g_sram_code=0x%x, bRet=0x%x\n",CodeNum,u8DMD_MSB123xc_Sram_Code,bRet));
1959 #endif
1960
1961 return bRet;
1962 }
1963
_DTV_DVBC_DSPReg_Init(void)1964 static MS_BOOL _DTV_DVBC_DSPReg_Init(void)
1965 {
1966 MS_U8 idx = 0;
1967
1968 #ifdef MS_DEBUG
1969 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1970 #endif
1971 for (idx = 0; idx<((MS_U8)DVBC_PARAM_LEN - (MS_U8)C_opmode_rfagc_en); idx++)
1972 {
1973 if( _MDrv_DMD_MSB123xc_SetDSPReg(idx + (MS_U8)C_opmode_rfagc_en, MSB123xc_DVBC_DSPREG_TABLE[idx])!=TRUE)
1974 {
1975 #ifdef MS_DEBUG
1976 ERR_DOMOD_MSB(printf("dsp reg init NG\n"));
1977 #endif
1978 return FALSE;
1979 }
1980 }
1981
1982 #ifdef MS_DEBUG
1983 ERR_DOMOD_MSB(printf("DVBC dsp reg init ok\n"));
1984 #endif
1985
1986 return TRUE;
1987 }
1988
1989
_DTV_DVBT_DSPReg_CRC(void)1990 static MS_U8 _DTV_DVBT_DSPReg_CRC(void)
1991 {
1992 MS_U8 crc = 0;
1993 MS_U8 idx = 0;
1994
1995 #ifdef MS_DEBUG
1996 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1997 #endif
1998 for (idx = 0; idx<(sizeof(MSB123xc_DVBT_DSPREG_TABLE)); idx++)
1999 {
2000 crc ^= MSB123xc_DVBT_DSPREG_TABLE[idx];
2001 }
2002
2003 crc = ~crc;
2004
2005 return crc;
2006 }
2007
_DTV_DVBT_DSPReg_Init(void)2008 static MS_BOOL _DTV_DVBT_DSPReg_Init(void)
2009 {
2010 //MS_U8 idx = 0;
2011 #ifdef MS_DEBUG
2012 MS_U32 u32tmm_7 = 0, u32tmm_8 = 0;
2013 #endif
2014
2015 #ifdef MS_DEBUG
2016 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2017 u32tmm_7 = MsOS_GetSystemTime();
2018 #endif
2019
2020 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)T_CONFIG_FC_L, MSB123xc_DVBT_DSPREG_TABLE[0x13]) != TRUE)
2021 {
2022 printf("T2 dsp reg init NG\n");
2023 }
2024 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)T_CONFIG_FC_H, MSB123xc_DVBT_DSPREG_TABLE[0x14]) != TRUE)
2025 {
2026 printf("T2 dsp reg init NG\n");
2027 }
2028 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)T_CONFIG_BW, MSB123xc_DVBT_DSPREG_TABLE[0x17]) != TRUE)
2029 {
2030 printf("T2 dsp reg init NG\n");
2031 }
2032 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)T_CONFIG_IQ_SWAP, MSB123xc_DVBT_DSPREG_TABLE[0x1F]) != TRUE)
2033 {
2034 printf("T2 dsp reg init NG\n");
2035 }
2036 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)T_CONFIG_TS_SERIAL, MSB123xc_DVBT_DSPREG_TABLE[0x2B]) != TRUE)
2037 {
2038 printf("T2 dsp reg init NG\n");
2039 }
2040 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)T_CONFIG_TS_CLK_RATE, MSB123xc_DVBT_DSPREG_TABLE[0x2C]) != TRUE)
2041 {
2042 printf("T2 dsp reg init NG\n");
2043 }
2044 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)T_CONFIG_TS_OUT_INV, MSB123xc_DVBT_DSPREG_TABLE[0x2D]) != TRUE)
2045 {
2046 printf("T2 dsp reg init NG\n");
2047 }
2048 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)T_CONFIG_TS_DATA_SWAP, MSB123xc_DVBT_DSPREG_TABLE[0x2E]) != TRUE)
2049 {
2050 printf("T2 dsp reg init NG\n");
2051 }
2052
2053
2054 /*
2055 for (idx = 0; idx<((MS_U8)DVBT_PARAM_LEN - (MS_U8)T_OPMODE_RFAGC_EN - 1); idx++)
2056 {
2057 if( _MDrv_DMD_MSB123xc_SetDSPReg(idx + (MS_U8)T_OPMODE_RFAGC_EN, MSB123xc_DVBT_DSPREG_TABLE[idx])!=TRUE)
2058 {
2059 printf("dsp reg init NG\n");
2060 return FALSE;
2061 }
2062 }
2063
2064 #ifdef MS_DEBUG
2065 u32tmm_8 = MsOS_GetSystemTime();
2066 printf("[1111]t8 - t7 = %ld (%ld - %ld) \n",u32tmm_8-u32tmm_7,u32tmm_8,u32tmm_7);
2067 u32tmm_7 = MsOS_GetSystemTime();
2068 #endif
2069
2070 MSB123xc_DVBT_DSPREG_TABLE[(MS_U8)T_PARAM_CHECK_SUM-(MS_U8)T_OPMODE_RFAGC_EN] = _DTV_DVBT_DSPReg_CRC();
2071
2072 #ifdef MS_DEBUG
2073 u32tmm_8 = MsOS_GetSystemTime();
2074 printf("[2222]t8 - t7 = %ld (%ld - %ld) \n",u32tmm_8-u32tmm_7,u32tmm_8,u32tmm_7);
2075 u32tmm_7 = MsOS_GetSystemTime();
2076 #endif
2077
2078 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)T_PARAM_CHECK_SUM, MSB123xc_DVBT_DSPREG_TABLE[(MS_U8)T_PARAM_CHECK_SUM-(MS_U8)T_OPMODE_RFAGC_EN])!=TRUE)
2079 {
2080 printf("dsp reg write crc NG\n");
2081 return FALSE;
2082 }
2083 */
2084 #ifdef MS_DEBUG
2085 u32tmm_8 = MsOS_GetSystemTime();
2086 printf("[3333]t8 - t7 = %ld (%ld - %ld) \n",u32tmm_8-u32tmm_7,u32tmm_8,u32tmm_7);
2087 #endif
2088
2089 printf("dvbt dsp reg init ok\n");
2090
2091 return TRUE;
2092 }
2093
_DTV_DVBT2_DSPReg_Init(void)2094 static MS_BOOL _DTV_DVBT2_DSPReg_Init(void)
2095 {
2096 #ifdef MS_DEBUG
2097 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2098 #endif
2099
2100 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)E_T2_BW, MSB123xc_DVBT2_DSPREG_TABLE[0]) != TRUE)
2101 {
2102 printf("T2 dsp reg init NG\n");
2103 }
2104 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)E_T2_FC_L, MSB123xc_DVBT2_DSPREG_TABLE[1]) != TRUE)
2105 {
2106 printf("T2 dsp reg init NG\n");
2107 }
2108 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)E_T2_FC_H, MSB123xc_DVBT2_DSPREG_TABLE[2]) != TRUE)
2109 {
2110 printf("T2 dsp reg init NG\n");
2111 }
2112 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)E_T2_TS_SERIAL, MSB123xc_DVBT2_DSPREG_TABLE[3]) != TRUE)
2113 {
2114 printf("T2 dsp reg init NG\n");
2115 }
2116 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)E_T2_TS_CLK_RATE, MSB123xc_DVBT2_DSPREG_TABLE[4]) != TRUE)
2117 {
2118 printf("T2 dsp reg init NG\n");
2119 }
2120 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)E_T2_TS_OUT_INV, MSB123xc_DVBT2_DSPREG_TABLE[5]) != TRUE)
2121 {
2122 printf("T2 dsp reg init NG\n");
2123 }
2124 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)E_T2_TS_DATA_SWAP, MSB123xc_DVBT2_DSPREG_TABLE[6]) != TRUE)
2125 {
2126 printf("T2 dsp reg init NG\n");
2127 }
2128 if( _MDrv_DMD_MSB123xc_SetDSPReg((MS_U8)E_T2_TS_ERR_POL, MSB123xc_DVBT2_DSPREG_TABLE[7]) != TRUE)
2129 {
2130 printf("T2 dsp reg init NG\n");
2131 }
2132
2133 printf("T2 dsp reg init ok\n");
2134
2135 return TRUE;
2136 }
2137
_LoadDSPCode(void)2138 static MS_BOOL _LoadDSPCode(void)
2139 {
2140 ////MAPI_U32 u32Now = MsOS_GetSystemTime();
2141 //printf("\t\t\tLoadDSPCode TIME %ld (=%ld-%ld)\n", u32Now-u32StartTime, u32Now, u32StartTime);
2142 ////DBG_DOMOD_MSB(printf("\t\t\tLoadDSPCode TIME %ld (=%ld-%ld)\n", u32Now-u32StartTime, u32Now, u32StartTime));//to measure time
2143 //u32StartTime = u32Now;
2144
2145 MS_U32 u32Timeout = 0;
2146 MS_U8 u8DoneFlag = 0;
2147 MS_U8 u8Data = 0;
2148 MS_BOOL bRet = true;
2149 #ifdef MS_DEBUG
2150 MS_U32 u32tmm_9 = 0, u32tmm_10 = 0, u32tmm_11 = 0, u32tmm_12 = 0, u32tmm_13 = 0;
2151 #endif
2152
2153 #ifdef MS_DEBUG
2154 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2155 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]LoadDspCode\n"));
2156 DBG_DOMOD_MSB(printf(">>>MSB123xc: Load DSP...\n"));
2157 #endif
2158
2159 switch(eDMD_MSB123xc_CurrentDemodulatorType)
2160 {
2161 case E_DMD_MSB123xc_DEMOD_DVBT2:
2162 u8Data=1;
2163 break;
2164 case E_DMD_MSB123xc_DEMOD_DVBT:
2165 u8Data=2;
2166 break;
2167 case E_DMD_MSB123xc_DEMOD_DVBC:
2168 u8Data=3;
2169 break;
2170 default:
2171 u8Data=2;
2172 return FALSE;
2173 }
2174
2175 if(_sDMD_MSB123xc_InitData.u8WO_SPI_Flash == 1)
2176 {
2177 MS_U8 u8FirmwareType = MSB123xc_DVBT;
2178
2179 #ifdef MS_DEBUG
2180 u32tmm_11 = MsOS_GetSystemTime();
2181 #endif
2182
2183 switch (u8Data)
2184 {
2185 case 1:
2186 u8FirmwareType = MSB123xc_DVBT2;
2187 break;
2188 case 2:
2189 default:
2190 u8FirmwareType = MSB123xc_DVBT;
2191 break;
2192 case 3:
2193 u8FirmwareType = MSB123xc_DVBC;
2194 break;
2195 }
2196
2197 bRet &= _LoadDspCodeToSDRAM(u8FirmwareType);
2198
2199 // mask miu access for all and mcu
2200 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2 + 1,0x7f);
2201 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2,0xfe);
2202 // 10us delay
2203 MsOS_DelayTaskUs(10);
2204
2205 // Disable MCU
2206 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x0b00+(0x19)*2, 0x03);
2207
2208 bRet &= _LoadSdram2Sram(u8FirmwareType);
2209
2210 // enable miu access of mcu gdma
2211 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2,0xf0);
2212 // 10us delay
2213 MsOS_DelayTaskUs(10);
2214
2215 // Enable MCU
2216 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x0b00+(0x19)*2, 0x00);
2217 }
2218 else
2219 {
2220 #ifdef MS_DEBUG
2221 u32tmm_9 = MsOS_GetSystemTime();
2222 #endif
2223 // mask miu access for all and mcu
2224 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2 + 1,0x7f);
2225 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2,0xfe);
2226 // 10us delay
2227 MsOS_DelayTaskUs(10);
2228
2229 // Disable MCU
2230 _MDrv_DMD_MSB123xc_SetReg(0x0b00+(0x19)*2, 0x03);
2231
2232 // Run code on bootloader
2233 _MDrv_DMD_MSB123xc_SetReg(0x1000+(0x0c)*2, 0x02);
2234
2235 // Assign f/w code type to load => 0: boot-loader 1: dvbt2, 2: dvbt, 3: dvbc
2236 _MDrv_DMD_MSB123xc_SetReg(0x0900 + (0x4f) * 2, u8Data);
2237
2238
2239 // enable miu access of mcu gdma
2240 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2,0xf0);
2241 // 10us delay
2242 MsOS_DelayTaskUs(10);
2243
2244 // Enable MCU
2245 _MDrv_DMD_MSB123xc_SetReg(0x0b00+(0x19)*2, 0x00);
2246
2247 #ifdef MS_DEBUG
2248 u32tmm_10 = MsOS_GetSystemTime();
2249 printf("[tmm8]t10 - t9 = %ld (%ld - %ld)\n",u32tmm_10-u32tmm_9,u32tmm_10,u32tmm_9);
2250 #endif
2251
2252
2253 do
2254 {
2255 _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x4f)*2, &u8DoneFlag);
2256
2257 if (u32Timeout++ > 500)
2258 return FALSE;
2259
2260 MsOS_DelayTaskUs(1*1000);
2261
2262 }
2263 while(u8DoneFlag != 0xaa);
2264
2265 #ifdef MS_DEBUG
2266 u32tmm_11 = MsOS_GetSystemTime();
2267 printf("[tmm8]t11 - t10 = %ld (%ld - %ld)\n",u32tmm_11-u32tmm_10,u32tmm_11,u32tmm_10);
2268 #endif
2269
2270 // mask miu access for all and mcu
2271 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2 + 1,0x7f);
2272 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2,0xfe);
2273 // 10us delay
2274 MsOS_DelayTaskUs(10);
2275
2276 // Disable MCU
2277 _MDrv_DMD_MSB123xc_SetReg(0x0b00+(0x19)*2, 0x03);
2278
2279 // Run code on loaded firmware
2280 _MDrv_DMD_MSB123xc_SetReg(0x1000+(0x0c)*2, 0x05);
2281
2282 do
2283 {
2284 _MDrv_DMD_MSB123xc_GetReg(0x1000+(0x0c)*2, &u8DoneFlag);
2285
2286 if (u32Timeout++ > 500)
2287 return FALSE;
2288
2289 MsOS_DelayTaskUs(1*1000);
2290
2291 }
2292 while(u8DoneFlag != 0x05);
2293
2294 // enable miu access of mcu gdma
2295 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x1200+(0x23)*2,0xf0);
2296 // 10us delay
2297 MsOS_DelayTaskUs(10);
2298
2299 // Enable MCU
2300 _MDrv_DMD_MSB123xc_SetReg(0x0b00+(0x19)*2, 0x00);
2301 }
2302
2303 #ifdef MS_DEBUG
2304 u32tmm_12 = MsOS_GetSystemTime();
2305 printf("[tmm8]t12 - t11 = %ld (%ld - %ld), TYPE is %d \n",u32tmm_12-u32tmm_11,u32tmm_12,u32tmm_11, eDMD_MSB123xc_CurrentDemodulatorType);
2306 #endif
2307
2308 switch(eDMD_MSB123xc_CurrentDemodulatorType)
2309 {
2310 case E_DMD_MSB123xc_DEMOD_DVBT2:
2311 _DTV_DVBT2_DSPReg_Init();
2312 break;
2313 case E_DMD_MSB123xc_DEMOD_DVBT:
2314 _DTV_DVBT_DSPReg_Init();
2315 break;
2316 case E_DMD_MSB123xc_DEMOD_DVBC://mick
2317 _DTV_DVBC_DSPReg_Init();
2318 break;
2319 default:
2320 return FALSE;
2321 }
2322
2323 #ifdef MS_DEBUG
2324 u32tmm_13 = MsOS_GetSystemTime();
2325 printf("[tmm8]t13 - t12 = %ld (%ld - %ld)\n",u32tmm_13-u32tmm_12,u32tmm_13,u32tmm_12);
2326 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]LoadDspCode\n"));
2327 #endif
2328
2329 return bRet;
2330 }
2331
_msb123xc_flash_mode_en(void)2332 static MS_BOOL _msb123xc_flash_mode_en(void)
2333 {
2334 MS_BOOL bRet = TRUE;
2335 MS_U8 data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
2336 MS_U8 u8MsbData[6] = {0};
2337 MS_U8 ch_num = 3;
2338 MS_U8 u8Data = 0;
2339 MS_U16 u16Addr = 0;
2340 MS_U8 retry_num = MSB123xc_MAX_FLASH_ON_RETRY_NUM;
2341
2342 #ifdef MS_DEBUG
2343 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]msb123xc_flash_mode_en\n"));
2344 #endif
2345
2346 do
2347 {
2348
2349 if (retry_num != MSB123xc_MAX_FLASH_ON_RETRY_NUM)
2350 {
2351 #ifdef MS_DEBUG
2352 ERR_DOMOD_MSB(printf("[msb123xc][error]flash mode en fail.....retry=%d\n",retry_num);)
2353 #endif
2354 }
2355 // bRet = TRUE;
2356 // password
2357 // 8'hb2(SRID)->8,h53(PWD1)->8,h45(PWD2)->8,h52(PWD3)->8,h44(PWD4)->8,h42(PWD5)
2358 data[0] = 0x53;
2359 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, data);
2360
2361 // 8'hb2(SRID)->8,h71(CMD) //TV.n_iic_
2362 data[0] = 0x71;
2363 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
2364
2365 // 8'hb2(SRID)->8,h81(CMD) //TV.n_iic_sel_b0
2366 data[0] = ((ch_num & 0x01) != 0)? 0x81 : 0x80;
2367 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
2368
2369 // 8'hb2(SRID)->8,h83(CMD) //TV.n_iic_sel_b1
2370 data[0] = ((ch_num & 0x02) != 0)? 0x83 : 0x82;
2371 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
2372
2373 // 8'hb2(SRID)->8,h84(CMD) //TV.n_iic_sel_b2
2374 data[0] = ((ch_num & 0x04) != 0)? 0x85 : 0x84;
2375 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
2376
2377 // 8'hb2(SRID)->8,h53(CMD) //TV.n_iic_ad_byte_en2, 32bit read/write
2378 data[0] = 0x53;
2379 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
2380
2381 // 8'hb2(SRID)->8,h7f(CMD) //TV.n_iic_sel_use_cfg
2382 data[0] = 0x7f;
2383 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
2384
2385 /*
2386 // 8'hb2(SRID)->8,h35(CMD) //TV.n_iic_use
2387 data[0] = 0x35;
2388 bRet &= iptr->WriteBytes(0, NULL, 1, data);
2389
2390 // 8'hb2(SRID)->8,h71(CMD) //TV.n_iic_Re-shape
2391 data[0] = 0x71;
2392 bRet &= iptr->WriteBytes(0, NULL, 1, data);
2393 */
2394 bRet = TRUE;
2395
2396 // confirm first, 0x99 and 0xaa.
2397 // beg read register
2398 u16Addr = 0x0900+(0x4f<<1);
2399 u8Data = 0x0;
2400
2401 u8MsbData[0] = 0x10;
2402 u8MsbData[1] = 0x00;
2403 u8MsbData[2] = 0x00;
2404 u8MsbData[3] = (u16Addr >> 8) &0xff;
2405 u8MsbData[4] = u16Addr &0xff;
2406
2407 u8MsbData[0] = 0x35;
2408 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2409
2410 u8MsbData[0] = 0x10;
2411 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
2412 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 0, NULL, 1, &u8Data);
2413
2414 u8MsbData[0] = 0x34;
2415 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2416 // end read register
2417
2418 if ((u8Data == 0x99) || (u8Data == 0xaa))
2419 {
2420 #ifdef MS_DEBUG
2421 ERR_DOMOD_MSB(printf("[msb123xc][warning]flash is already on....\n");)
2422 #endif
2423 break;
2424 }
2425 // flash mode enable.
2426 // beg read register
2427 u16Addr = 0x0900+(0x28<<1)+1;
2428 u8Data = 0x0;
2429
2430 u8MsbData[0] = 0x10;
2431 u8MsbData[1] = 0x00;
2432 u8MsbData[2] = 0x00;
2433 u8MsbData[3] = (u16Addr >> 8) &0xff;
2434 u8MsbData[4] = u16Addr &0xff;
2435
2436 u8MsbData[0] = 0x35;
2437
2438 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2439
2440
2441
2442 u8MsbData[0] = 0x10;
2443 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
2444 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 0, NULL, 1, &u8Data);
2445
2446 u8MsbData[0] = 0x34;
2447 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2448 // end read register
2449
2450 // beg write register
2451 u16Addr = 0x0900+(0x28<<1) + 1;
2452 u8Data &= (0xff-0x01);
2453
2454 u8MsbData[0] = 0x10;
2455 u8MsbData[1] = 0x00;
2456 u8MsbData[2] = 0x00;
2457 u8MsbData[3] = (u16Addr >> 8) &0xff;
2458 u8MsbData[4] = u16Addr &0xff;
2459 u8MsbData[5] = u8Data;
2460
2461 u8MsbData[0] = 0x35;
2462 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2463
2464 u8MsbData[0] = 0x10;
2465 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
2466
2467 u8MsbData[0] = 0x34;
2468 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2469 // end write register
2470
2471 // beg write register
2472 u16Addr = 0x0900+(0x06<<1);
2473 u8Data = 0x10;
2474
2475 u8MsbData[0] = 0x10;
2476 u8MsbData[1] = 0x00;
2477 u8MsbData[2] = 0x00;
2478 u8MsbData[3] = (u16Addr >> 8) &0xff;
2479 u8MsbData[4] = u16Addr &0xff;
2480 u8MsbData[5] = u8Data;
2481
2482 u8MsbData[0] = 0x35;
2483 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2484
2485 u8MsbData[0] = 0x10;
2486 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
2487
2488 u8MsbData[0] = 0x34;
2489 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2490 // end write register
2491
2492 // beg write register
2493
2494 u16Addr = 0x0900+(0x07<<1);
2495 u8Data = 0x10;
2496
2497 u8MsbData[0] = 0x10;
2498 u8MsbData[1] = 0x00;
2499 u8MsbData[2] = 0x00;
2500 u8MsbData[3] = (u16Addr >> 8) &0xff;
2501 u8MsbData[4] = u16Addr &0xff;
2502 u8MsbData[5] = u8Data;
2503
2504 u8MsbData[0] = 0x35;
2505 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2506
2507 u8MsbData[0] = 0x10;
2508 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
2509
2510 u8MsbData[0] = 0x34;
2511 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2512 }
2513 while( (bRet == FALSE) && (retry_num-- != 0));
2514 // end write register
2515
2516 #ifdef MS_DEBUG
2517 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]msb123xc_flash_mode_en,bRet=%d\n",bRet));
2518 #endif
2519
2520 return bRet;
2521 }
2522
_msb123xc_flash_boot_ready_waiting(MS_U8 * ptimeout)2523 static MS_BOOL _msb123xc_flash_boot_ready_waiting(MS_U8 *ptimeout)
2524 {
2525
2526 MS_BOOL bRet = TRUE;
2527 // MAPI_U8 data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
2528 MS_U8 u8MsbData[6] = {0};
2529 MS_U8 u8Data = 0;
2530 MS_U16 u16Addr = 0;
2531 MS_U8 u8_timeout = 0;
2532
2533 #ifdef MS_DEBUG
2534 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][beg]msb123xc_flash_boot_ready_waiting\n"));
2535 #endif
2536
2537 // wait for flash->dram ready.
2538 // read register
2539
2540 u16Addr = 0x0900+(0x4f<<1);
2541 u8Data = 0x0;
2542
2543 u8MsbData[0] = 0x10;
2544 u8MsbData[1] = 0x00;
2545 u8MsbData[2] = 0x00;
2546 u8MsbData[3] = (u16Addr >> 8) &0xff;
2547 u8MsbData[4] = u16Addr &0xff;
2548
2549 u8_timeout = 0xff;
2550
2551 while( (u8Data != 0x99) && (u8Data != 0xaa) && (u8_timeout-->0))
2552 {
2553 u8MsbData[0] = 0x35;
2554 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2555
2556 u8MsbData[0] = 0x10;
2557 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
2558 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 0, NULL, 1, &u8Data);
2559
2560 u8MsbData[0] = 0x34;
2561 bRet &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2562 // 10ms
2563 MsOS_DelayTaskUs(1000*10);
2564 }
2565 // end read register
2566 *ptimeout = 0;
2567 if (u8_timeout == 0x00)
2568 {
2569 *ptimeout = 1;
2570 #ifdef MS_DEBUG
2571 ERR_DOMOD_MSB(printf("[msb123xc][error]msb123xc_flash_boot_ready_waiting, timeout....\n");)
2572 #endif
2573 }
2574
2575 #ifdef MS_DEBUG
2576 DBG_DEMOD_LOAD_I2C(printf("[msb123xc][end]msb123xc_flash_boot_ready_waiting, t=%d\n",u8_timeout));
2577 #endif
2578 return bRet;
2579 }
2580
_msb123xc_flash_WP_reg_read(MS_U16 u16Addr,MS_U8 * pu8Data)2581 static MS_BOOL _msb123xc_flash_WP_reg_read(MS_U16 u16Addr, MS_U8 *pu8Data)
2582 {
2583 MS_BOOL bRet;
2584 MS_U8 u8MsbData[5];
2585
2586 u8MsbData[0] = 0x10;
2587 u8MsbData[1] = 0x00;
2588 u8MsbData[2] = 0x00;
2589 u8MsbData[3] = (u16Addr >> 8) &0xff;
2590 u8MsbData[4] = u16Addr &0xff;
2591
2592 u8MsbData[0] = 0x35;
2593 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2594
2595 u8MsbData[0] = 0x10;
2596 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
2597 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 0, NULL, 1, pu8Data);
2598
2599 u8MsbData[0] = 0x34;
2600 bRet=(*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2601 return bRet;
2602 }
2603
_msb123xc_flash_WP_reg_write(MS_U16 u16Addr,MS_U8 u8Data)2604 static MS_BOOL _msb123xc_flash_WP_reg_write(MS_U16 u16Addr, MS_U8 u8Data)
2605 {
2606 MS_BOOL bRet;
2607 MS_U8 u8MsbData[6];
2608
2609 //bRet &= iptr->SetSpeed(0);
2610
2611
2612 u8MsbData[0] = 0x10;
2613 u8MsbData[1] = 0x00;
2614 u8MsbData[2] = 0x00;
2615 u8MsbData[3] = (u16Addr >> 8) &0xff;
2616 u8MsbData[4] = u16Addr &0xff;
2617 u8MsbData[5] = u8Data;
2618
2619 u8MsbData[0] = 0x35;
2620 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2621
2622 u8MsbData[0] = 0x10;
2623 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
2624
2625 u8MsbData[0] = 0x34;
2626 bRet=(*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
2627 return bRet;
2628 }
2629
_msbMSB123xc_flash_WRSR(MS_U8 reg)2630 static MS_BOOL _msbMSB123xc_flash_WRSR(MS_U8 reg)
2631 {
2632 MS_U8 bWriteData[5]= {0x4D, 0x53, 0x54, 0x41, 0x52};
2633 MS_U8 bAddr[1];
2634 MS_BOOL bRet = TRUE;
2635
2636 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, bWriteData);
2637
2638 // WREN
2639 bAddr[0] = 0x10;
2640 bWriteData[0] = 0x06;
2641 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
2642
2643 bWriteData[0] = 0x12;
2644 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
2645
2646 // WRSR
2647 bAddr[0] = 0x10;
2648 bWriteData[0] = 0x01;
2649 bWriteData[1] = reg;
2650 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 2, bWriteData);
2651
2652 bWriteData[0] = 0x12;
2653 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
2654
2655 // WRDI
2656 bAddr[0] = 0x10;
2657 bWriteData[0] = 0x04;
2658 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
2659
2660 bWriteData[0] = 0x12;
2661 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
2662
2663 // end
2664 bWriteData[0] = 0x24;
2665 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
2666
2667 #ifdef MS_DEBUG
2668 DBG_FLASH_WP(printf("[wb]msbMSB123xc_flash_WRSR, reg=0x%x\n",reg);)
2669 #endif
2670
2671 return bRet;
2672 }
2673
_msbMSB123xc_flash_SRSR(MS_U8 * p_reg)2674 static MS_BOOL _msbMSB123xc_flash_SRSR(MS_U8 *p_reg)
2675 {
2676 MS_U8 bWriteData[5]= {0x4D, 0x53, 0x54, 0x41, 0x52};
2677 MS_U8 bAddr[1];
2678 MS_BOOL bRet = TRUE;
2679
2680 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, bWriteData);
2681
2682 bAddr[0] = 0x10;
2683 bWriteData[0] = 0x05;
2684 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
2685
2686 bAddr[0] = 0x11;
2687 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 1, bAddr, 1, p_reg);
2688
2689 bWriteData[0] = 0x12;
2690 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
2691
2692 // end
2693 bWriteData[0] = 0x24 ;
2694 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
2695
2696 #ifdef MS_DEBUG
2697 DBG_FLASH_WP(printf("[wb]msbMSB123xc_flash_SRSR, reg=0x%x\n",*p_reg);)
2698 #endif
2699
2700 return bRet;
2701 }
2702
_msb123xc_flash_WP(MS_U8 enable)2703 static MS_BOOL _msb123xc_flash_WP(MS_U8 enable)
2704 #if 0
2705 {
2706 MAPI_U8 reg = 0;
2707 MAPI_BOOL bRet = true;
2708 MAPI_U8 u8_count = 0;
2709
2710 DBG_FLASH_WP(printf("[wb]msb1233c_flash_WP_Enable=%d\n",enable);)
2711
2712 if (enable == 1)
2713 {
2714 u8_count = 20;
2715 do
2716 {
2717 msb1233c_flash_SRSR(®);
2718 usleep(1*1000);
2719 }
2720 while(reg&0x01 && u8_count--);
2721
2722 if (u8_count == 0)
2723 {
2724 bRet = false;
2725 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
2726 return bRet;
2727 }
2728
2729 msb1233c_flash_WRSR(reg|0x9c);
2730
2731
2732 u8_count = 20;
2733 do
2734 {
2735 msb1233c_flash_SRSR(®);
2736 usleep(1*1000);
2737 }
2738 while(reg&0x01 && u8_count--);
2739
2740 if (u8_count == 0)
2741 {
2742 bRet = false;
2743 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
2744 return bRet;
2745 }
2746
2747 // active low
2748 // pull low
2749 bRet &= msb1233c_flash_WP_reg_read(0x0900+0x63*2+1, ®);
2750 bRet &= msb1233c_flash_WP_reg_write(0x0900+0x63*2+1, reg&(~0x08));
2751
2752 // gpio11 output enable
2753 bRet &= msb1233c_flash_WP_reg_read(0x0900+0x64*2+1, ®);
2754 bRet &= msb1233c_flash_WP_reg_write(0x0900+0x64*2+1, reg&(~0x08));
2755 }
2756 else
2757 {
2758 // unactive high
2759 // pull high
2760 bRet &= msb1233c_flash_WP_reg_read(0x0900+0x63*2+1, ®);
2761 bRet &= msb1233c_flash_WP_reg_write(0x0900+0x63*2+1, reg|0x08);
2762
2763 // gpio11 output enable
2764 bRet &= msb1233c_flash_WP_reg_read(0x0900+0x64*2+1, ®);
2765 bRet &= msb1233c_flash_WP_reg_write(0x0900+0x64*2+1, reg&(~0x08));
2766
2767 u8_count = 20;
2768 do
2769 {
2770 msb1233c_flash_SRSR(®);
2771 usleep(1*1000);
2772 }
2773 while(reg&0x01 && u8_count--);
2774
2775 if (u8_count == 0)
2776 {
2777 bRet = false;
2778 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
2779 return bRet;
2780 }
2781
2782 msb1233c_flash_WRSR(reg&(~0x9c));
2783
2784 u8_count = 20;
2785 do
2786 {
2787 msb1233c_flash_SRSR(®);
2788 usleep(1*1000);
2789 }
2790 while(reg&0x01 && u8_count--);
2791
2792 if (u8_count == 0)
2793 {
2794 bRet = false;
2795 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
2796 return bRet;
2797 }
2798 }
2799
2800 return bRet;
2801 }
2802 #else
2803 {
2804 MS_U8 reg = 0;
2805 MS_BOOL bRet = TRUE;
2806 MS_U8 u8_count = 0;
2807
2808 #ifdef MS_DEBUG
2809 DBG_FLASH_WP(printf("[wb]msb123xc_flash_WP_Enable=%d\n",enable);)
2810 #endif
2811
2812 if (enable == 1)
2813 {
2814 u8_count = 20;
2815 do
2816 {
2817 _msbMSB123xc_flash_SRSR(®);
2818 MsOS_DelayTaskUs(1*1000);
2819 }
2820 while(reg&0x01 && u8_count--);
2821
2822 if (u8_count == 0)
2823 {
2824 bRet = FALSE;
2825 #ifdef MS_DEBUG
2826 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
2827 #endif
2828 return bRet;
2829 }
2830
2831 _msbMSB123xc_flash_WRSR(reg|0x9c);
2832 u8_count = 20;
2833
2834 do
2835 {
2836 _msbMSB123xc_flash_SRSR(®);
2837 MsOS_DelayTaskUs(1*1000);
2838 }
2839 while(reg&0x01 && u8_count--);
2840
2841 if (u8_count == 0)
2842 {
2843 bRet = FALSE;
2844 #ifdef MS_DEBUG
2845 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
2846 #endif
2847 return bRet;
2848 }
2849
2850 // active low
2851 // pull low
2852 bRet &= _msb123xc_flash_WP_reg_read(0x0A00+0x22*2, ®);
2853 bRet &= _msb123xc_flash_WP_reg_write(0x0A00+0x22*2, reg&(~0x01));
2854 // gpio11 output enable
2855 bRet &= _msb123xc_flash_WP_reg_read(0x0A00+0x22*2, ®);
2856 bRet &= _msb123xc_flash_WP_reg_write(0x0A00+0x22*2, reg&(~0x02));
2857 }
2858 else
2859 {
2860 // unactive high
2861 // pull high
2862 bRet &= _msb123xc_flash_WP_reg_read(0x0A00+0x22*2, ®);
2863 bRet &= _msb123xc_flash_WP_reg_write(0x0A00+0x22*2, reg|0x01);
2864 // gpio11 output enable
2865 bRet &= _msb123xc_flash_WP_reg_read(0x0A00+0x22*2, ®);
2866 bRet &= _msb123xc_flash_WP_reg_write(0x0A00+0x22*2, reg&(~0x02));
2867 u8_count = 20;
2868
2869 do
2870 {
2871 _msbMSB123xc_flash_SRSR(®);
2872 MsOS_DelayTaskUs(1*1000);
2873 }
2874 while(reg&0x01 && u8_count--);
2875
2876 if (u8_count == 0)
2877 {
2878 bRet = FALSE;
2879 #ifdef MS_DEBUG
2880 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
2881 #endif
2882 return bRet;
2883 }
2884 _msbMSB123xc_flash_WRSR(reg&(~0x9c));
2885 u8_count = 20;
2886
2887 do
2888 {
2889 _msbMSB123xc_flash_SRSR(®);
2890 MsOS_DelayTaskUs(1*1000);
2891 }
2892 while(reg&0x01 && u8_count--);
2893
2894 if (u8_count == 0)
2895 {
2896 bRet = FALSE;
2897 #ifdef MS_DEBUG
2898 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
2899 #endif
2900 return bRet;
2901 }
2902 }
2903 return bRet;
2904 }
2905 #endif
2906
2907 MS_U8 _MSB123xc_CHIP_MATCH_TABLE[] =
2908 {
2909 //Kaiser, Kaiserin, Keltic, Kronus, Kappa , Clippers, keres
2910 0x56, 0x41, 0x72, 0x2F, 0x75, 0x86, 0x7E
2911 };
2912
_msbMSB123xc_set_bonding_option(MS_U16 u16ChipID)2913 static MS_BOOL _msbMSB123xc_set_bonding_option(MS_U16 u16ChipID)
2914 {
2915 MS_BOOL bRet = TRUE;
2916 MS_U8 u8Idx;
2917 MS_U8 u8MatchFlag = 0;
2918 MS_U8 u8Data = 0;
2919 MS_U32 u32_timeout = 0;
2920 #ifdef MS_DEBUG
2921 DBG_DOMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2922 #endif
2923
2924 printf("_msbMSB123xc_set_bonding_option u16ChipID %x\n", u16ChipID);
2925
2926 for (u8Idx = 0 ; u8Idx < sizeof( _MSB123xc_CHIP_MATCH_TABLE) ; u8Idx++)
2927 {
2928 if(u16ChipID == _MSB123xc_CHIP_MATCH_TABLE[u8Idx])
2929 {
2930 printf("_MSB123xc_CHIP_MATCH_TABLE matched!\n");
2931 u8MatchFlag = 0x01;
2932 break;
2933 }
2934 else
2935 {
2936 printf("_MSB123xc_CHIP_MATCH_TABLE did not matched!\n");
2937 u8MatchFlag = 0x00;
2938 }
2939 }
2940
2941 if (_MSB123xc_I2C_CH_Reset(3) == FALSE)
2942 {
2943 #ifdef MS_DEBUG
2944 ERR_DOMOD_MSB(printf(">>>MSB123xc CH3 Reset:Fail\n"));
2945 #endif
2946 printf(">>>MSB123xc CH3 Reset:Fail\n");
2947 return FALSE;
2948 }
2949
2950 // MSB123xc : 0x0902[8]=0 , 0x0902[0]=0;
2951 // MSB1235 : 0x0902[8]=1 , 0x0902[0]=1; (before overwrite, SDRAM not enable)
2952 // 0x0902[8]=1 , 0x0902[0]=0; (after overwrite, SDRAM enable)
2953 // check bonding value, 0x0902[8]
2954 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x02)*2+1, &u8Data);
2955 if((u8Data & 0x01) == 0x01) //for MSB1236C
2956 {
2957 if(u8MatchFlag == 0x01)
2958 {
2959 //check overwrite or not
2960 //0x0902[0] : reg_bonding[0]
2961 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x02)*2, &u8Data);
2962 if((u8Data & 0x01) != 0x00)
2963 {
2964 //0x0905[0] : reg_bond_ov_en[0] = 1
2965 //0x0905[8] : reg_bond_ov[0] = 0
2966 // set overwrite enable
2967 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x0900+(0x05)*2, 0x01);
2968 // set overwrite value
2969 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x0900+(0x05)*2+1, 0x00);
2970 }
2971
2972 do
2973 {
2974 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x02)*2, &u8Data);
2975 if(u32_timeout++ > 500)
2976 {
2977 #ifdef MS_DEBUG
2978 ERR_DOMOD_MSB(printf("@msb1236c, Set bonding option failure.!!!\n"));
2979 #endif
2980 return FALSE;
2981 }
2982 }
2983 while((u8Data & 0x01) == 0x01);
2984
2985 #ifdef MS_DEBUG
2986 printf("@ Set bonding option for MSB1236 \n");
2987 #endif
2988 }
2989 else
2990 {
2991 return FALSE;
2992 }
2993 }
2994 else // for MSB123xc
2995 {
2996 //check overwrite or not
2997 //0x0902[0] : reg_bonding[0]
2998 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x02)*2, &u8Data);
2999 if((u8Data & 0x01) != 0x00)
3000 {
3001 //0x0905[0] : reg_bond_ov_en[0] = 1
3002 //0x0905[8] : reg_bond_ov[0] = 0
3003 // set overwrite enable
3004 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x0900+(0x05)*2, 0x01);
3005 // set overwrite value
3006 bRet &= _MDrv_DMD_MSB123xc_SetReg(0x0900+(0x05)*2+1, 0x00);
3007 }
3008
3009 do
3010 {
3011 bRet &= _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x02)*2, &u8Data);
3012 if(u32_timeout++ > 500)
3013 {
3014 #ifdef MS_DEBUG
3015 ERR_DOMOD_MSB(printf("@msbMSB123xc, Set bonding option failure.!!!\n"));
3016 #endif
3017 return FALSE;
3018 }
3019 }
3020 while((u8Data & 0x01) == 0x01);
3021
3022 #ifdef MS_DEBUG
3023 printf("@ Set bonding option for MSB123xc \n");
3024 #endif
3025 }
3026
3027 #ifdef MS_DEBUG
3028 if (!bRet) printf("%s %d Error\n", __func__, __LINE__);
3029 #endif
3030 return bRet;
3031 }
3032
_IspCheckVer(MS_U8 * pLibData,MS_BOOL * pMatch)3033 static MS_BOOL _IspCheckVer(MS_U8* pLibData, MS_BOOL* pMatch)
3034 {
3035 MS_U8 bReadData[VERSION_CODE_SIZE];
3036 MS_U32 indx = 0;
3037 *pMatch = true;
3038
3039 MS_U8 bWriteData[5] = {0x4D, 0x53, 0x54, 0x41, 0x52};
3040 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, bWriteData);
3041
3042 MS_U8 bAddr[1], bError = true;
3043 //MAPI_U16 Count;
3044
3045 memset(bReadData, 0 , sizeof(bReadData));
3046
3047 bAddr[0] = 0x10;
3048 //dwStartAddr=0;
3049
3050 bWriteData[0] = 0x03;
3051 bWriteData[1] = VERSION_CODE_ADDR >> 16;
3052 bWriteData[2] = VERSION_CODE_ADDR >> 8;
3053 bWriteData[3] = VERSION_CODE_ADDR & 0xFF;
3054
3055 bError &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 4, bWriteData);
3056
3057 bAddr[0] = 0x11;
3058 bError &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 1, bAddr, VERSION_CODE_SIZE, bReadData);
3059
3060 bWriteData[0] = 0x12;
3061 bError &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3062
3063 if(FALSE == bError)
3064 {
3065 bWriteData[0] = 0x24 ;
3066 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3067 return FALSE;
3068 }
3069
3070 bWriteData[0] = 0x24 ;
3071 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3072
3073 printf("sttest version data = ");
3074 for(indx = 0; indx < (VERSION_CODE_SIZE); indx++)
3075 {
3076 printf(" %x ,", bReadData[indx]);
3077 if(pLibData[indx+VERSION_CODE_ADDR] != bReadData[indx])
3078 {
3079 *pMatch = FALSE;
3080 //break;
3081 }
3082 }
3083 printf(" \n");
3084
3085 return TRUE;
3086 }
3087
_dram_crc_check(MS_U16 chksum_lib,MS_BOOL * pMatch)3088 static MS_BOOL _dram_crc_check(MS_U16 chksum_lib, MS_BOOL* pMatch)
3089 {
3090 MS_U16 chksum = 0;
3091 // MAPI_U16 chksum_lib = 0;
3092 MS_U16 u16Addr = 0;
3093 MS_U8 u8MsbData[5];
3094 MS_U8 reg = 0;
3095 MS_BOOL bRet;
3096 MS_U8 mcu_status = 0;
3097
3098 *pMatch = false;
3099
3100 // MAPI_U8 bWriteData[5]={0x4D, 0x53, 0x54, 0x41, 0x52};
3101 // iptr->WriteBytes(0, NULL, 5, bWriteData);
3102
3103 /// crc H byte
3104 u16Addr = 0x0c00+0x0d*2+1;
3105
3106 u8MsbData[0] = 0x10;
3107 u8MsbData[1] = 0x00;
3108 u8MsbData[2] = 0x00;
3109 u8MsbData[3] = (u16Addr >> 8) &0xff;
3110 u8MsbData[4] = u16Addr &0xff;
3111
3112 u8MsbData[0] = 0x35;
3113 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3114
3115 u8MsbData[0] = 0x10;
3116 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
3117 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 0, NULL, 1, ®);
3118
3119 u8MsbData[0] = 0x34;
3120 bRet=(*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3121
3122
3123 chksum = reg;
3124
3125 /// crc L byte
3126 u16Addr = 0x0c00+0x0d*2;
3127
3128 u8MsbData[0] = 0x10;
3129 u8MsbData[1] = 0x00;
3130 u8MsbData[2] = 0x00;
3131 u8MsbData[3] = (u16Addr >> 8) &0xff;
3132 u8MsbData[4] = u16Addr &0xff;
3133
3134 u8MsbData[0] = 0x35;
3135 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3136
3137 u8MsbData[0] = 0x10;
3138 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
3139 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 0, NULL, 1, ®);
3140
3141 u8MsbData[0] = 0x34;
3142 bRet=(*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3143
3144
3145 chksum = (chksum<<8)|reg;
3146
3147 // get mcu status
3148
3149 u16Addr = 0x0900+0x4f*2;
3150
3151 u8MsbData[0] = 0x10;
3152 u8MsbData[1] = 0x00;
3153 u8MsbData[2] = 0x00;
3154 u8MsbData[3] = (u16Addr >> 8) &0xff;
3155 u8MsbData[4] = u16Addr &0xff;
3156
3157 u8MsbData[0] = 0x35;
3158 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3159
3160 u8MsbData[0] = 0x10;
3161 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
3162 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 0, NULL, 1, ®);
3163
3164 u8MsbData[0] = 0x34;
3165 bRet=(*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3166
3167
3168 mcu_status = reg;
3169
3170
3171 /// check the crc in dsp lib array
3172
3173 if (mcu_status == 0xaa && ((chksum_lib&0xff00) == (chksum&0xff00)) )
3174 *pMatch = true;
3175 else if(chksum_lib == chksum)
3176 *pMatch = true;
3177
3178 #ifdef MS_DEBUG
3179 printf("[crc]chksum_lib=0x%x, chksum=0x%x, bRet=%d, Match=%d, mcu_status=0x%x\n",chksum_lib,chksum,bRet,*pMatch,mcu_status);
3180 #endif
3181
3182 return bRet;
3183 }
3184
_IspProcFlash(MS_U8 * pLibArry,MS_U32 dwLibSize)3185 static MS_BOOL _IspProcFlash(MS_U8* pLibArry, MS_U32 dwLibSize)
3186 {
3187 MS_U32 dwLoop, dwTimeOut;
3188 MS_U32 dwStartAddr, dwEndAddr;
3189 //MAPI_U16 wLoop;
3190 MS_U8 bError = false;//, bWriteData[PAGE_WRITE_SIZE];
3191
3192 MS_U8 bWriteData[5]= {0x4D, 0x53, 0x54, 0x41, 0x52};
3193 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, bWriteData);
3194
3195 dwStartAddr = (MS_U32) 0;
3196 dwEndAddr = dwLibSize;
3197
3198
3199 MS_U8 bAddr[1];
3200 MS_U8 bReadData=0;
3201 for(dwLoop=dwStartAddr; (dwLoop < dwEndAddr); dwLoop+=PAGE_WRITE_SIZE)
3202 {
3203
3204 dwTimeOut = 10000;
3205
3206 while(dwTimeOut--)
3207 {
3208 bAddr[0] = 0x10;
3209 bWriteData[0] = 0x05;
3210 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
3211
3212 bAddr[0] = 0x11;
3213 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_READ_BYTES, 1, bAddr, 1, &bReadData);
3214
3215 bWriteData[0] = 0x12;
3216 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3217
3218 if (!(bReadData & 0x01))
3219 break;
3220
3221 if(dwTimeOut==1)
3222 {
3223 bError = 1;
3224 break;
3225 }
3226 MsOS_DelayTaskUs(0);
3227 }
3228
3229 if(!bError)
3230 {
3231
3232 MS_U8 bAddr[5], bWriteData[1];
3233 MS_BOOL bError = TRUE;
3234
3235 bAddr[0] = 0x10;
3236 bWriteData[0] = 0x06;
3237 bError &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
3238
3239 bWriteData[0] = 0x12;
3240 bError &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3241
3242 // Page Program
3243 bAddr[0] = 0x10;
3244 bAddr[1] = 0x02;
3245 bAddr[2] = dwLoop >> 16;
3246 bAddr[3] = dwLoop >> 8;
3247 bAddr[4] = dwLoop;
3248
3249 bError &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 5, bAddr, PAGE_WRITE_SIZE, (pLibArry+dwLoop));
3250
3251 bWriteData[0] = 0x12;
3252 bError &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3253
3254 bAddr[0] = 0x10;
3255 bWriteData[0] = 0x04;
3256 bError &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
3257
3258 bWriteData[0] = 0x12;
3259 bError &= (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3260
3261 if(bError == FALSE)
3262 {
3263 break;
3264 }
3265 }
3266 }
3267
3268 bWriteData[0]=0x24 ;
3269 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3270
3271 if(bError==FALSE)
3272 return TRUE;
3273 else
3274 return FALSE;
3275
3276 }
3277
MDrv_DMD_MSB123xc_SetCurrentDemodulatorType(eDMD_MSB123xc_DemodulatorType eCurrentDemodulatorType)3278 void MDrv_DMD_MSB123xc_SetCurrentDemodulatorType(eDMD_MSB123xc_DemodulatorType eCurrentDemodulatorType)
3279 {
3280 #ifdef MS_DEBUG
3281 printf("MDrv_DMD_MSB123xc_SetCurrentDemodulatorType %d\n", eCurrentDemodulatorType);
3282 #endif
3283 eDMD_MSB123xc_CurrentDemodulatorType = eCurrentDemodulatorType;
3284 }
3285
MDrv_DMD_MSB123xc_LoadDSPCode(void)3286 MS_BOOL MDrv_DMD_MSB123xc_LoadDSPCode(void)
3287 {
3288 MS_BOOL bRet = TRUE;
3289 DMD_LOCK();
3290 bRet = _LoadDSPCode();
3291 DMD_UNLOCK();
3292 return bRet;
3293 }
MDrv_DMD_MSB123xc_DTV_DVBT_DSPReg_CRC(void)3294 MS_BOOL MDrv_DMD_MSB123xc_DTV_DVBT_DSPReg_CRC(void)
3295 {
3296 MS_BOOL bRet = TRUE;
3297 DMD_LOCK();
3298 bRet = _DTV_DVBT_DSPReg_CRC();
3299 DMD_UNLOCK();
3300 return bRet;
3301 }
3302
MDrv_DMD_MSB123xc_Power_On_Initialization(void)3303 MS_BOOL MDrv_DMD_MSB123xc_Power_On_Initialization(void)
3304 {
3305 MS_U8 status = TRUE;
3306 MS_BOOL bMatch = false;
3307 MS_U8 u8RetryCnt = 6;
3308 #ifdef MS_DEBUG
3309 MS_U32 u32tmm_1, u32tmm_2, u32tmm_3, u32tmm_4, u32tmm_5, u32tmm_6 = 0x00;
3310 #endif
3311
3312 DMD_LOCK();
3313 #ifdef MS_DEBUG
3314 u32tmm_1 = MsOS_GetSystemTime();
3315 #endif
3316
3317 if (_sDMD_MSB123xc_InitData.bPreloadDSPCodeFromMainCHIPI2C)
3318 {
3319 DMD_UNLOCK();
3320 return TRUE;
3321 }
3322
3323 #ifdef MS_DEBUG
3324 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
3325 {
3326 printf(">>>MSB123xc: Enter Power_On_Initialization()\n");
3327 }
3328 #endif
3329
3330 if ( _msbMSB123xc_set_bonding_option( MDrv_SYS_GetChipID() ) == FALSE )
3331 {
3332 DMD_UNLOCK();
3333 return TRUE;
3334 }
3335
3336 if (bDMD_MSB123xc_Power_init_en == TRUE)
3337 {
3338 DMD_UNLOCK();
3339 return TRUE;
3340 }
3341 else
3342 {
3343 bDMD_MSB123xc_Power_init_en = (u8DMD_MSB123xc_PowerOnInitialization_Flow == 2) ? (TRUE) : (FALSE);
3344 }
3345
3346 if(_sDMD_MSB123xc_InitData.u8WO_SPI_Flash== 1)
3347 {
3348 if (_sDMD_MSB123xc_InitData.bPreloadDSPCodeFromMainCHIPI2C)
3349 {
3350
3351 }
3352 else
3353 {
3354 //status &= _MSB123xc_I2C_CH_Reset(3);
3355 status &= _MSB123xc_HW_init();
3356 status &= _LoadDspCodeToSDRAM(MSB123xc_ALL);
3357 if (_LoadDSPCode() == FALSE)
3358 {
3359 printf(">>>>MSB123xc:Fail\n");
3360 status= FALSE;
3361 }
3362 }
3363 }
3364 else
3365 {
3366 #ifdef MS_DEBUG
3367 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
3368 {
3369 printf("u8DMD_MSB123xc_PowerOnInitialization_Flow = %d\n", u8DMD_MSB123xc_PowerOnInitialization_Flow);
3370 }
3371 #endif
3372 if(u8DMD_MSB123xc_PowerOnInitialization_Flow ==0)
3373 {
3374 status = _msb123xc_flash_mode_en();
3375 if (status == FALSE)
3376 {
3377 printf("[msb123xc][error]msb123xc_flash_mode_en fail....\n");
3378 }
3379 u8DMD_MSB123xc_PowerOnInitialization_Flow++;
3380 }
3381 else
3382 {
3383 if(u8DMD_MSB123xc_PowerOnInitialization_Flow<2)
3384 {
3385 u8DMD_MSB123xc_PowerOnInitialization_Flow++;
3386 }
3387
3388 MS_U8 u8DoneFlag = 0;
3389 MS_U16 u16_counter = 0;
3390
3391 MS_U16 crc16 = 0;
3392
3393 crc16 = MSB123xc_LIB[sizeof(MSB123xc_LIB)-2];
3394 crc16 = (crc16<<8)|MSB123xc_LIB[sizeof(MSB123xc_LIB)-1];
3395
3396 do
3397 {
3398 printf(">>>MSB123xc: u8RetryCnt = %d\n",u8RetryCnt);
3399
3400 MS_U8 flash_waiting_ready_timeout = 0;
3401 u8RetryCnt--;
3402
3403 #ifdef MS_DEBUG
3404 u32tmm_3 = MsOS_GetSystemTime();
3405 #endif
3406
3407 status = _msb123xc_flash_boot_ready_waiting(&flash_waiting_ready_timeout);
3408 if ( (flash_waiting_ready_timeout == 1) || (status == FALSE) )
3409 {
3410 printf("[msb123xc][error]msb123xc_flash_boot_ready_waiting fail....\n");
3411 }
3412
3413 #ifdef MS_DEBUG
3414 u32tmm_4 = MsOS_GetSystemTime();
3415 printf("[tmm1]t4-t3 = %ld (%ld - %ld)\n",u32tmm_4-u32tmm_3,u32tmm_4,u32tmm_3);
3416 #endif
3417
3418 if(status == FALSE)
3419 {
3420 if (_sDMD_MSB123xc_InitData.fpGPIOReset != NULL)
3421 {
3422 #ifdef MS_DEBUG
3423 printf(">>>MSB123xc: Reset Demodulator\n");
3424 #endif
3425 (*_sDMD_MSB123xc_InitData.fpGPIOReset)(FALSE); // gptr->SetOff();
3426 MsOS_DelayTaskUs(resetDemodTime*1000);
3427 (*_sDMD_MSB123xc_InitData.fpGPIOReset)(TRUE); // gptr->SetOn();
3428 MsOS_DelayTaskUs(waitFlashTime * 1000);
3429 }
3430
3431 if (_MSB123xc_I2C_CH_Reset(3) == FALSE)
3432 {
3433 printf(">>>MSB123xc CH Reset:Fail\n");
3434 status= FALSE;
3435 continue;
3436 }
3437
3438 u16_counter = 1000;
3439 do
3440 {
3441 // 10 ms
3442 MsOS_DelayTaskUs(10*1000);
3443 u16_counter--;
3444 _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x4f)*2, &u8DoneFlag);
3445 }
3446 while(u8DoneFlag != 0x99 && u16_counter != 0);
3447
3448 if(u16_counter == 0 && u8DoneFlag != 0x99)
3449 {
3450 printf("[wb]Err, MSB123xc didn't ready yet\n");
3451 status = false;
3452 }
3453 else
3454 {
3455 status = TRUE;
3456 }
3457
3458 }
3459 // No need to switch to CH0 before SPI Flash access.
3460
3461 {
3462 #ifdef MS_DEBUG
3463 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
3464 {
3465 printf(">>>MSB123xc: Check Version...");
3466 }
3467 #endif
3468
3469 if (_IspCheckVer(MSB123xc_LIB, &bMatch) == FALSE)
3470 {
3471 printf(">>> ISP read FAIL!\n");
3472 status= FALSE;
3473 continue;
3474 }
3475
3476
3477 if(bMatch == FALSE)
3478 {
3479 printf(">>> IspCheckVer FAIL!\n");
3480 }
3481 else
3482 {
3483 if (_MSB123xc_I2C_CH_Reset(3) == FALSE)
3484 {
3485 printf(">>>MSB123xc CH Reset:Fail\n");
3486 status= FALSE;
3487 continue;
3488 }
3489 else
3490 {
3491 #ifdef MS_DEBUG
3492 if (eDMD_MSB123xc_DbgLevel >= E_DMD_MSB123xc_DBGLV_DEBUG)
3493 {
3494 printf(">>>MSB123xc CH Reset:OK\n");
3495 }
3496 #endif
3497 }
3498
3499 if (_dram_crc_check(crc16, &bMatch) == FALSE)
3500 {
3501 printf(">>> reg read fail!\n");
3502 status= FALSE;
3503 continue;
3504 }
3505
3506 if(bMatch == FALSE)
3507 printf(">>> dram crc check FAIL!\n");
3508 else
3509 printf(">>> dram crc check OK!\n");
3510
3511
3512 }
3513
3514 if (_sDMD_MSB123xc_InitData.bFlashWPEnable)
3515 {
3516 if (bMatch == FALSE)
3517 {
3518 // disable flash WP, pull high.
3519 if(_msb123xc_flash_WP(0) == FALSE)
3520 {
3521 printf("[wb]Err, FLASH WP Disable Fail!!!\n");
3522 }
3523 MsOS_DelayTaskUs(100*1000);
3524 }
3525 }
3526
3527 ////bMatch = true; //FIXME : Remove this to enable auto FW reload.
3528 if (bMatch == FALSE)// Version not match
3529 {
3530 MS_U8 bAddr[1];
3531 MS_U8 bWriteData[5]= {0x4D, 0x53, 0x54, 0x41, 0x52};
3532
3533 printf(">>> Not match! Reload Flash...");
3534 if ( (sizeof(MSB123xc_LIB)%256) != 0)
3535 {
3536 printf(" MSB123xc_LIB 256byte alignment error!%u \n",sizeof(MSB123xc_LIB));
3537 }
3538
3539 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, bWriteData);
3540
3541 bAddr[0] = 0x10;
3542 bWriteData[0] = 0x06;
3543 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
3544
3545 bWriteData[0] = 0x12;
3546 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3547
3548 bAddr[0] = 0x10;
3549
3550 bWriteData[0] = 0xC7;
3551 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
3552
3553 bWriteData[0] = 0x12;
3554 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3555
3556 bWriteData[0]=0x24 ;
3557 (*_sDMD_MSB123xc_InitData.fpMSB123xc_I2C_Access)(E_DMD_MSB123xc_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB123xc_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3558
3559 #ifdef MS_DEBUG
3560 printf("\t\t\tStart %ld\n", MsOS_GetSystemTime());
3561 #endif
3562 if ( (sizeof(MSB123xc_LIB) - 2) > MAX_MSB123xc_LIB_LEN)
3563 {
3564 printf("Err, msb123xcc_lib size(%d) is larger than flash size(%d)\n", sizeof(MSB123xc_LIB), MAX_MSB123xc_LIB_LEN);
3565 }
3566
3567 // if (IspProcFlash(MSB123xc_LIB, sizeof(MSB123xc_LIB)) == MAPI_FALSE)
3568 if (_IspProcFlash(MSB123xc_LIB, sizeof(MSB123xc_LIB)-2) == FALSE)
3569 {
3570 printf("ISP write FAIL\n");
3571 status= FALSE;
3572 continue;
3573 }
3574 else
3575 {
3576 #ifdef MS_DEBUG
3577 printf("\t\t\tEnd %ld\n", MsOS_GetSystemTime());
3578 #endif
3579 //check again
3580 if ((_IspCheckVer(MSB123xc_LIB, &bMatch) == FALSE)||(bMatch==false))
3581 {
3582 printf(">>> ISP read FAIL! bMatch %d \n",bMatch);
3583 status= FALSE;
3584 continue;
3585 }
3586 else // reset again
3587 {
3588 if (_sDMD_MSB123xc_InitData.fpGPIOReset != NULL)
3589 {
3590 #ifdef MS_DEBUG
3591 printf(">>>MSB123xc[2]: Reset Demodulator\n");
3592 #endif
3593 (*_sDMD_MSB123xc_InitData.fpGPIOReset)(FALSE); // gptr->SetOff();
3594 MsOS_DelayTaskUs(resetDemodTime*1000);
3595 (*_sDMD_MSB123xc_InitData.fpGPIOReset)(TRUE); // gptr->SetOn();
3596 MsOS_DelayTaskUs(waitFlashTime * 1000);
3597 }
3598
3599 if (_MSB123xc_I2C_CH_Reset(3) == FALSE)
3600 {
3601 printf(">>>MSB123xc CH Reset:Fail\n");
3602 status= FALSE;
3603 continue;
3604 }
3605
3606 u16_counter = 1000;
3607 do
3608 {
3609 // 10 ms
3610 MsOS_DelayTaskUs(10*1000);
3611 u16_counter--;
3612 _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x4f)*2, &u8DoneFlag);
3613 }
3614 while(u8DoneFlag != 0x99 && u16_counter != 0);
3615
3616 if(u16_counter == 0 && u8DoneFlag != 0x99)
3617 {
3618 printf("[wb]Err, MSB123xc didn't ready yet\n");
3619 status = FALSE;
3620 }
3621 else
3622 status = TRUE;
3623
3624 if (_MSB123xc_I2C_CH_Reset(3) == FALSE)
3625 {
3626 printf(">>>MSB123xc CH Reset:Fail\n");
3627 status= FALSE;
3628 continue;
3629 }
3630 else
3631 {
3632 printf(">>>MSB123xc CH Reset:OK\n");
3633 }
3634
3635 if (_dram_crc_check(crc16, &bMatch) == FALSE)
3636 {
3637 printf(">>> reg read fail!\n");
3638 status= FALSE;
3639 continue;
3640 }
3641
3642 if(bMatch == false)
3643 printf(">>> dram crc check FAIL!\n");
3644 else
3645 printf(">>> dram crc check OK!\n");
3646 }
3647 #ifdef MS_DEBUG
3648 printf(" OK\n");
3649 #endif
3650 }
3651 }
3652 else
3653 {
3654 // Version match, do nothing
3655 #ifdef MS_DEBUG
3656 printf(">>> Match\n");
3657 #endif
3658 } // if (bMatch == false)
3659
3660 if (_sDMD_MSB123xc_InitData.bFlashWPEnable)
3661 {
3662 if (bMatch == TRUE)
3663 {
3664 // Enable flash WP, pull high.
3665 if(_msb123xc_flash_WP(1) == FALSE)
3666 {
3667 printf("[wb]Err, FLASH WP Enable Fail!!!\n");
3668 }
3669 MsOS_DelayTaskUs(100*1000);
3670 }
3671 } // bFlashWPEnable
3672 }
3673
3674
3675 if (_MSB123xc_I2C_CH_Reset(3) == FALSE)
3676 {
3677 printf(">>>MSB123xc CH Reset:Fail\n");
3678 status= FALSE;
3679 continue;
3680 }
3681 else
3682 {
3683 #ifdef MS_DEBUG
3684 printf(">>>MSB123xc CH Reset:OK\n");
3685 #endif
3686 }
3687
3688 #ifdef MS_DEBUG
3689 u32tmm_5 = MsOS_GetSystemTime();
3690 #endif
3691
3692 if (_LoadDSPCode() == FALSE)
3693 {
3694 printf(">>>>MSB123xc:Fail\n");
3695 status= FALSE;
3696 continue;
3697 }
3698 else
3699 {
3700 #ifdef MS_DEBUG
3701 printf(">>>MSB123xc:OK\n");
3702 #endif
3703 }
3704
3705 #ifdef MS_DEBUG
3706 u32tmm_6 = MsOS_GetSystemTime();
3707 printf("[tmm1]t6-t5 = %ld (%ld - %ld)\n",u32tmm_6-u32tmm_5,u32tmm_6,u32tmm_5);
3708 #endif
3709
3710 #ifdef MS_DEBUG
3711 {
3712 MS_U8 u8ChipRevId = 0;
3713 _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x01)*2, &u8ChipRevId);
3714 printf(">>>MSB123xc:Edinburgh RevID:%x\n", u8ChipRevId);
3715
3716
3717 _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x49)*2, &u8ChipRevId);
3718 printf(">>>MSB123xc:Edinburgh 0x49_L:%x\n", u8ChipRevId);
3719
3720 _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x49)*2+1, &u8ChipRevId);
3721 printf(">>>MSB123xc:Edinburgh 0x49_H:%x\n", u8ChipRevId);
3722
3723 _MDrv_DMD_MSB123xc_GetReg(0x0900+(0x4A)*2, &u8ChipRevId);
3724 printf(">>>MSB123xc:Edinburgh 0x4A_L:%x\n", u8ChipRevId);
3725 }
3726 #endif
3727 }
3728 while((u8RetryCnt>0)&&(status==FALSE));
3729 }
3730 }
3731
3732 if(status==FALSE)
3733 {
3734 printf("msb123xc power_on_init FAIL !!!!!! \n\n");
3735 }
3736 else
3737 {
3738 #ifdef MS_DEBUG
3739 printf("msb123xc power_on_init OK !!!!!! \n\n");
3740 u32tmm_2 = MsOS_GetSystemTime();
3741 printf("[tmm]t2-t1 = %ld (%ld - %ld)\n",u32tmm_2-u32tmm_1,u32tmm_2,u32tmm_1);
3742 #endif
3743 }
3744
3745 DMD_UNLOCK();
3746 return status;
3747 }
3748
3749
3750