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MStar hereby reserves the 91*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom. 92*53ee8cc1Swenshuai.xi // 93*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 94*53ee8cc1Swenshuai.xi 95*53ee8cc1Swenshuai.xi /////////////////////////////////////////////////////////////////////////////////////////////////// 96*53ee8cc1Swenshuai.xi /// 97*53ee8cc1Swenshuai.xi /// @file drvDMD.h 98*53ee8cc1Swenshuai.xi /// @brief DVBC Demodulator Driver Interface 99*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor,Inc. 100*53ee8cc1Swenshuai.xi /////////////////////////////////////////////////////////////////////////////////////////////////// 101*53ee8cc1Swenshuai.xi 102*53ee8cc1Swenshuai.xi #ifndef _DRV_DMD_H_ 103*53ee8cc1Swenshuai.xi #define _DRV_DMD_H_ 104*53ee8cc1Swenshuai.xi 105*53ee8cc1Swenshuai.xi 106*53ee8cc1Swenshuai.xi 107*53ee8cc1Swenshuai.xi #ifdef __cplusplus 108*53ee8cc1Swenshuai.xi extern "C" 109*53ee8cc1Swenshuai.xi { 110*53ee8cc1Swenshuai.xi #endif 111*53ee8cc1Swenshuai.xi 112*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 113*53ee8cc1Swenshuai.xi // Driver Capability 114*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 115*53ee8cc1Swenshuai.xi 116*53ee8cc1Swenshuai.xi 117*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 118*53ee8cc1Swenshuai.xi // Macro and Define 119*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 120*53ee8cc1Swenshuai.xi 121*53ee8cc1Swenshuai.xi 122*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 123*53ee8cc1Swenshuai.xi // Type and Structure 124*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 125*53ee8cc1Swenshuai.xi 126*53ee8cc1Swenshuai.xi /// Mdulation constellation scheme 127*53ee8cc1Swenshuai.xi typedef enum _DMD_QamType 128*53ee8cc1Swenshuai.xi { 129*53ee8cc1Swenshuai.xi E_DMD_QAM16 = 0, ///< QAM 16 130*53ee8cc1Swenshuai.xi E_DMD_QAM32 = 1, ///< QAM 32 131*53ee8cc1Swenshuai.xi E_DMD_QAM64 = 2, ///< QAM 64 132*53ee8cc1Swenshuai.xi E_DMD_QAM128 = 3, ///< QAM 128 133*53ee8cc1Swenshuai.xi E_DMD_QAM256 = 4, ///< QAM 256 134*53ee8cc1Swenshuai.xi 135*53ee8cc1Swenshuai.xi E_DMD_QAM_LASTNUM, 136*53ee8cc1Swenshuai.xi } __attribute__((packed)) DMD_QAMType; 137*53ee8cc1Swenshuai.xi 138*53ee8cc1Swenshuai.xi /// Demodulation IQ type 139*53ee8cc1Swenshuai.xi typedef enum _DMD_IQType 140*53ee8cc1Swenshuai.xi { 141*53ee8cc1Swenshuai.xi E_DMD_IQ_NORMAL = 0, ///< IQ Normal 142*53ee8cc1Swenshuai.xi E_DMD_IQ_INVERT = 1, ///< IQ Invert 143*53ee8cc1Swenshuai.xi } __attribute__((packed)) DMD_IQType; 144*53ee8cc1Swenshuai.xi 145*53ee8cc1Swenshuai.xi /// Demodulation tap assign 146*53ee8cc1Swenshuai.xi typedef enum _DMD_TapAssign 147*53ee8cc1Swenshuai.xi { 148*53ee8cc1Swenshuai.xi E_DMD_TAP_PRE = 0, ///< PreTap assign 149*53ee8cc1Swenshuai.xi E_DMD_TAP_POST = 1, ///< PostTap assign 150*53ee8cc1Swenshuai.xi } __attribute__((packed)) DMD_TapAssign; 151*53ee8cc1Swenshuai.xi 152*53ee8cc1Swenshuai.xi 153*53ee8cc1Swenshuai.xi #if 1//(FRONTEND_DEMOD_TYPE == DEMOD_MSDVBC) 154*53ee8cc1Swenshuai.xi 155*53ee8cc1Swenshuai.xi /// Demodulator auto tune control 156*53ee8cc1Swenshuai.xi typedef struct 157*53ee8cc1Swenshuai.xi { 158*53ee8cc1Swenshuai.xi // Demodulator option 159*53ee8cc1Swenshuai.xi MS_BOOL bX4CFE_en; ///< Carrier frequency estimation 160*53ee8cc1Swenshuai.xi MS_BOOL bPPD_en; ///< Tap assign estimation 161*53ee8cc1Swenshuai.xi MS_BOOL bIQAutoSwap_en; ///< IQ mode auto swap 162*53ee8cc1Swenshuai.xi MS_BOOL bQAMScan_en; ///< QAM type auto scan 163*53ee8cc1Swenshuai.xi MS_BOOL bFHO_en; ///< FHO 164*53ee8cc1Swenshuai.xi MS_BOOL (*fptTunerSet)(MS_U32); ///< Tuner set freq function pointer 165*53ee8cc1Swenshuai.xi } DMD_Mode; 166*53ee8cc1Swenshuai.xi 167*53ee8cc1Swenshuai.xi /// Demodulator tune parameter 168*53ee8cc1Swenshuai.xi typedef struct 169*53ee8cc1Swenshuai.xi { 170*53ee8cc1Swenshuai.xi // Channel setting 171*53ee8cc1Swenshuai.xi MS_U32 u32SymRate; ///< Symbol rate (Ksym/sec) 172*53ee8cc1Swenshuai.xi 173*53ee8cc1Swenshuai.xi // Channel characteristic 174*53ee8cc1Swenshuai.xi DMD_QAMType eQamType; ///< QAM type 175*53ee8cc1Swenshuai.xi DMD_IQType eIQSwap; ///< IQ type 176*53ee8cc1Swenshuai.xi DMD_TapAssign eTapAssign; ///< Tap assign 177*53ee8cc1Swenshuai.xi MS_U32 u32FreqOffset; ///< Carrier frequency offset 178*53ee8cc1Swenshuai.xi MS_U8 u8TuneFreqOffset; ///< Request Tuner offset 179*53ee8cc1Swenshuai.xi MS_U32 u32TunerFreq; ///< Request Tuner offset 180*53ee8cc1Swenshuai.xi } DMD_Param; 181*53ee8cc1Swenshuai.xi 182*53ee8cc1Swenshuai.xi /// Demodulator special status parameter 183*53ee8cc1Swenshuai.xi typedef struct 184*53ee8cc1Swenshuai.xi { 185*53ee8cc1Swenshuai.xi MS_BOOL bRtyTunerFreq; ///< Tuner freq retry flag 186*53ee8cc1Swenshuai.xi MS_BOOL bRtyTunerOvr; ///< Retry over indicator for freq offset retry 187*53ee8cc1Swenshuai.xi MS_S32 s32TunerFreqOffset; ///< Demod request tuner freq offset 188*53ee8cc1Swenshuai.xi }DMD_Status; 189*53ee8cc1Swenshuai.xi 190*53ee8cc1Swenshuai.xi #else 191*53ee8cc1Swenshuai.xi 192*53ee8cc1Swenshuai.xi typedef struct 193*53ee8cc1Swenshuai.xi { 194*53ee8cc1Swenshuai.xi // N/A 195*53ee8cc1Swenshuai.xi } DMD_Mode; 196*53ee8cc1Swenshuai.xi 197*53ee8cc1Swenshuai.xi // Device dependant parameter 198*53ee8cc1Swenshuai.xi typedef struct 199*53ee8cc1Swenshuai.xi { 200*53ee8cc1Swenshuai.xi // N/A 201*53ee8cc1Swenshuai.xi } DMD_Param; 202*53ee8cc1Swenshuai.xi 203*53ee8cc1Swenshuai.xi typedef struct 204*53ee8cc1Swenshuai.xi { 205*53ee8cc1Swenshuai.xi // N/A 206*53ee8cc1Swenshuai.xi }DMD_Status; 207*53ee8cc1Swenshuai.xi 208*53ee8cc1Swenshuai.xi #endif 209*53ee8cc1Swenshuai.xi 210*53ee8cc1Swenshuai.xi 211*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 212*53ee8cc1Swenshuai.xi // Function and Variable 213*53ee8cc1Swenshuai.xi //------------------------------------------------------------------------------------------------- 214*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_Init(void); 215*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_Open(void); 216*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_Close(void); 217*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_Reset(void); 218*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_Restart(DMD_Param *pParam); 219*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_SetMode(DMD_Mode *pMode); 220*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_TsOut(MS_BOOL bEnable); 221*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_PowerOnOff(MS_BOOL bPowerOn); 222*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_SetBW(MS_U32 u32BW); 223*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_GetBW(MS_U32 *pu32BW); 224*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_GetLock(MS_BOOL *pbLock); 225*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_GetSNR(MS_U32 *pu32SNR); 226*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_GetBER(float *pfBER); 227*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_GetPWR(MS_S32 *ps32Signal); 228*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_GetParam(DMD_Param *pParam); 229*53ee8cc1Swenshuai.xi extern MS_BOOL MDrv_Dmd_Config(MS_U8 *pRegParam); 230*53ee8cc1Swenshuai.xi 231*53ee8cc1Swenshuai.xi #ifdef __cplusplus 232*53ee8cc1Swenshuai.xi } 233*53ee8cc1Swenshuai.xi #endif 234*53ee8cc1Swenshuai.xi 235*53ee8cc1Swenshuai.xi 236*53ee8cc1Swenshuai.xi #endif // _DRV_DMD_H_ 237