xref: /utopia/UTPA2-700.0.x/modules/demodulator/drv/demod/drvDMD_common.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi //<MStar Software>
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93*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
94*53ee8cc1Swenshuai.xi 
95*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
96*53ee8cc1Swenshuai.xi ///
97*53ee8cc1Swenshuai.xi /// file    drvDMD_common.c
98*53ee8cc1Swenshuai.xi /// @brief  DMD Driver Interface
99*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc.
100*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
101*53ee8cc1Swenshuai.xi 
102*53ee8cc1Swenshuai.xi 
103*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
104*53ee8cc1Swenshuai.xi //  Include Files
105*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
106*53ee8cc1Swenshuai.xi // Common Definition
107*53ee8cc1Swenshuai.xi #ifdef MSOS_TYPE_LINUX_KERNEL
108*53ee8cc1Swenshuai.xi #include <linux/string.h>
109*53ee8cc1Swenshuai.xi #else
110*53ee8cc1Swenshuai.xi #include <string.h>
111*53ee8cc1Swenshuai.xi #include <stdio.h>
112*53ee8cc1Swenshuai.xi #include <math.h>
113*53ee8cc1Swenshuai.xi #endif
114*53ee8cc1Swenshuai.xi #include "MsCommon.h"
115*53ee8cc1Swenshuai.xi #include "MsVersion.h"
116*53ee8cc1Swenshuai.xi #include "MsOS.h"
117*53ee8cc1Swenshuai.xi #include "drvSYS.h"
118*53ee8cc1Swenshuai.xi #include "drvDMD_common.h"
119*53ee8cc1Swenshuai.xi #include "halDMD_INTERN_common.h"
120*53ee8cc1Swenshuai.xi #include "drvDMD_VD_MBX.h"
121*53ee8cc1Swenshuai.xi #include "ULog.h"
122*53ee8cc1Swenshuai.xi #include "drvMSPI.h"
123*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
124*53ee8cc1Swenshuai.xi //  Driver Compiler Options
125*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
126*53ee8cc1Swenshuai.xi 
127*53ee8cc1Swenshuai.xi 
128*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
129*53ee8cc1Swenshuai.xi //  Local Defines
130*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
131*53ee8cc1Swenshuai.xi #define SPI_DEVICE_BUFFER_SIZE           256
132*53ee8cc1Swenshuai.xi //////////////MSPI Define//////////////////
133*53ee8cc1Swenshuai.xi #define READ_INDEX  0
134*53ee8cc1Swenshuai.xi #define WRITE_INDEX 1
135*53ee8cc1Swenshuai.xi #define CMD_INDEX 0
136*53ee8cc1Swenshuai.xi #define ADDR_INDEX 1
137*53ee8cc1Swenshuai.xi //SSPI COMMAND
138*53ee8cc1Swenshuai.xi #define RIU_W_CMD      0x1A
139*53ee8cc1Swenshuai.xi #define RIU_W1_CMD     0x1D
140*53ee8cc1Swenshuai.xi #define RIU_R_CMD       0x18
141*53ee8cc1Swenshuai.xi #define RIU_R1_CMD      0x1C
142*53ee8cc1Swenshuai.xi #define RIU_RT_CMD      0x11
143*53ee8cc1Swenshuai.xi #define RIU_R1T_CMD      0x15
144*53ee8cc1Swenshuai.xi #define MIU_W_CMD      0x25
145*53ee8cc1Swenshuai.xi #define MIU_R_CMD   0x20
146*53ee8cc1Swenshuai.xi #define MIU_ST_CMD       0x21
147*53ee8cc1Swenshuai.xi #define CFG_W_CMD       0x05
148*53ee8cc1Swenshuai.xi #define CFG_R_CMD       0x00
149*53ee8cc1Swenshuai.xi 
150*53ee8cc1Swenshuai.xi 
151*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
152*53ee8cc1Swenshuai.xi //  Local Structurs
153*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
154*53ee8cc1Swenshuai.xi 
155*53ee8cc1Swenshuai.xi 
156*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
157*53ee8cc1Swenshuai.xi //  Global Variables
158*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
159*53ee8cc1Swenshuai.xi 
160*53ee8cc1Swenshuai.xi 
161*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
162*53ee8cc1Swenshuai.xi //  Local Variables
163*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
164*53ee8cc1Swenshuai.xi /*
165*53ee8cc1Swenshuai.xi #ifdef CONFIG_AMAZON
166*53ee8cc1Swenshuai.xi extern s_MDRV_DMD_INTERFACE_FUNCTION  sMdrvDmdInterfaceFunc;
167*53ee8cc1Swenshuai.xi #endif
168*53ee8cc1Swenshuai.xi */
169*53ee8cc1Swenshuai.xi MS_U8   u8DMD_I2C_SLAVE_BUS;
170*53ee8cc1Swenshuai.xi MS_U8   u8DMD_I2C_SLAVE_ADDR;
171*53ee8cc1Swenshuai.xi MS_BOOL   bIS_EXTERN_DMD;
172*53ee8cc1Swenshuai.xi s_I2C_Interface_func   sI2cInterfaceFunc;
173*53ee8cc1Swenshuai.xi 
174*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
175*53ee8cc1Swenshuai.xi //  Debug Functions
176*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
177*53ee8cc1Swenshuai.xi #ifdef MS_DEBUG
178*53ee8cc1Swenshuai.xi #define DMD_DBG(x)          (x)
179*53ee8cc1Swenshuai.xi #else
180*53ee8cc1Swenshuai.xi #define DMD_DBG(x)          //(x)
181*53ee8cc1Swenshuai.xi #endif
182*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
183*53ee8cc1Swenshuai.xi //  Local Functions
184*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
185*53ee8cc1Swenshuai.xi 
186*53ee8cc1Swenshuai.xi 
187*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
188*53ee8cc1Swenshuai.xi //  Global Functions
189*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
MDrv_DMD_PreInit(void)190*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_PreInit(void)
191*53ee8cc1Swenshuai.xi {
192*53ee8cc1Swenshuai.xi     DMD_DBG(ULOGD("DEMOD","MDrv_DMD_PreInit\n"));
193*53ee8cc1Swenshuai.xi     /*
194*53ee8cc1Swenshuai.xi     #ifdef CONFIG_AMAZON
195*53ee8cc1Swenshuai.xi     sMdrvDmdInterfaceFunc.MDrv_DMD_I2C_Channel_Change  = MDrv_DMD_I2C_Channel_Change;
196*53ee8cc1Swenshuai.xi     sMdrvDmdInterfaceFunc.MDrv_DMD_I2C_Channel_Set        = MDrv_DMD_I2C_Channel_Set;
197*53ee8cc1Swenshuai.xi     sMdrvDmdInterfaceFunc.MDrv_DMD_ReadReg                     = MDrv_DMD_ReadReg;
198*53ee8cc1Swenshuai.xi     sMdrvDmdInterfaceFunc.MDrv_DMD_WriteReg                     = MDrv_DMD_WriteReg;
199*53ee8cc1Swenshuai.xi     sMdrvDmdInterfaceFunc.MDrv_DMD_WriteRegs                   = MDrv_DMD_WriteRegs;
200*53ee8cc1Swenshuai.xi     sMdrvDmdInterfaceFunc.Log10Approx                                 = Log10Approx;
201*53ee8cc1Swenshuai.xi     #endif
202*53ee8cc1Swenshuai.xi     */
203*53ee8cc1Swenshuai.xi     HAL_DMD_RegInit();
204*53ee8cc1Swenshuai.xi 
205*53ee8cc1Swenshuai.xi     //HAL_DMD_TS1_Tristate(TRUE);
206*53ee8cc1Swenshuai.xi     MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET_ALL_OFF);
207*53ee8cc1Swenshuai.xi 
208*53ee8cc1Swenshuai.xi     return TRUE;
209*53ee8cc1Swenshuai.xi }
210*53ee8cc1Swenshuai.xi 
MDrv_DMD_RFAGC_Tristate(MS_BOOL bEnable)211*53ee8cc1Swenshuai.xi void MDrv_DMD_RFAGC_Tristate(MS_BOOL bEnable)
212*53ee8cc1Swenshuai.xi {
213*53ee8cc1Swenshuai.xi     HAL_DMD_RFAGC_Tristate(bEnable);
214*53ee8cc1Swenshuai.xi }
215*53ee8cc1Swenshuai.xi 
MDrv_DMD_IFAGC_Tristate(MS_BOOL bEnable)216*53ee8cc1Swenshuai.xi void MDrv_DMD_IFAGC_Tristate(MS_BOOL bEnable)
217*53ee8cc1Swenshuai.xi {
218*53ee8cc1Swenshuai.xi     HAL_DMD_IFAGC_Tristate(bEnable);
219*53ee8cc1Swenshuai.xi }
220*53ee8cc1Swenshuai.xi 
MDrv_DMD_TS_GetClockRate(void * fTS_CLK)221*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_TS_GetClockRate(void *fTS_CLK)
222*53ee8cc1Swenshuai.xi {
223*53ee8cc1Swenshuai.xi     // TODO: TS output is only valid when demod is locked
224*53ee8cc1Swenshuai.xi //    return HAL_DMD_TS_GetClockRate(fTS_CLK);
225*53ee8cc1Swenshuai.xi return true;
226*53ee8cc1Swenshuai.xi }
227*53ee8cc1Swenshuai.xi 
MDrv_DMD_TSO_Clk_Control(MS_U8 * u8cmd_array)228*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_TSO_Clk_Control(MS_U8 *u8cmd_array)
229*53ee8cc1Swenshuai.xi {
230*53ee8cc1Swenshuai.xi     return HAL_DMD_TSO_Clk_Control(u8cmd_array);
231*53ee8cc1Swenshuai.xi }
232*53ee8cc1Swenshuai.xi 
MDrv_DMD_ReadReg(MS_U32 u32Reg,MS_U8 * u8Value)233*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_ReadReg(MS_U32 u32Reg, MS_U8 *u8Value)
234*53ee8cc1Swenshuai.xi {
235*53ee8cc1Swenshuai.xi     MS_BOOL bResult = FALSE;
236*53ee8cc1Swenshuai.xi     if (bIS_EXTERN_DMD == FALSE)
237*53ee8cc1Swenshuai.xi         bResult = MDrv_SYS_DMD_VD_MBX_ReadReg(u32Reg, u8Value);
238*53ee8cc1Swenshuai.xi     else //external demod
239*53ee8cc1Swenshuai.xi         bResult = HAL_DMD_IIC_ReadByte((u8DMD_I2C_SLAVE_BUS << 8 | u8DMD_I2C_SLAVE_ADDR), u32Reg, u8Value);
240*53ee8cc1Swenshuai.xi     return bResult;
241*53ee8cc1Swenshuai.xi }
MDrv_DMD_WriteReg(MS_U32 u32Reg,MS_U8 u8Value)242*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_WriteReg(MS_U32 u32Reg, MS_U8 u8Value)
243*53ee8cc1Swenshuai.xi {
244*53ee8cc1Swenshuai.xi     MS_BOOL bResult = FALSE;
245*53ee8cc1Swenshuai.xi     if (bIS_EXTERN_DMD == FALSE)
246*53ee8cc1Swenshuai.xi         bResult = MDrv_SYS_DMD_VD_MBX_WriteReg(u32Reg, u8Value);
247*53ee8cc1Swenshuai.xi     else //external demod
248*53ee8cc1Swenshuai.xi         bResult = HAL_DMD_IIC_WriteByte((u8DMD_I2C_SLAVE_BUS << 8 | u8DMD_I2C_SLAVE_ADDR), u32Reg, u8Value);
249*53ee8cc1Swenshuai.xi     return bResult;
250*53ee8cc1Swenshuai.xi }
251*53ee8cc1Swenshuai.xi 
MDrv_DMD_WriteRegs(MS_U32 u32Reg,MS_U8 * u8Value,MS_U8 u8Length)252*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_WriteRegs(MS_U32 u32Reg, MS_U8 *u8Value, MS_U8 u8Length)
253*53ee8cc1Swenshuai.xi {
254*53ee8cc1Swenshuai.xi     MS_BOOL bResult = FALSE;
255*53ee8cc1Swenshuai.xi     if (bIS_EXTERN_DMD == FALSE)
256*53ee8cc1Swenshuai.xi         bResult = MDrv_SYS_DMD_VD_MBX_WriteReg(u32Reg, (*u8Value));
257*53ee8cc1Swenshuai.xi     else //external demod
258*53ee8cc1Swenshuai.xi         bResult = HAL_DMD_IIC_WriteBytes((u8DMD_I2C_SLAVE_BUS << 8 | u8DMD_I2C_SLAVE_ADDR), u32Reg, u8Value, u8Length);
259*53ee8cc1Swenshuai.xi     return bResult;
260*53ee8cc1Swenshuai.xi 
261*53ee8cc1Swenshuai.xi }
262*53ee8cc1Swenshuai.xi 
MDrv_DMD_I2C_Channel_Change(MS_U8 ch_num)263*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_I2C_Channel_Change(MS_U8 ch_num)
264*53ee8cc1Swenshuai.xi {
265*53ee8cc1Swenshuai.xi     MS_BOOL bResult = FALSE;
266*53ee8cc1Swenshuai.xi     bResult = HAL_DMD_I2C_Channel_Change((u8DMD_I2C_SLAVE_BUS << 8 | u8DMD_I2C_SLAVE_ADDR), ch_num);
267*53ee8cc1Swenshuai.xi 
268*53ee8cc1Swenshuai.xi     return bResult;
269*53ee8cc1Swenshuai.xi 
270*53ee8cc1Swenshuai.xi }
271*53ee8cc1Swenshuai.xi 
MDrv_DMD_I2C_Channel_Set(MS_U8 ch_num)272*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_I2C_Channel_Set(MS_U8  ch_num)
273*53ee8cc1Swenshuai.xi {
274*53ee8cc1Swenshuai.xi     MS_BOOL bResult = FALSE;
275*53ee8cc1Swenshuai.xi 
276*53ee8cc1Swenshuai.xi     bResult = HAL_DMD_I2C_Channel_Set((u8DMD_I2C_SLAVE_BUS << 8 | u8DMD_I2C_SLAVE_ADDR), ch_num);
277*53ee8cc1Swenshuai.xi     return bResult;
278*53ee8cc1Swenshuai.xi 
279*53ee8cc1Swenshuai.xi }
280*53ee8cc1Swenshuai.xi 
MDrv_DMD_SSPI_Init(MS_U8 u8DeviceNum)281*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_SSPI_Init(MS_U8  u8DeviceNum)
282*53ee8cc1Swenshuai.xi {
283*53ee8cc1Swenshuai.xi 
284*53ee8cc1Swenshuai.xi 
285*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX_KERNEL
286*53ee8cc1Swenshuai.xi     if(MDrv_MSPI_Init_Ext(u8DeviceNum) == E_MSPI_OK)
287*53ee8cc1Swenshuai.xi         return TRUE;
288*53ee8cc1Swenshuai.xi     else
289*53ee8cc1Swenshuai.xi         return FALSE;
290*53ee8cc1Swenshuai.xi #endif
291*53ee8cc1Swenshuai.xi      return true;
292*53ee8cc1Swenshuai.xi 
293*53ee8cc1Swenshuai.xi }
294*53ee8cc1Swenshuai.xi 
MDrv_DMD_SSPI_MIU_Writes(MS_U32 u32Addr,MS_U8 * pdata,MS_U16 u16Size)295*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_SSPI_MIU_Writes(MS_U32 u32Addr, MS_U8 *pdata, MS_U16 u16Size)
296*53ee8cc1Swenshuai.xi {
297*53ee8cc1Swenshuai.xi     MS_BOOL bRet = TRUE;
298*53ee8cc1Swenshuai.xi     MS_U8 Wdata[5];
299*53ee8cc1Swenshuai.xi 
300*53ee8cc1Swenshuai.xi     Wdata[0] = MIU_W_CMD;
301*53ee8cc1Swenshuai.xi     Wdata[1] = u32Addr & 0xFF;
302*53ee8cc1Swenshuai.xi     Wdata[2] = (u32Addr >> 8) & 0xFF;
303*53ee8cc1Swenshuai.xi     Wdata[3] = (u32Addr >> 16)& 0xFF;
304*53ee8cc1Swenshuai.xi     Wdata[4] = (u32Addr >> 24);
305*53ee8cc1Swenshuai.xi     //ULOGD("DEMOD","MDrv_SS_MIU_Writes\n");
306*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX_KERNEL
307*53ee8cc1Swenshuai.xi     // Write operation
308*53ee8cc1Swenshuai.xi     MDrv_MSPI_SlaveEnable(TRUE);
309*53ee8cc1Swenshuai.xi     // send write address
310*53ee8cc1Swenshuai.xi     MDrv_MSPI_Write(Wdata,sizeof(Wdata));
311*53ee8cc1Swenshuai.xi     // send data
312*53ee8cc1Swenshuai.xi     MDrv_MSPI_Write(pdata,u16Size);
313*53ee8cc1Swenshuai.xi     MDrv_MSPI_SlaveEnable(FALSE);
314*53ee8cc1Swenshuai.xi #endif
315*53ee8cc1Swenshuai.xi     return bRet;
316*53ee8cc1Swenshuai.xi }
317*53ee8cc1Swenshuai.xi 
MDrv_DMD_SSPI_MIU_Reads(MS_U32 u32Addr,MS_U8 * pdata,MS_U16 u16Size)318*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_SSPI_MIU_Reads(MS_U32 u32Addr, MS_U8 *pdata, MS_U16 u16Size)
319*53ee8cc1Swenshuai.xi {
320*53ee8cc1Swenshuai.xi 
321*53ee8cc1Swenshuai.xi     MS_BOOL bRet = TRUE;
322*53ee8cc1Swenshuai.xi     MS_U8 Rdata[SPI_DEVICE_BUFFER_SIZE];
323*53ee8cc1Swenshuai.xi     MS_U16 dataLen, i, j=0;
324*53ee8cc1Swenshuai.xi 
325*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX_KERNEL
326*53ee8cc1Swenshuai.xi     do
327*53ee8cc1Swenshuai.xi     {
328*53ee8cc1Swenshuai.xi         dataLen = (u16Size>16?16:u16Size);//(len>24?24:len);
329*53ee8cc1Swenshuai.xi 
330*53ee8cc1Swenshuai.xi         Rdata[0] = MIU_R_CMD;
331*53ee8cc1Swenshuai.xi         Rdata[1] = u32Addr & 0xFF;
332*53ee8cc1Swenshuai.xi         Rdata[2] = (u32Addr >> 8) & 0xFF;
333*53ee8cc1Swenshuai.xi         Rdata[3] = (u32Addr >> 16)& 0xFF;
334*53ee8cc1Swenshuai.xi         Rdata[4] = (u32Addr >> 24);
335*53ee8cc1Swenshuai.xi         Rdata[5] = dataLen+1;
336*53ee8cc1Swenshuai.xi         //ULOGD("DEMOD","MDrv_SS_MIU_Reads, addr=0x%lx, dataLen=%d\n", u32Addr, dataLen);
337*53ee8cc1Swenshuai.xi 
338*53ee8cc1Swenshuai.xi         // send read command to read data
339*53ee8cc1Swenshuai.xi 
340*53ee8cc1Swenshuai.xi         MDrv_MSPI_SlaveEnable(TRUE);
341*53ee8cc1Swenshuai.xi         MDrv_MSPI_Write(Rdata,6);
342*53ee8cc1Swenshuai.xi         MDrv_MSPI_SlaveEnable(FALSE);
343*53ee8cc1Swenshuai.xi 
344*53ee8cc1Swenshuai.xi         // read operation
345*53ee8cc1Swenshuai.xi         Rdata[0] = MIU_ST_CMD;
346*53ee8cc1Swenshuai.xi         MDrv_MSPI_SlaveEnable(TRUE);
347*53ee8cc1Swenshuai.xi         MDrv_MSPI_Write(Rdata,1);
348*53ee8cc1Swenshuai.xi         //ULOGD("DEMOD","Read Operation\n");
349*53ee8cc1Swenshuai.xi         MDrv_MSPI_Read(Rdata, dataLen+1);
350*53ee8cc1Swenshuai.xi         MDrv_MSPI_SlaveEnable(FALSE);
351*53ee8cc1Swenshuai.xi 
352*53ee8cc1Swenshuai.xi         if(Rdata[0] != 0x0A)
353*53ee8cc1Swenshuai.xi         {
354*53ee8cc1Swenshuai.xi             ULOGD("DEMOD","MDrv_SS_MIU_Reads fail, status=0x%x\n", Rdata[0] );
355*53ee8cc1Swenshuai.xi             return false;
356*53ee8cc1Swenshuai.xi         }
357*53ee8cc1Swenshuai.xi 
358*53ee8cc1Swenshuai.xi         for (i=1; i<dataLen+1; i++, j++)
359*53ee8cc1Swenshuai.xi         {
360*53ee8cc1Swenshuai.xi             pdata[j] = Rdata[i];
361*53ee8cc1Swenshuai.xi             //ULOGD("DEMOD","%x, ", pdata[j]);
362*53ee8cc1Swenshuai.xi         }
363*53ee8cc1Swenshuai.xi 
364*53ee8cc1Swenshuai.xi         u16Size -= dataLen;
365*53ee8cc1Swenshuai.xi         u32Addr += dataLen;
366*53ee8cc1Swenshuai.xi         //ULOGD("DEMOD","u16Size=%d,  u32Addr=0x%lx\n", u16Size, u32Addr);
367*53ee8cc1Swenshuai.xi     }while(u16Size);
368*53ee8cc1Swenshuai.xi #endif
369*53ee8cc1Swenshuai.xi     return bRet;
370*53ee8cc1Swenshuai.xi }
371*53ee8cc1Swenshuai.xi 
MDrv_DMD_SSPI_RIU_Write8(MS_U16 u16Addr,MS_U8 data)372*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_SSPI_RIU_Write8(MS_U16 u16Addr, MS_U8 data)
373*53ee8cc1Swenshuai.xi {
374*53ee8cc1Swenshuai.xi     MS_BOOL bRet = TRUE;
375*53ee8cc1Swenshuai.xi     MS_U8 Wdata[4];
376*53ee8cc1Swenshuai.xi 
377*53ee8cc1Swenshuai.xi     Wdata[0] = RIU_W1_CMD;
378*53ee8cc1Swenshuai.xi     Wdata[1] = u16Addr & 0xFF;
379*53ee8cc1Swenshuai.xi     Wdata[2] = (u16Addr >> 8) & 0xFF;
380*53ee8cc1Swenshuai.xi     Wdata[3] = data;
381*53ee8cc1Swenshuai.xi     //ULOGD("DEMOD","MDrv_SS_RIU_Write\n");
382*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX_KERNEL
383*53ee8cc1Swenshuai.xi     // Write operation
384*53ee8cc1Swenshuai.xi     MDrv_MSPI_SlaveEnable(TRUE);
385*53ee8cc1Swenshuai.xi 
386*53ee8cc1Swenshuai.xi     // send write address & data
387*53ee8cc1Swenshuai.xi     MDrv_MSPI_Write(Wdata,4);
388*53ee8cc1Swenshuai.xi 
389*53ee8cc1Swenshuai.xi     MDrv_MSPI_SlaveEnable(FALSE);
390*53ee8cc1Swenshuai.xi #endif
391*53ee8cc1Swenshuai.xi     return bRet;
392*53ee8cc1Swenshuai.xi }
393*53ee8cc1Swenshuai.xi 
MDrv_DMD_SSPI_RIU_Read8(MS_U16 u16Addr,MS_U8 * pdata)394*53ee8cc1Swenshuai.xi MS_BOOL MDrv_DMD_SSPI_RIU_Read8(MS_U16 u16Addr, MS_U8 *pdata)
395*53ee8cc1Swenshuai.xi {
396*53ee8cc1Swenshuai.xi     MS_BOOL bRet = TRUE;
397*53ee8cc1Swenshuai.xi     MS_U8 Rdata[5];
398*53ee8cc1Swenshuai.xi 
399*53ee8cc1Swenshuai.xi     Rdata[0] = RIU_R1T_CMD;
400*53ee8cc1Swenshuai.xi     Rdata[1] = u16Addr & 0xFF;
401*53ee8cc1Swenshuai.xi     Rdata[2] = (u16Addr >> 8) & 0xFF;
402*53ee8cc1Swenshuai.xi     Rdata[3] = 0x00;
403*53ee8cc1Swenshuai.xi     //ULOGD("DEMOD","MDrv_SS_RIU_Read8\n");
404*53ee8cc1Swenshuai.xi #ifndef MSOS_TYPE_LINUX_KERNEL
405*53ee8cc1Swenshuai.xi     MDrv_MSPI_SlaveEnable(TRUE);
406*53ee8cc1Swenshuai.xi     // send read command to read data
407*53ee8cc1Swenshuai.xi     MDrv_MSPI_Write(Rdata,4);
408*53ee8cc1Swenshuai.xi     // read operation
409*53ee8cc1Swenshuai.xi     //ULOGD("DEMOD","Read Operation\n");
410*53ee8cc1Swenshuai.xi     MDrv_MSPI_Read(pdata, 1);
411*53ee8cc1Swenshuai.xi     MDrv_MSPI_SlaveEnable(FALSE);
412*53ee8cc1Swenshuai.xi #endif
413*53ee8cc1Swenshuai.xi 
414*53ee8cc1Swenshuai.xi     return bRet;
415*53ee8cc1Swenshuai.xi 
416*53ee8cc1Swenshuai.xi }
417