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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvAVD.c
98 /// @brief AVD Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106 // Common Definition
107 #ifdef MSOS_TYPE_LINUX_KERNEL
108 #include <linux/string.h>
109 #else
110 #include <string.h>
111 #include <stdio.h>
112 #include <math.h>
113 #endif
114 #include "MsCommon.h"
115 #include "MsVersion.h"
116 #include "MsOS.h"
117
118 // Internal Definition
119 //#include "regCHIP.h"
120 //#include "regAVD.h"
121 //#include "mapi_tuner.h"
122 #include "drvSYS.h"
123 #include "drvDMD_VD_MBX.h"
124 #include "drvDMD_INTERN_DVBT_v2.h"
125 #include "halDMD_INTERN_DVBT.h"
126 #include "halDMD_INTERN_common.h"
127 #include "drvSAR.h" // for Utopia2
128 #include "utopia.h"
129 #include "utopia_dapi.h"
130 #include "../../utopia_core/utopia_driver_id.h"
131 #include "ULog.h"
132 //-------------------------------------------------------------------------------------------------
133 // Driver Compiler Options
134 //-------------------------------------------------------------------------------------------------
135
136
137 //-------------------------------------------------------------------------------------------------
138 // Local Defines
139 //-------------------------------------------------------------------------------------------------
140
141
142 //-------------------------------------------------------------------------------------------------
143 // Local Structurs
144 //-------------------------------------------------------------------------------------------------
145
146
147 //-------------------------------------------------------------------------------------------------
148 // Global Variables
149 //-------------------------------------------------------------------------------------------------
150 #define DMD_LOCK() \
151 do{ \
152 MS_ASSERT(MsOS_In_Interrupt() == FALSE); \
153 if (_s32DMD_DVBT_Mutex == -1) return FALSE; \
154 if (_u8DMDDbgLevel == DMD_DBGLV_DEBUG) ULOGD("DEMOD","%s lock mutex\n", __FUNCTION__);\
155 MsOS_ObtainMutex(_s32DMD_DVBT_Mutex, MSOS_WAIT_FOREVER);\
156 }while(0)
157
158 #define DMD_UNLOCK() \
159 do{ \
160 MsOS_ReleaseMutex(_s32DMD_DVBT_Mutex);\
161 if (_u8DMDDbgLevel == DMD_DBGLV_DEBUG) ULOGD("DEMOD","%s unlock mutex\n", __FUNCTION__); \
162 }while(0)
163
164 #if 0
165 MS_U8 DVBT_TS_PHASE_EN =0;
166 MS_U8 DVBT_TS_PHASE_NUM = 0;
167 #endif
168
169 //-------------------------------------------------------------------------------------------------
170 // Local Variables
171 //-------------------------------------------------------------------------------------------------
172 MS_BOOL bIsDVBT = FALSE; // Usage for STR
173
174 // YP mark
175 #if 0
176
177 #if 1
178 static MSIF_Version _drv_dmd_dvbt_intern_version = {
179 .MW = { DMD_DVBT_INTERN_VER, },
180 };
181 #else
182 static MSIF_Version _drv_dmd_dvbt_intern_version;
183 #endif
184
185 static DMD_DVBT_InitData _sDMD_DVBT_InitData;
186 static DMD_DbgLv _u8DMDDbgLevel=DMD_DBGLV_NONE;
187 static MS_S32 _s32DMD_DVBT_Mutex=-1;
188 static DMD_DVBT_Info sDMD_DVBT_Info;
189 static MS_U16 u16DMD_DVBT_TPS_Timeout = 1500, u16DMD_DVBT_FEC_Timeout=6000;
190 static MS_U32 u32DMD_DVBT_IfFrequency = 36167L, u32DMD_DVBT_FsFrequency = 45474L;
191 static MS_U8 u8DMD_DVBT_IQSwap=0;
192 static DMD_RF_CHANNEL_BANDWIDTH eDMD_DVBT_BandWidth=E_DMD_RF_CH_BAND_8MHz;
193 #endif
194 //-------------------------------------------------------------------------------------------------
195 // Debug Functions
196 //-------------------------------------------------------------------------------------------------
197 #ifdef MS_DEBUG
198 #define DMD_DBG(x) (x)
199 #else
200 #define DMD_DBG(x) // (x)
201 #endif
202 //-------------------------------------------------------------------------------------------------
203 // Local Functions
204 //-------------------------------------------------------------------------------------------------
205 typedef MS_BOOL (*IOCTL_DVBT_Init)(DMD_DVBT_InitData_Transform*, MS_U32);
206 typedef MS_BOOL (*IOCTL_DVBT_Exit)(void);
207 typedef MS_BOOL (*IOCTL_DVBT_SetDbgLevel)(DMD_DbgLv);
208 //typedef DMD_DVBT_Info* (*IOCTL_DVBT_GetInfo)(DMD_DVBT_INFO_TYPE);
209 typedef MS_BOOL (*IOCTL_DVBT_GetLibVer)(const MSIF_Version **);
210 typedef MS_BOOL (*IOCTL_DVBT_GetFWVer)(MS_U16 *);
211 typedef MS_BOOL (*IOCTL_DVBT_GetReg)(MS_U16, MS_U8 *);
212 typedef MS_BOOL (*IOCTL_DVBT_SetReg)(MS_U16, MS_U8);
213 typedef MS_BOOL (*IOCTL_DVBT_SetSerialControl)(MS_BOOL);
214 typedef MS_BOOL (*IOCTL_DVBT_SetConfig)(DMD_RF_CHANNEL_BANDWIDTH, MS_BOOL, MS_BOOL);
215 typedef MS_BOOL (*IOCTL_DVBT_SetConfigHPLP)(DMD_RF_CHANNEL_BANDWIDTH, MS_BOOL, MS_BOOL, MS_BOOL);
216 typedef MS_BOOL (*IOCTL_DVBT_SetConfigHPLPSetIF)(DMD_RF_CHANNEL_BANDWIDTH, MS_BOOL, MS_BOOL, MS_BOOL, MS_U32, MS_U32, MS_U8);
217 typedef MS_BOOL (*IOCTL_DVBT_SetActive)(MS_BOOL);
218 typedef MS_BOOL (*IOCTL_DVBT_GetLock)(DMD_DVBT_GETLOCK_TYPE, DMD_LOCK_STATUS *);
219 //typedef MS_BOOL (*IOCTL_DVBT_GetSignalStrength)(MS_U16 *);
220 //typedef MS_BOOL (*IOCTL_DVBT_GetSignalStrengthWithRFPower)(MS_U16 *, float);
221 //typedef MS_BOOL (*IOCTL_DVBT_GetSignalQuality)(MS_U16 *);
222 //typedef MS_BOOL (*IOCTL_DVBT_GetSignalQualityWithRFPower)(MS_U16 *, float);
223 //arthur
224 typedef MS_BOOL (*IOCTL_DVBT_GetSNR)(MS_U32 *);
225 typedef MS_BOOL (*IOCTL_DVBT_GetPostViterbiBer)(MS_U16 *,MS_U32 *,MS_U16 *);
226 typedef MS_BOOL (*IOCTL_DVBT_GetIFAGC)(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err);
227
228 //typedef MS_BOOL (*IOCTL_DVBT_GetPreViterbiBer)(float *);
229 typedef MS_BOOL (*IOCTL_DVBT_GetPacketErr)(MS_U16 *);
230 typedef MS_BOOL (*IOCTL_DVBT_GetTPSInfo)(MS_U16 *);
231 typedef MS_BOOL (*IOCTL_DVBT_GetCellID)(MS_U16 *);
232 //typedef MS_BOOL (*IOCTL_DVBT_GetFreqOffset)(float *);
233 //typedef MS_BOOL (*IOCTL_DVBT_NORDIGSSITableWrite)(DMD_CONSTEL, DMD_CODERATE, float);
234 //typedef MS_BOOL (*IOCTL_DVBT_NORDIGSSITableRead)(DMD_CONSTEL, DMD_CODERATE, float*);
235 typedef MS_U32 (*IOCTL_DVBT_SetPowerState)(EN_POWER_MODE);
236
237 typedef struct DVBT_INSTANT_PRIVATE
238 {
239 IOCTL_DVBT_Init fpDVBTInit;
240 IOCTL_DVBT_Exit fpDVBTExit;
241 IOCTL_DVBT_SetDbgLevel fpDVBTSetDbgLevel;
242 //IOCTL_DVBT_GetInfo fpDVBTGetInfo;
243 IOCTL_DVBT_GetLibVer fpDVBTGetLibVer;
244 IOCTL_DVBT_GetFWVer fpDVBTGetFWVer;
245 IOCTL_DVBT_GetReg fpDVBTGetReg;
246 IOCTL_DVBT_SetReg fpDVBTSetReg;
247 IOCTL_DVBT_SetSerialControl fpDVBTSetSerialControl;
248 // IOCTL_DVBT_SetConfig fpDVBTSetConfig;
249 // IOCTL_DVBT_SetConfigHPLP fpDVBTSetConfigHPLP;
250 IOCTL_DVBT_SetConfigHPLPSetIF fpDVBTSetConfigHPLPSetIF;
251 IOCTL_DVBT_SetActive fpDVBTSetActive;
252 IOCTL_DVBT_GetLock fpDVBTGetLock;
253 // IOCTL_DVBT_GetSignalStrength fpDVBTGetSignalStrength;
254 // IOCTL_DVBT_GetSignalStrengthWithRFPower fpDVBTGetSignalStrengthWithRFPower;
255 // IOCTL_DVBT_GetSignalQuality fpDVBTGetSignalQuality;
256 // IOCTL_DVBT_GetSignalQualityWithRFPower fpDVBTGetSignalQualityWithRFPower;
257 //arthur
258 IOCTL_DVBT_GetIFAGC fpDVBT_GetIFAGC;
259 IOCTL_DVBT_GetSNR fpDVBTGetSNR;
260 IOCTL_DVBT_GetPostViterbiBer fpDVBTGetPostViterbiBer;
261 // IOCTL_DVBT_GetPreViterbiBer fpDVBTGetPreViterbiBer;
262 IOCTL_DVBT_GetPacketErr fpDVBTGetPacketErr;
263 IOCTL_DVBT_GetTPSInfo fpDVBTGetTPSInfo;
264 IOCTL_DVBT_GetCellID fpDVBTGetCellID;
265 // IOCTL_DVBT_GetFreqOffset fpDVBTGetFreqOffset;
266 // IOCTL_DVBT_NORDIGSSITableWrite fpDVBTNORDIGSSITableWrite;
267 // IOCTL_DVBT_NORDIGSSITableRead fpDVBTNORDIGSSITableRead;
268 IOCTL_DVBT_SetPowerState fpDVBTSetPowerState;
269 } DVBT_INSTANT_PRIVATE;
270
271
272 /***********************************
273 original driver code define
274 ************************************/
275 #define DMD_LOCK() \
276 do{ \
277 MS_ASSERT(MsOS_In_Interrupt() == FALSE); \
278 if (_s32DMD_DVBT_Mutex == -1) return FALSE; \
279 if (_u8DMDDbgLevel == DMD_DBGLV_DEBUG) ULOGD("DEMOD","%s lock mutex\n", __FUNCTION__);\
280 MsOS_ObtainMutex(_s32DMD_DVBT_Mutex, MSOS_WAIT_FOREVER);\
281 }while(0)
282
283 #define DMD_UNLOCK() \
284 do{ \
285 MsOS_ReleaseMutex(_s32DMD_DVBT_Mutex);\
286 if (_u8DMDDbgLevel == DMD_DBGLV_DEBUG) ULOGD("DEMOD","%s unlock mutex\n", __FUNCTION__); \
287 }while(0)
288
289 MS_U8 DVBT_TS_PHASE_EN =0;
290 MS_U8 DVBT_TS_PHASE_NUM = 0;
291 //-------------------------------------------------------------------------------------------------
292 // Local Variables
293 //-------------------------------------------------------------------------------------------------
294 #if 1
295 static MSIF_Version _drv_dmd_dvbt_intern_version = {
296 .MW = { DMD_DVBT_INTERN_VER, },
297 };
298 #else
299 static MSIF_Version _drv_dmd_dvbt_intern_version;
300 #endif
301
302 //bryan temp mark
303 #if(0)
304 static DMD_DVBT_InitData _sDMD_DVBT_InitData;
305 #else
306 static DMD_DVBT_InitData_Transform _sDMD_DVBT_InitData;
307 #endif
308 static DMD_DbgLv _u8DMDDbgLevel=DMD_DBGLV_NONE;
309 static MS_S32 _s32DMD_DVBT_Mutex=-1;
310 static DMD_DVBT_Info sDMD_DVBT_Info;
311 static MS_U16 u16DMD_DVBT_TPS_Timeout = 1500, u16DMD_DVBT_FEC_Timeout=6000;
312 static MS_U32 u32DMD_DVBT_IfFrequency = 36167L, u32DMD_DVBT_FsFrequency = 45474L;
313 static MS_U8 u8DMD_DVBT_IQSwap=0;
314 static DMD_RF_CHANNEL_BANDWIDTH eDMD_DVBT_BandWidth=E_DMD_RF_CH_BAND_8MHz;
315 //-------------------------------------------------------------------------------------------------
316 // Debug Functions
317 //-------------------------------------------------------------------------------------------------
318 #if(0)
319 #ifdef MS_DEBUG
320 #define DMD_DBG(x) (x)
321 #else
322 #define DMD_DBG(x) //(x)
323 #endif
324 #endif
325
326
327 /* bryan temp mark*/
328 #if(0)
DMD_DVBT_Init(DMD_DVBT_InitData * pDMD_DVBT_InitData,MS_U32 u32InitDataLen)329 MS_BOOL DMD_DVBT_Init(DMD_DVBT_InitData *pDMD_DVBT_InitData, MS_U32 u32InitDataLen)
330 {
331 char pDMD_DVBT_MutexString[16];
332 MS_U8 u8ADCIQMode = 0, u8PadSel = 0, bPGAEnable = 0, u8PGAGain = 5;
333 MS_BOOL bRFAGCTristateEnable = 1;
334 MS_BOOL bIFAGCTristateEnable = 0;
335
336 if (_s32DMD_DVBT_Mutex != -1)
337 {
338 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init more than once\n"));
339 return FALSE;
340 }
341
342 if (NULL == strncpy(pDMD_DVBT_MutexString,"Mutex DMD DVBT",16))
343 {
344 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init strcpy Fail\n"));
345 return FALSE;
346 }
347 _s32DMD_DVBT_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, pDMD_DVBT_MutexString, MSOS_PROCESS_SHARED);
348 if (_s32DMD_DVBT_Mutex == -1)
349 {
350 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init Create Mutex Fail\n"));
351 return FALSE;
352 }
353 //_u8DMDDbgLevel = DMD_DBGLV_DEBUG;
354 #ifdef MS_DEBUG
355 if (_u8DMDDbgLevel >= DMD_DBGLV_INFO)
356 {
357 ULOGD("DEMOD","MDrv_DMD_DVBT_Init\n");
358 }
359 #endif
360
361 if ( sizeof(_sDMD_DVBT_InitData) == u32InitDataLen)
362 {
363 memcpy(&_sDMD_DVBT_InitData, pDMD_DVBT_InitData, u32InitDataLen);
364 }
365 else
366 {
367 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init input data structure incorrect\n"));
368 return FALSE;
369 }
370
371 if (_sDMD_DVBT_InitData.u8SarChannel != 0xFF)
372 {
373 MDrv_SAR_Adc_Config(_sDMD_DVBT_InitData.u8SarChannel, TRUE);
374 }
375
376 DMD_LOCK();
377 MDrv_SYS_DMD_VD_MBX_SetType(E_DMD_VD_MBX_TYPE_DVBT);
378 HAL_DMD_RegInit();
379
380 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
381 {
382 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=2)
383 {
384 bRFAGCTristateEnable = (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[3] & (BIT_(0))) ? TRUE : FALSE; // RFAGC tristate control
385 bIFAGCTristateEnable = (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[3] & (BIT_(4))) ? TRUE : FALSE; // IFAGC tristate control
386 }
387 else
388 {
389 bRFAGCTristateEnable = 1;
390 bIFAGCTristateEnable = 0;
391 }
392 }
393 else
394 {
395 bRFAGCTristateEnable = 1;
396 bIFAGCTristateEnable = 0;
397 }
398
399 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
400 {
401 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=3)
402 {
403 u32DMD_DVBT_IfFrequency = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[4]; // IF frequency
404 u32DMD_DVBT_IfFrequency = (u32DMD_DVBT_IfFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[5]; // IF frequency
405 u32DMD_DVBT_IfFrequency = (u32DMD_DVBT_IfFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[6]; // IF frequency
406 u32DMD_DVBT_IfFrequency = (u32DMD_DVBT_IfFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[7]; // IF frequency
407 u32DMD_DVBT_FsFrequency = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[8]; // FS frequency
408 u32DMD_DVBT_FsFrequency = (u32DMD_DVBT_FsFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[9]; // FS frequency
409 u32DMD_DVBT_FsFrequency = (u32DMD_DVBT_FsFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[10]; // FS frequency
410 u32DMD_DVBT_FsFrequency = (u32DMD_DVBT_FsFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[11]; // FS frequency
411 u8DMD_DVBT_IQSwap = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[12]; // IQ Swap
412
413 u8ADCIQMode = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[13]; // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
414 u8PadSel = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[14]; // u8PadSel : 0=Normal, 1=analog pad
415 bPGAEnable = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[15]; // bPGAEnable : 0=disable, 1=enable
416 u8PGAGain = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[16]; // u8PGAGain : default 5
417 }
418 else
419 {
420
421 }
422 }
423 else
424 {
425
426 }
427 #ifdef MS_DEBUG
428 ULOGD("DEMOD","u32DMD_DVBT_IfFrequency %ld\n",u32DMD_DVBT_IfFrequency);
429 ULOGD("DEMOD","u32DMD_DVBT_FsFrequency %ld\n",u32DMD_DVBT_FsFrequency);
430 ULOGD("DEMOD","u8DMD_DVBT_IQSwap %d\n",u8DMD_DVBT_IQSwap);
431 #endif
432
433 u16DMD_DVBT_TPS_Timeout = 1500;
434 u16DMD_DVBT_FEC_Timeout = 6000;
435 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
436 {
437 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=4)
438 {
439 u16DMD_DVBT_TPS_Timeout = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[17]; // TPS timeout in ms
440 u16DMD_DVBT_TPS_Timeout = (u16DMD_DVBT_TPS_Timeout<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[18];
441 if (u16DMD_DVBT_TPS_Timeout < 700) u16DMD_DVBT_TPS_Timeout=700;
442 //ULOGD("DEMOD","u16DMD_DVBT_TPS_Timeout %d\n",u16DMD_DVBT_TPS_Timeout);
443
444 u16DMD_DVBT_FEC_Timeout = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[19]; // FEC timeout in ms
445 u16DMD_DVBT_FEC_Timeout = (u16DMD_DVBT_FEC_Timeout<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[20];
446 if (u16DMD_DVBT_FEC_Timeout < 2500) u16DMD_DVBT_FEC_Timeout=2500;
447 //ULOGD("DEMOD","u16DMD_DVBT_FEC_Timeout %d\n",u16DMD_DVBT_FEC_Timeout);
448 }
449 else
450 {
451 }
452 }
453 else
454 {
455 }
456
457 if (bIFAGCTristateEnable)
458 {
459 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET_ALL_OFF);
460 }
461 else
462 {
463 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET);
464 }
465
466
467 // oga
468 DVBT_TS_PHASE_EN =0;
469 DVBT_TS_PHASE_NUM = 0;
470 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
471 {
472 /*
473 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=5) // version bigger than 5, apply TS phase solution
474 {
475 DVBT_TS_PHASE_EN = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[INDEX_T_TS_PHASE_EN];
476 DVBT_TS_PHASE_NUM = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[INDEX_T_TS_PHASE_NUM];
477 ULOGD("DEMOD","##DVBT:TS check: bTsPhaseEn = %d, u16TsPhaseNum = %d\n",DVBT_TS_PHASE_EN,DVBT_TS_PHASE_NUM);
478 }
479 else
480 {
481 ULOGD("DEMOD","##DVBT:TS Phase check !!, board version smaller than 4\n");
482 }
483 */
484 }
485 else // if init board define is NULL TS phase needs check.
486 {
487 ULOGD("DEMOD","##DVBT:TS Phase check !!\n");
488 }
489
490
491
492 if (_sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitExt != NULL)
493 {
494 if (_sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitExt[0]>=1)
495 {
496 INTERN_DVBT_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, _sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitExt, _sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitSize);
497 }
498 else
499 {
500 ULOGD("DEMOD","u8DMD_DVBT_DSPRegInitExt Error\n");
501 }
502 }
503 else
504 {
505 INTERN_DVBT_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, NULL, 0);
506 }
507
508 INTERN_DVBT_Version(&sDMD_DVBT_Info.u16Version);
509 DMD_UNLOCK();
510 #ifdef MS_DEBUG
511 ULOGD("DEMOD","firmware version: %x\n",sDMD_DVBT_Info.u16Version);
512 #endif
513 return TRUE;
514 }
515 #else
DMD_DVBT_Init(DMD_DVBT_InitData_Transform * pDMD_DVBT_InitData,MS_U32 u32InitDataLen)516 MS_BOOL DMD_DVBT_Init(DMD_DVBT_InitData_Transform *pDMD_DVBT_InitData, MS_U32 u32InitDataLen)
517 {
518 char pDMD_DVBT_MutexString[16];
519 MS_U8 u8ADCIQMode = 0, u8PadSel = 0, bPGAEnable = 0, u8PGAGain = 5;
520 MS_BOOL bRFAGCTristateEnable = 1;
521 MS_BOOL bIFAGCTristateEnable = 0;
522
523 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_Init\n"));
524
525 bIsDVBT = TRUE;
526
527 if (_s32DMD_DVBT_Mutex != -1)
528 {
529 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init more than once\n"));
530 return FALSE;
531 }
532
533 if (NULL == strncpy(pDMD_DVBT_MutexString,"Mutex DMD DVBT",16))
534 {
535 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init strcpy Fail\n"));
536 return FALSE;
537 }
538 _s32DMD_DVBT_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, pDMD_DVBT_MutexString, MSOS_PROCESS_SHARED);
539 if (_s32DMD_DVBT_Mutex == -1)
540 {
541 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init Create Mutex Fail\n"));
542 return FALSE;
543 }
544 //_u8DMDDbgLevel = DMD_DBGLV_DEBUG;
545 #ifdef MS_DEBUG
546 if (_u8DMDDbgLevel >= DMD_DBGLV_INFO)
547 {
548 ULOGD("DEMOD","MDrv_DMD_DVBT_Init\n");
549 }
550 #endif
551 u32InitDataLen=sizeof(_sDMD_DVBT_InitData);
552 //if ( sizeof(_sDMD_DVBT_InitData) == u32InitDataLen)
553 //bryan temp test
554 if(1)
555 {
556 memcpy(&_sDMD_DVBT_InitData, pDMD_DVBT_InitData, u32InitDataLen);
557 }
558 else
559 {
560 DMD_DBG(ULOGD("DEMOD","MDrv_DMD_DVBT_Init input data structure incorrect\n"));
561 return FALSE;
562 }
563
564 if (_sDMD_DVBT_InitData.u8SarChannel != 0xFF)
565 {
566 //bryan temp mark
567 // MDrv_SAR_Adc_Config(_sDMD_DVBT_InitData.u8SarChannel, TRUE);
568 }
569
570 DMD_LOCK();
571 MDrv_SYS_DMD_VD_MBX_SetType(E_DMD_VD_MBX_TYPE_DVBT);
572 HAL_DMD_RegInit();
573
574 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
575 {
576 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=2)
577 {
578 bRFAGCTristateEnable = (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[3] & (BIT_(0))) ? TRUE : FALSE; // RFAGC tristate control
579 bIFAGCTristateEnable = (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[3] & (BIT_(4))) ? TRUE : FALSE; // IFAGC tristate control
580 }
581 else
582 {
583 bRFAGCTristateEnable = 1;
584 bIFAGCTristateEnable = 0;
585 }
586 }
587 else
588 {
589 bRFAGCTristateEnable = 1;
590 bIFAGCTristateEnable = 0;
591 }
592
593 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
594 {
595 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=3)
596 {
597 u32DMD_DVBT_IfFrequency = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[4]; // IF frequency
598 u32DMD_DVBT_IfFrequency = (u32DMD_DVBT_IfFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[5]; // IF frequency
599 u32DMD_DVBT_IfFrequency = (u32DMD_DVBT_IfFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[6]; // IF frequency
600 u32DMD_DVBT_IfFrequency = (u32DMD_DVBT_IfFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[7]; // IF frequency
601 u32DMD_DVBT_FsFrequency = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[8]; // FS frequency
602 u32DMD_DVBT_FsFrequency = (u32DMD_DVBT_FsFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[9]; // FS frequency
603 u32DMD_DVBT_FsFrequency = (u32DMD_DVBT_FsFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[10]; // FS frequency
604 u32DMD_DVBT_FsFrequency = (u32DMD_DVBT_FsFrequency<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[11]; // FS frequency
605 u8DMD_DVBT_IQSwap = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[12]; // IQ Swap
606
607 u8ADCIQMode = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[13]; // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
608 u8PadSel = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[14]; // u8PadSel : 0=Normal, 1=analog pad
609 bPGAEnable = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[15]; // bPGAEnable : 0=disable, 1=enable
610 u8PGAGain = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[16]; // u8PGAGain : default 5
611 }
612 else
613 {
614
615 }
616 }
617 else
618 {
619
620 }
621 #ifdef MS_DEBUG
622 ULOGD("DEMOD","u32DMD_DVBT_IfFrequency %ld\n",u32DMD_DVBT_IfFrequency);
623 ULOGD("DEMOD","u32DMD_DVBT_FsFrequency %ld\n",u32DMD_DVBT_FsFrequency);
624 ULOGD("DEMOD","u8DMD_DVBT_IQSwap %d\n",u8DMD_DVBT_IQSwap);
625 #endif
626
627 u16DMD_DVBT_TPS_Timeout = 1500;
628 u16DMD_DVBT_FEC_Timeout = 6000;
629 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
630 {
631 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=4)
632 {
633 u16DMD_DVBT_TPS_Timeout = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[17]; // TPS timeout in ms
634 u16DMD_DVBT_TPS_Timeout = (u16DMD_DVBT_TPS_Timeout<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[18];
635 if (u16DMD_DVBT_TPS_Timeout < 700) u16DMD_DVBT_TPS_Timeout=700;
636 //ULOGD("DEMOD","u16DMD_DVBT_TPS_Timeout %d\n",u16DMD_DVBT_TPS_Timeout);
637
638 u16DMD_DVBT_FEC_Timeout = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[19]; // FEC timeout in ms
639 u16DMD_DVBT_FEC_Timeout = (u16DMD_DVBT_FEC_Timeout<<8)+_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[20];
640 if (u16DMD_DVBT_FEC_Timeout < 2500) u16DMD_DVBT_FEC_Timeout=2500;
641 //ULOGD("DEMOD","u16DMD_DVBT_FEC_Timeout %d\n",u16DMD_DVBT_FEC_Timeout);
642 }
643 else
644 {
645 }
646 }
647 else
648 {
649 }
650
651 if (bIFAGCTristateEnable)
652 {
653 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET_ALL_OFF);
654 }
655 else
656 {
657 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET);
658 }
659
660
661 // oga
662 DVBT_TS_PHASE_EN =0;
663 DVBT_TS_PHASE_NUM = 0;
664 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
665 {
666 /*
667 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=5) // version bigger than 5, apply TS phase solution
668 {
669 DVBT_TS_PHASE_EN = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[INDEX_T_TS_PHASE_EN];
670 DVBT_TS_PHASE_NUM = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[INDEX_T_TS_PHASE_NUM];
671 ULOGD("DEMOD","##DVBT:TS check: bTsPhaseEn = %d, u16TsPhaseNum = %d\n",DVBT_TS_PHASE_EN,DVBT_TS_PHASE_NUM);
672 }
673 else
674 {
675 ULOGD("DEMOD","##DVBT:TS Phase check !!, board version smaller than 4\n");
676 }
677 */
678 }
679 else // if init board define is NULL TS phase needs check.
680 {
681 ULOGD("DEMOD","##DVBT:TS Phase check !!\n");
682 }
683
684
685
686 if (_sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitExt != NULL)
687 {
688 if (_sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitExt[0]>=1)
689 {
690 INTERN_DVBT_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, _sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitExt, _sDMD_DVBT_InitData.u8DMD_DVBT_DSPRegInitSize);
691 }
692 else
693 {
694 ULOGD("DEMOD","u8DMD_DVBT_DSPRegInitExt Error\n");
695 }
696 }
697 else
698 {
699 INTERN_DVBT_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, NULL, 0);
700 }
701
702 INTERN_DVBT_Version(&sDMD_DVBT_Info.u16Version);
703 DMD_UNLOCK();
704 #ifdef MS_DEBUG
705 ULOGD("DEMOD","firmware version: %x\n",sDMD_DVBT_Info.u16Version);
706 #endif
707 return TRUE;
708 }
709 #endif
710
DMD_DVBT_Exit(void)711 MS_BOOL DMD_DVBT_Exit(void)
712 {
713 MS_BOOL bRet;
714
715 #ifdef MS_DEBUG
716 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
717 {
718 ULOGD("DEMOD","MDrv_DMD_DVBT_Exit\n");
719 }
720 #endif
721
722 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_Exit\n"));
723 bIsDVBT = FALSE;
724
725 DMD_LOCK();
726 bRet = INTERN_DVBT_Exit();
727 DMD_UNLOCK();
728 MsOS_DeleteMutex(_s32DMD_DVBT_Mutex);
729 _s32DMD_DVBT_Mutex= -1;
730 return bRet;
731 }
732
DMD_DVBT_SetDbgLevel(DMD_DbgLv u8DbgLevel)733 MS_BOOL DMD_DVBT_SetDbgLevel(DMD_DbgLv u8DbgLevel)
734 {
735 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_SetDbgLevel\n"));
736
737 DMD_LOCK();
738 _u8DMDDbgLevel = u8DbgLevel;
739 DMD_UNLOCK();
740 return TRUE;
741 }
742
743 /*bryan temp mark*/
744 #if(0)
DMD_DVBT_GetInfo(DMD_DVBT_INFO_TYPE eInfoType)745 DMD_DVBT_Info* DMD_DVBT_GetInfo(DMD_DVBT_INFO_TYPE eInfoType)
746 {
747 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT_GetInfo\n"));
748
749 DMD_LOCK();
750 switch (eInfoType)
751 {
752 case E_DMD_DVBT_MODULATION_INFO:
753 INTERN_DVBT_Show_Modulation_info();
754 break;
755 case E_DMD_DVBT_DEMOD_INFO:
756 INTERN_DVBT_Show_Demod_Info();
757 break;
758 case E_DMD_DVBT_LOCK_INFO:
759 INTERN_DVBT_Show_Lock_Info();
760 break;
761 case E_DMD_DVBT_PRESFO_INFO:
762 INTERN_DVBT_Show_PRESFO_Info();
763 break;
764 case E_DMD_DVBT_LOCK_TIME_INFO:
765 INTERN_DVBT_Show_Lock_Time_Info();
766 break;
767 case E_DMD_DVBT_BER_INFO:
768 INTERN_DVBT_Show_BER_Info();
769 break;
770 case E_DMD_DVBT_AGC_INFO:
771 INTERN_DVBT_Show_AGC_Info();
772 break;
773 default:
774 #ifdef MS_DEBUG
775 ULOGD("DEMOD","MDrv_DMD_DVBT_GetInfo %d Error\n", eInfoType);
776 #endif
777 break;
778 }
779 DMD_UNLOCK();
780 return &sDMD_DVBT_Info;
781 }
782 #endif
783
784
DMD_DVBT_GetLibVer(const MSIF_Version ** ppVersion)785 MS_BOOL DMD_DVBT_GetLibVer(const MSIF_Version **ppVersion)
786 {
787 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_GetLibVer\n"));
788
789 DMD_LOCK();
790 if (!ppVersion)
791 {
792 return FALSE;
793 }
794
795 *ppVersion = &_drv_dmd_dvbt_intern_version;
796 DMD_UNLOCK();
797 return TRUE;
798 }
799
DMD_DVBTGetFWVer(MS_U16 * ver)800 MS_BOOL DMD_DVBTGetFWVer(MS_U16 *ver)
801 {
802
803 MS_BOOL bRet;
804 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBTGetFWVer\n"));
805
806 DMD_LOCK();
807
808 bRet = INTERN_DVBT_Version(ver);
809 //ULOGD("DEMOD","MDrv_DMD_DVBT_GetFWVer %x\n",*ver);
810 DMD_UNLOCK();
811
812 return bRet;
813
814 }
815
DMD_DVBT_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)816 MS_BOOL DMD_DVBT_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
817 {
818 MS_BOOL bRet;
819
820 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_GetReg\n"));
821
822 DMD_LOCK();
823 bRet=MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, pu8Data);
824 DMD_UNLOCK();
825
826 #ifdef MS_DEBUG
827 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
828 {
829 ULOGD("DEMOD","MDrv_DMD_DVBT_GetReg %x %x\n", u16Addr, *pu8Data);
830 }
831 #endif
832
833 return bRet;
834 }
835
DMD_DVBT_SetReg(MS_U16 u16Addr,MS_U8 u8Data)836 MS_BOOL DMD_DVBT_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
837 {
838 MS_BOOL bRet;
839
840 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_SetReg\n"));
841
842 #ifdef MS_DEBUG
843 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
844 {
845 ULOGD("DEMOD","MDrv_DMD_DVBT_SetReg %x %x\n", u16Addr, u8Data);
846 }
847 #endif
848
849 DMD_LOCK();
850 bRet=MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, u8Data);
851 DMD_UNLOCK();
852 return bRet;
853 }
854
DMD_DVBT_SetSerialControl(MS_BOOL bEnable)855 MS_BOOL DMD_DVBT_SetSerialControl(MS_BOOL bEnable)
856 {
857 MS_BOOL bRet;
858 MS_U8 u8TSClk;
859
860 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_SetSerialControl\n"));
861
862 #ifdef MS_DEBUG
863 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
864 {
865 ULOGD("DEMOD","MDrv_DMD_DVBT_SetSerialControl %x\n", bEnable);
866 }
867 #endif
868
869 DMD_LOCK();
870 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
871 {
872 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=1)
873 {
874 u8TSClk = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[2]; // TS_CLK
875 }
876 else
877 {
878 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
879 }
880 }
881 else
882 {
883 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
884 }
885 bRet=INTERN_DVBT_Serial_Control(bEnable, u8TSClk);
886 DMD_UNLOCK();
887 return bRet;
888 }
889
DMD_DVBT_SetConfig(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG)890 MS_BOOL DMD_DVBT_SetConfig(DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG)
891 {
892 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_SetConfig\n"));
893
894 return MDrv_DMD_DVBT_SetConfigHPLPSetIF(BW, bSerialTS, bPalBG, 0, u32DMD_DVBT_IfFrequency, u32DMD_DVBT_FsFrequency, u8DMD_DVBT_IQSwap);
895 }
896
897
DMD_DVBT_SetConfigHPLP(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel)898 MS_BOOL DMD_DVBT_SetConfigHPLP(DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel)
899 {
900 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_SetConfigHPLP\n"));
901
902 return MDrv_DMD_DVBT_SetConfigHPLPSetIF(BW, bSerialTS, bPalBG, bLPSel, u32DMD_DVBT_IfFrequency, u32DMD_DVBT_FsFrequency, u8DMD_DVBT_IQSwap);
903 }
904
905
DMD_DVBT_SetConfigHPLPSetIF(DMD_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_BOOL bPalBG,MS_BOOL bLPSel,MS_U32 u32IFFreq,MS_U32 u32FSFreq,MS_U8 u8IQSwap)906 MS_BOOL DMD_DVBT_SetConfigHPLPSetIF(DMD_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_BOOL bPalBG, MS_BOOL bLPSel, MS_U32 u32IFFreq, MS_U32 u32FSFreq, MS_U8 u8IQSwap)
907 {
908 MS_BOOL bRet;
909 MS_U8 u8TSClk;
910
911 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_SetConfigHPLPSetIF\n"));
912
913 #ifdef MS_DEBUG
914 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
915 {
916 ULOGD("DEMOD","MDrv_DMD_DVBT_SetConfigHPLPSetIF %d %d %d %d %ld %ld %d\n", BW, bSerialTS, bPalBG, bLPSel, u32IFFreq, u32FSFreq, u8IQSwap);
917 }
918 #endif
919
920 DMD_LOCK();
921 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt != NULL)
922 {
923 if (_sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[0]>=1)
924 {
925 u8TSClk = _sDMD_DVBT_InitData.u8DMD_DVBT_InitExt[2]; // TS_CLK
926 }
927 else
928 {
929 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
930 }
931 }
932 else
933 {
934 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
935 }
936
937 bRet=INTERN_DVBT_Config(BW, bSerialTS, bPalBG, bLPSel, u8TSClk, u32IFFreq, u32FSFreq, u8IQSwap);
938 eDMD_DVBT_BandWidth=BW;
939 DMD_UNLOCK();
940 return bRet;
941 }
942
DMD_DVBT_SetActive(MS_BOOL bEnable)943 MS_BOOL DMD_DVBT_SetActive(MS_BOOL bEnable)
944 {
945 MS_BOOL bRet;
946
947 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_SetActive\n"));
948
949 #ifdef MS_DEBUG
950 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
951 {
952 ULOGD("DEMOD","MDrv_DMD_DVBT_SetActive %d\n", bEnable);
953 }
954 #endif
955
956 DMD_LOCK();
957 bRet=INTERN_DVBT_Active(bEnable);
958 DMD_UNLOCK();
959 return bRet;
960 }
961
DMD_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eType,DMD_LOCK_STATUS * eLockStatus)962 MS_BOOL DMD_DVBT_GetLock(DMD_DVBT_GETLOCK_TYPE eType, DMD_LOCK_STATUS *eLockStatus)
963 {
964 MS_BOOL bRet=TRUE;
965 DMD_LOCK();
966
967 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_GetLock\n"));
968
969 if ( eType == E_DMD_DMD_DVBT_GETLOCK ) // for channel scan
970 {
971 *eLockStatus = INTERN_DVBT_Lock(u16DMD_DVBT_TPS_Timeout, u16DMD_DVBT_FEC_Timeout);
972 }
973 else
974 {
975 if (INTERN_DVBT_GetLock(eType) == TRUE)
976 {
977 *eLockStatus = E_DMD_LOCK;
978 }
979 else
980 {
981 *eLockStatus = E_DMD_UNLOCK;
982 }
983 }
984 DMD_UNLOCK();
985
986 #ifdef MS_DEBUG
987 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
988 {
989 ULOGD("DEMOD","MDrv_DMD_DVBT_GetLock %d\n", bRet);
990 }
991 #endif
992 return bRet;
993 }
994
995
996 /*bryan temp mark*/
997 #if(0)
DMD_DVBT_GetSignalStrengthWithRFPower(MS_U16 * u16Strength,float fRFPowerDbm)998 MS_BOOL DMD_DVBT_GetSignalStrengthWithRFPower(MS_U16 *u16Strength, float fRFPowerDbm)
999 {
1000 MS_U8 u8SarValue;
1001 MS_BOOL bRet;
1002
1003 DMD_LOCK();
1004 if (_sDMD_DVBT_InitData.u8SarChannel != 0xFF)
1005 {
1006 u8SarValue=MDrv_SAR_Adc_GetValue(_sDMD_DVBT_InitData.u8SarChannel);
1007 }
1008 else
1009 {
1010 u8SarValue=0xFF;
1011 }
1012 bRet=INTERN_DVBT_GetSignalStrength(u16Strength, (const DMD_DVBT_InitData *)(&_sDMD_DVBT_InitData), u8SarValue, fRFPowerDbm);
1013 DMD_UNLOCK();
1014
1015 #ifdef MS_DEBUG
1016 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
1017 {
1018 ULOGD("DEMOD","MDrv_DMD_DVBT_GetSignalStrength %d\n", *u16Strength);
1019 }
1020 #endif
1021 return bRet;
1022 }
1023 #endif
1024
1025 #if(0)
DMD_DVBT_GetSignalQualityWithRFPower(MS_U16 * u16Quality,float fRFPowerDbm)1026 MS_BOOL DMD_DVBT_GetSignalQualityWithRFPower(MS_U16 *u16Quality, float fRFPowerDbm)
1027 {
1028 MS_U8 u8SarValue=0;
1029 MS_BOOL bRet=0;
1030
1031 DMD_LOCK();
1032 if (_sDMD_DVBT_InitData.u8SarChannel != 0xFF)
1033 {
1034 u8SarValue=MDrv_SAR_Adc_GetValue(_sDMD_DVBT_InitData.u8SarChannel);
1035 }
1036 else
1037 {
1038 u8SarValue=0xFF;
1039 }
1040 bRet=INTERN_DVBT_GetSignalQuality(u16Quality, (const DMD_DVBT_InitData *)(&_sDMD_DVBT_InitData), u8SarValue, fRFPowerDbm);
1041 DMD_UNLOCK();
1042
1043 #ifdef MS_DEBUG
1044 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
1045 {
1046 ULOGD("DEMOD","MDrv_DMD_DVBT_GetSignalQuality %d\n", *u16Quality);
1047 }
1048 #endif
1049 return bRet;
1050 }
1051 #endif
1052
1053 //arthur
DMD_DVBT_GetIFAGC(MS_U8 * ifagc_reg,MS_U8 * ifagc_reg_lsb,MS_U16 * ifagc_err)1054 MS_BOOL DMD_DVBT_GetIFAGC(MS_U8 *ifagc_reg, MS_U8 *ifagc_reg_lsb, MS_U16 *ifagc_err)
1055 {
1056 MS_BOOL bRet;
1057
1058 DMD_LOCK();
1059 bRet=INTERN_DVBT_GetIFAGC(ifagc_reg, ifagc_reg_lsb, ifagc_err);
1060 DMD_UNLOCK();
1061
1062 return bRet;
1063 }
1064
DMD_DVBT_GetSNR(MS_U32 * noise_power_reg)1065 MS_BOOL DMD_DVBT_GetSNR(MS_U32 *noise_power_reg)
1066 {
1067 DMD_LOCK();
1068 INTERN_DVBT_GetSNR(noise_power_reg);
1069 DMD_UNLOCK();
1070
1071 return TRUE;
1072 }
1073
DMD_DVBT_GetPostViterbiBer(MS_U16 * BitErrPeriod_reg,MS_U32 * BitErr_reg,MS_U16 * PktErr_reg)1074 MS_BOOL DMD_DVBT_GetPostViterbiBer(MS_U16 *BitErrPeriod_reg, MS_U32 *BitErr_reg, MS_U16 *PktErr_reg)
1075 {
1076 MS_BOOL bRet;
1077
1078 DMD_LOCK();
1079 bRet = INTERN_DVBT_GetPostViterbiBer(BitErrPeriod_reg, BitErr_reg, PktErr_reg);
1080 DMD_UNLOCK();
1081
1082 return bRet;
1083 }
1084 #if(0)
DMD_DVBT_GetPreViterbiBer(float * ber)1085 MS_BOOL DMD_DVBT_GetPreViterbiBer(float *ber)
1086 {
1087 MS_BOOL bRet;
1088
1089 DMD_LOCK();
1090 bRet=INTERN_DVBT_GetPreViterbiBer(ber);
1091 DMD_UNLOCK();
1092
1093 return bRet;
1094 }
1095 #endif
1096
DMD_DVBT_GetPacketErr(MS_U16 * pktErr)1097 MS_BOOL DMD_DVBT_GetPacketErr(MS_U16 *pktErr)
1098 {
1099 MS_BOOL bRet;
1100 // float fBER;
1101 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_GetPacketErr\n"));
1102
1103 DMD_LOCK();
1104 //bryan temp mark
1105 //INTERN_DVBT_GetPostViterbiBer(&fBER);
1106 bRet=INTERN_DVBT_GetPacketErr(pktErr);
1107
1108 //bryan temp mark
1109 //if ((*pktErr ==1) && (fBER<= 0.000001)) // for no signal case, from Oga
1110 if ((*pktErr ==1) )
1111 {
1112 *pktErr = 0x3FF;
1113 }
1114 #ifdef MS_DEBUG
1115 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
1116 {
1117 ULOGD("DEMOD","MDrv_DMD_DVBT_GetPacketErr %d\n", *pktErr);
1118 }
1119 #endif
1120 DMD_UNLOCK();
1121
1122 return bRet;
1123 }
1124
DMD_DVBT_GetTPSInfo(MS_U16 * u16Info)1125 MS_BOOL DMD_DVBT_GetTPSInfo(MS_U16 *u16Info)
1126 {
1127 MS_BOOL bRet;
1128
1129 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_GetTPSInfo\n"));
1130
1131 DMD_LOCK();
1132 bRet=INTERN_DVBT_Get_TPS_Info(u16Info);
1133 DMD_UNLOCK();
1134
1135 return bRet;
1136 }
1137
DMD_DVBT_GetCellID(MS_U16 * u16CellID)1138 MS_BOOL DMD_DVBT_GetCellID(MS_U16 *u16CellID)
1139 {
1140 MS_BOOL bRet;
1141
1142 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_GetCellID\n"));
1143
1144 DMD_LOCK();
1145 bRet=INTERN_DVBT_Get_CELL_ID(u16CellID);
1146 DMD_UNLOCK();
1147 #ifdef MS_DEBUG
1148 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
1149 {
1150 ULOGD("DEMOD","MDrv_DMD_DVBT_GetCellID %d\n", *u16CellID);
1151 }
1152 #endif
1153 return bRet;
1154 }
1155
1156 /*bryan temp mark*/
1157 #if(0)
DMD_DVBT_GetFreqOffset(float * pFreqOff)1158 MS_BOOL DMD_DVBT_GetFreqOffset(float *pFreqOff)
1159 {
1160 MS_BOOL bRet=TRUE;
1161 MS_U8 u8BW=8;
1162
1163 DMD_LOCK();
1164 switch (eDMD_DVBT_BandWidth)
1165 {
1166 case E_DMD_RF_CH_BAND_6MHz:
1167 u8BW=6;
1168 break;
1169
1170 case E_DMD_RF_CH_BAND_7MHz:
1171 u8BW=7;
1172 break;
1173
1174 case E_DMD_RF_CH_BAND_8MHz:
1175 default:
1176 u8BW=8;
1177 break;
1178 }
1179 bRet=INTERN_DVBT_Get_FreqOffset(pFreqOff, u8BW);
1180 DMD_UNLOCK();
1181
1182 #ifdef MS_DEBUG
1183 if (_u8DMDDbgLevel >= DMD_DBGLV_DEBUG)
1184 {
1185 ULOGD("DEMOD","MDrv_DMD_DVBT_GetStatus %d %f\n", u8BW, *pFreqOff);
1186 }
1187 #endif
1188 return bRet;
1189 }
1190 #endif
1191
1192 /*bryan temp mark*/
1193 #if(0)
DMD_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel,DMD_CODERATE code_rate,float write_value)1194 MS_BOOL DMD_DVBT_NORDIG_SSI_Table_Write(DMD_CONSTEL constel, DMD_CODERATE code_rate, float write_value)
1195 {
1196 return INTERN_DVBT_NORDIG_SSI_Table_Write(constel, code_rate, write_value);
1197 }
1198
DMD_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel,DMD_CODERATE code_rate,float * read_value)1199 MS_BOOL DMD_DVBT_NORDIG_SSI_Table_Read(DMD_CONSTEL constel, DMD_CODERATE code_rate, float *read_value)
1200 {
1201 return INTERN_DVBT_NORDIG_SSI_Table_Read(constel, code_rate, read_value);
1202 }
1203 #endif
1204
DMD_DVBT_SetPowerState(EN_POWER_MODE u16PowerState)1205 MS_U32 DMD_DVBT_SetPowerState(EN_POWER_MODE u16PowerState)
1206 {
1207 static EN_POWER_MODE _prev_u16PowerState = E_POWER_MECHANICAL;
1208 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
1209
1210 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DMD_DVBT_SetPowerState\n"));
1211
1212 u32Return = u32Return;
1213
1214 if(bIsDVBT == TRUE)
1215 {
1216 if (u16PowerState == E_POWER_SUSPEND)
1217 {
1218 // MDrv_DMD_DVBT_Exit();
1219 DMD_DVBT_Exit();
1220 _prev_u16PowerState = u16PowerState;
1221 u32Return = UTOPIA_STATUS_SUCCESS;//SUSPEND_OK;
1222 }
1223 else if (u16PowerState == E_POWER_RESUME)
1224 {
1225 if (_prev_u16PowerState == E_POWER_SUSPEND)
1226 {
1227 DMD_DVBT_Init(&_sDMD_DVBT_InitData, sizeof(_sDMD_DVBT_InitData));
1228 _prev_u16PowerState = u16PowerState;
1229 u32Return = UTOPIA_STATUS_SUCCESS;//RESUME_OK;
1230 }
1231 else
1232 {
1233 ULOGD("DEMOD","[%s,%5d]It is not suspended yet. We shouldn't resume\n",__FUNCTION__,__LINE__);
1234 u32Return = UTOPIA_STATUS_FAIL;//SUSPEND_FAILED;
1235 }
1236 }
1237 else
1238 {
1239 ULOGD("DEMOD","[%s,%5d]Do Nothing: %d\n",__FUNCTION__,__LINE__,u16PowerState);
1240 u32Return = FALSE;
1241 }
1242 }
1243 else
1244 {
1245 ULOGD("DEMOD","\r\n ====== DVBT doesn't need to Suspend/Resume at Non-DVBT mode ====== \r\n");
1246 u32Return = FALSE;
1247 }
1248 // return UTOPIA_STATUS_SUCCESS;
1249 return u32Return;
1250 }
1251
1252
1253 //-------------------------------------------------------------------------------------------------
1254 // Global Functions
1255 //-------------------------------------------------------------------------------------------------
DVBTOpen(void ** ppInstance,MS_U32 u32ModuleVersion,void * pAttribute)1256 MS_U32 DVBTOpen(void** ppInstance, MS_U32 u32ModuleVersion, void* pAttribute)
1257 {
1258
1259 DVBT_INSTANT_PRIVATE *pDvbtPri= NULL;
1260
1261 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTOpen\n"));
1262
1263 // void *pDvbtPriVoid = NULL;
1264
1265 UtopiaInstanceCreate(sizeof(DVBT_INSTANT_PRIVATE), ppInstance);
1266 UtopiaInstanceGetPrivate(*ppInstance, (void*)&pDvbtPri);
1267 // pDvbtPri = (DVBT_INSTANT_PRIVATE*)pDvbtPriVoid;
1268
1269
1270
1271 pDvbtPri->fpDVBTInit = DMD_DVBT_Init;
1272 pDvbtPri->fpDVBTExit = DMD_DVBT_Exit;
1273 pDvbtPri->fpDVBTSetDbgLevel = DMD_DVBT_SetDbgLevel;
1274 /*bryan temp mark*/
1275 #if(0)
1276 pDvbtPri->fpDVBTGetInfo = DMD_DVBT_GetInfo;
1277 #endif
1278
1279 pDvbtPri->fpDVBTGetLibVer = DMD_DVBT_GetLibVer;
1280 pDvbtPri->fpDVBTGetFWVer = DMD_DVBTGetFWVer;
1281 pDvbtPri->fpDVBTGetReg = DMD_DVBT_GetReg;
1282 pDvbtPri->fpDVBTSetReg = DMD_DVBT_SetReg;
1283 pDvbtPri->fpDVBTSetSerialControl = DMD_DVBT_SetSerialControl;
1284 //pDvbtPri->fpDVBTSetConfig = DMD_DVBT_SetConfig;
1285 //pDvbtPri->fpDVBTSetConfigHPLP = MDrv_DMD_DVBT_SetConfigHPLP;
1286 pDvbtPri->fpDVBTSetConfigHPLPSetIF = DMD_DVBT_SetConfigHPLPSetIF;
1287 pDvbtPri->fpDVBTSetActive = DMD_DVBT_SetActive;
1288 pDvbtPri->fpDVBTGetLock = DMD_DVBT_GetLock;
1289 //pDvbtPri->fpDVBTGetSignalStrength = MDrv_DMD_DVBT_GetSignalStrength;
1290 /*bryan temp mark*/
1291 #if(0)
1292 pDvbtPri->fpDVBTGetSignalStrengthWithRFPower = DMD_DVBT_GetSignalStrengthWithRFPower;
1293 #endif
1294
1295 //pDvbtPri->fpDVBTGetSignalQuality = MDrv_DMD_DVBT_GetSignalQuality;
1296 #if(0)
1297 pDvbtPri->fpDVBTGetSignalQualityWithRFPower = DMD_DVBT_GetSignalQualityWithRFPower;
1298 #endif
1299
1300 //arthur
1301 pDvbtPri->fpDVBTGetSNR = DMD_DVBT_GetSNR;
1302 pDvbtPri->fpDVBTGetPostViterbiBer =DMD_DVBT_GetPostViterbiBer;
1303 pDvbtPri->fpDVBT_GetIFAGC=DMD_DVBT_GetIFAGC;
1304
1305 #if 0
1306 pDvbtPri->fpDVBTGetPreViterbiBer = DMD_DVBT_GetPreViterbiBer;
1307 #endif
1308
1309 pDvbtPri->fpDVBTGetPacketErr = DMD_DVBT_GetPacketErr;
1310 pDvbtPri->fpDVBTGetTPSInfo = DMD_DVBT_GetTPSInfo;
1311 pDvbtPri->fpDVBTGetCellID = DMD_DVBT_GetCellID;
1312
1313 #if(0)
1314 pDvbtPri->fpDVBTGetFreqOffset = DMD_DVBT_GetFreqOffset;
1315 #endif
1316
1317 #if(0)
1318 pDvbtPri->fpDVBTNORDIGSSITableWrite = DMD_DVBT_NORDIG_SSI_Table_Write;
1319 pDvbtPri->fpDVBTNORDIGSSITableRead = DMD_DVBT_NORDIG_SSI_Table_Read;
1320 #endif
1321
1322 pDvbtPri->fpDVBTSetPowerState = DMD_DVBT_SetPowerState;
1323
1324 //return TRUE;
1325 return UTOPIA_STATUS_SUCCESS;
1326 }
1327
DVBTIoctl(void * pInstance,MS_U32 u32Cmd,void * pArgs)1328 MS_U32 DVBTIoctl(void* pInstance, MS_U32 u32Cmd, void* pArgs)
1329 {
1330
1331 void* pModule = NULL;
1332 UtopiaInstanceGetModule(pInstance, &pModule);
1333
1334 //void* pResource = NULL;
1335
1336 DVBT_INSTANT_PRIVATE* psDVBTInstPri = NULL;
1337 void* psDVBTInstPriVoid = NULL;
1338 UtopiaInstanceGetPrivate(pInstance, (void**)&psDVBTInstPriVoid);
1339 psDVBTInstPri = (DVBT_INSTANT_PRIVATE*)psDVBTInstPriVoid;
1340
1341 MS_BOOL bRet = FALSE;
1342
1343 #if 0
1344 if (UtopiaResourceObtain(pModule, DVBT_POOL_ID_DMD0, &pResource) != 0)
1345 {
1346 DMD_DBG(ULOGD("DEMOD","UtopiaResourceObtainToInstant fail\n"));
1347 return UTOPIA_STATUS_ERR_RESOURCE;
1348 }
1349
1350 psDMD_DVBT_ResData = ((PDVBT_RESOURCE_PRIVATE)pResource)->sDMD_DVBT_ResData;
1351 #endif
1352
1353
1354
1355 switch (u32Cmd)
1356 {
1357 case DMD_DVBT_DRV_CMD_Init:
1358 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_Init\n"));
1359 //bryan test
1360 #if(0)
1361 bRet = psDVBTInstPri->fpDVBTInit( &(((PDVBT_INIT_PARAM)pArgs)->DMD_DVBT_InitData), ((PDVBT_INIT_PARAM)pArgs)->u32InitDataLen);
1362 #else
1363 bRet = psDVBTInstPri->fpDVBTInit( (((PDVBT_INIT_PARAM)pArgs)->DMD_DVBT_InitData), ((PDVBT_INIT_PARAM)pArgs)->u32InitDataLen);
1364 #endif
1365 ((PDVBT_INIT_PARAM)pArgs)->ret=bRet;
1366 break;
1367 case DMD_DVBT_DRV_CMD_Exit:
1368 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_Exit\n"));
1369 bRet = psDVBTInstPri->fpDVBTExit();
1370 ((PDVBT_EXIT_PARAM)pArgs)->ret=bRet;
1371 break;
1372 case DMD_DVBT_DRV_CMD_SetDbgLeve:
1373 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_SetDbgLevel\n"));
1374 bRet = psDVBTInstPri->fpDVBTSetDbgLevel(((PDVBT_SETDBG_LEVEL_PARAM)pArgs)->u8DbgLevel);
1375 ((PDVBT_SETDBG_LEVEL_PARAM)pArgs)->ret=bRet;
1376 break;
1377 /*bryan temp mark*/
1378 #if(0)
1379 case DMD_DVBT_DRV_CMD_GetInfo:
1380 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_GetInfo\n"));
1381 ((PDVBT_GETINFO_PARAM)pArgs)->pInfo = psDVBTInstPri->fpDVBTGetInfo(((PDVBT_GETINFO_PARAM)pArgs)->eInfoType);
1382 bRet = TRUE;
1383 ((PDVBT_GETINFO_PARAM)pArgs)->ret=bRet;
1384 break;
1385 #endif
1386 case DMD_DVBT_DRV_CMD_GetLibVer:
1387 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_GetLibVer\n"));
1388 bRet = psDVBTInstPri->fpDVBTGetLibVer(((PDVBT_GETLIBVER_PARAM)pArgs)->ppVersion);
1389 ((PDVBT_GETLIBVER_PARAM)pArgs)->ret=bRet;
1390 break;
1391 case DMD_DVBT_DRV_CMD_GetFWVer:
1392 // ULOGD("DEMOD","bryan debug check demod GetFWVer DVBT!!\n");
1393 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBTGetFWVer\n"));
1394 bRet = psDVBTInstPri->fpDVBTGetFWVer(((PDVBT_GETFWVER_PARAM)pArgs)->ver);
1395 ((PDVBT_GETFWVER_PARAM)pArgs)->ret=bRet;
1396 break;
1397 case DMD_DVBT_DRV_CMD_GetReg:
1398 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_GetReg\n"));
1399 bRet = psDVBTInstPri->fpDVBTGetReg( ((PDVBT_GETREG_PARAM)pArgs)->u16Addr, ((PDVBT_GETREG_PARAM)pArgs)->pu8Data);
1400 ((PDVBT_GETREG_PARAM)pArgs)->ret=bRet;
1401 break;
1402 case DMD_DVBT_DRV_CMD_SetReg:
1403 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_SetReg\n"));
1404 bRet = psDVBTInstPri->fpDVBTSetReg( ((PDVBT_SETREG_PARAM)pArgs)->u16Addr, ((PDVBT_SETREG_PARAM)pArgs)->u8Data);
1405 ((PDVBT_SETREG_PARAM)pArgs)->ret=bRet;
1406 break;
1407 case DMD_DVBT_DRV_CMD_SetSerialControl:
1408 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_SetSerialControl\n"));
1409 bRet = psDVBTInstPri->fpDVBTSetSerialControl( ((PDVBT_SetSerialControl_PARAM)pArgs)->bEnable);
1410 ((PDVBT_SetSerialControl_PARAM)pArgs)->ret=bRet;
1411 break;
1412 /*
1413 case DMD_DVBT_DRV_CMD_SetConfig:
1414 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_SetConfig\n"));
1415 u32Ret = psDVBTInstPri->fpDVBTSetConfig( ((PDVBT_SetConfig_PARAM)pArgs)->BW, ((PDVBT_SetConfig_PARAM)pArgs)->bSerialTS, ((PDVBT_SetConfig_PARAM)pArgs)->bPalBG);
1416 break;
1417 case DMD_DVBT_DRV_CMD_SetConfigHPLP:
1418 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_SetConfigHPLP\n"));
1419 u32Ret = psDVBTInstPri->fpDVBTSetConfigHPLP(((PDVBT_SetConfigHPLP_PARAM)pArgs)->BW, ((PDVBT_SetConfigHPLP_PARAM)pArgs)->bSerialTS, ((PDVBT_SetConfigHPLP_PARAM)pArgs)->bPalBG, ((PDVBT_SetConfigHPLP_PARAM)pArgs)->bLPSel);
1420 break;
1421 */
1422 case DMD_DVBT_DRV_CMD_SetConfigHPLPSetIF:
1423 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_SetConfigHPLPSetIF\n"));
1424 bRet = psDVBTInstPri->fpDVBTSetConfigHPLPSetIF(((PDVBT_SetConfigHPLPSetIF_PARAM)pArgs)->BW, ((PDVBT_SetConfigHPLPSetIF_PARAM)pArgs)->bSerialTS, ((PDVBT_SetConfigHPLPSetIF_PARAM)pArgs)->bPalBG, ((PDVBT_SetConfigHPLPSetIF_PARAM)pArgs)->bLPSel, ((PDVBT_SetConfigHPLPSetIF_PARAM)pArgs)->u32IFFreq, ((PDVBT_SetConfigHPLPSetIF_PARAM)pArgs)->u32FSFreq, ((PDVBT_SetConfigHPLPSetIF_PARAM)pArgs)->u8IQSwap);
1425 ((PDVBT_SetConfigHPLPSetIF_PARAM)pArgs)->ret=bRet;
1426 break;
1427 case DMD_DVBT_DRV_CMD_SetActive:
1428 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_SetActive\n"));
1429 bRet = psDVBTInstPri->fpDVBTSetActive(((PDVBT_SetActive_PARAM)pArgs)->bEnable);
1430 ((PDVBT_SetActive_PARAM)pArgs)->ret=bRet;
1431 break;
1432 case DMD_DVBT_DRV_CMD_GetLock:
1433 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_GetLock\n"));
1434 bRet = psDVBTInstPri->fpDVBTGetLock(((PDVBT_GetLock_PARAM)pArgs)->eType, ((PDVBT_GetLock_PARAM)pArgs)->eLockStatus);
1435 ((PDVBT_GetLock_PARAM)pArgs)->ret=bRet;
1436 break;
1437 /*
1438 case DMD_DVBT_DRV_CMD_GetSignalStrength:
1439 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_GetSignalStrength\n"));
1440 u32Ret = psDVBTInstPri->fpDVBTGetSignalStrength(((PDVBT_GetSignalStrength_PARAM)pArgs)->u16Strength);
1441 break;
1442 */
1443
1444 /*
1445 case DMD_DVBT_DRV_CMD_GetSignalStrengthWithRFPower:
1446 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_GetSignalStrengthWithRFPower\n"));
1447 bRet = psDVBTInstPri->fpDVBTGetSignalStrengthWithRFPower(((PDVBT_GetSignalStrengthWithRFPower_PARAM)pArgs)->u16Strength, ((PDVBT_GetSignalStrengthWithRFPower_PARAM)pArgs)->fRFPowerDbm);
1448 ((PDVBT_GetSignalStrengthWithRFPower_PARAM)pArgs)->ret=bRet;
1449 break;
1450 */
1451
1452 /*
1453 case DMD_DVBT_DRV_CMD_GetSignalQuality:
1454 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_GetSignalQuality\n"));
1455 u32Ret = psDVBTInstPri->fpDVBTGetSignalQuality(((PDVBT_GetSignalQuality_PARAM)pArgs)->u16Quality);
1456 break;
1457 */
1458
1459 /*
1460 case DMD_DVBT_DRV_CMD_GetSignalQualityWithRFPower:
1461 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_GetSignalQualityWithRFPower\n"));
1462 bRet = psDVBTInstPri->fpDVBTGetSignalQualityWithRFPower(((PDVBT_GetSignalQualityWithRFPower_PARAM)pArgs)->u16Quality, ((PDVBT_GetSignalQualityWithRFPower_PARAM)pArgs)->fRFPowerDbm);
1463 ((PDVBT_GetSignalQualityWithRFPower_PARAM)pArgs)->ret=bRet;
1464 break;
1465 */
1466 /* bryan temp mark*/
1467 // arthur
1468 case DMD_DVBT_DRV_CMD_GetSNR:
1469 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_GetSNR\n"));
1470 bRet = psDVBTInstPri->fpDVBTGetSNR(((PDVBT_GetSNR_PARAM)pArgs)->noise_power_reg);
1471 ((PDVBT_GetSNR_PARAM)pArgs)->ret=bRet;
1472 break;
1473
1474 case DMD_DVBT_DRV_CMD_GetIFAGC:
1475 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_GetIFAGC\n"));
1476 bRet=psDVBTInstPri->fpDVBT_GetIFAGC(((PDVBT_GetIFAGC_PARAM)pArgs)->ifagc_reg,\
1477 ((PDVBT_GetIFAGC_PARAM)pArgs)->ifagc_reg_lsb,\
1478 ((PDVBT_GetIFAGC_PARAM)pArgs)->ifagc_err_reg);
1479 ((PDVBT_GetIFAGC_PARAM)pArgs)->ret=bRet;
1480 break;
1481
1482 /*bryan temp mark */
1483
1484 case DMD_DVBT_DRV_CMD_GetPostViterbiBer:
1485 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_GetPostViterbiBer\n"));
1486 bRet = psDVBTInstPri->fpDVBTGetPostViterbiBer(((PDVBT_GetPostViterbiBer_PARAM)pArgs)->BitErrPeriod_reg, ((PDVBT_GetPostViterbiBer_PARAM)pArgs)->BitErr_reg, ((PDVBT_GetPostViterbiBer_PARAM)pArgs)->PktErr_reg);
1487 ((PDVBT_GetPostViterbiBer_PARAM)pArgs)->ret=bRet;
1488 break;
1489
1490 /*bryan temp mark */
1491 #if(0)
1492 case DMD_DVBT_DRV_CMD_GetPreViterbiBer:
1493 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_GetPreViterbiBer\n"));
1494 bRet = psDVBTInstPri->fpDVBTGetPreViterbiBer(((PDVBT_GetPreViterbiBer_PARAM)pArgs)->ber);
1495 ((PDVBT_GetPreViterbiBer_PARAM)pArgs)->ret=bRet;
1496 break;
1497 #endif
1498
1499 case DMD_DVBT_DRV_CMD_GetPacketErr:
1500 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_GetPacketErr\n"));
1501 bRet = psDVBTInstPri->fpDVBTGetPacketErr(((PDVBT_GetPacketErr_PARAM)pArgs)->pktErr);
1502 ((PDVBT_GetPacketErr_PARAM)pArgs)->ret=bRet;
1503 break;
1504 case DMD_DVBT_DRV_CMD_GetTPSInfo:
1505 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBToctl - MDrv_DMD_DVBT_GetTPSInfo\n"));
1506 bRet = psDVBTInstPri->fpDVBTGetTPSInfo(((PDVBT_GetTPSInfo_PARAM)pArgs)->u16Info);
1507 ((PDVBT_GetTPSInfo_PARAM)pArgs)->ret=bRet;
1508 break;
1509 case DMD_DVBT_DRV_CMD_GetCellID:
1510 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_GetCellID\n"));
1511 bRet = psDVBTInstPri->fpDVBTGetCellID(((PDVBT_GetCellID_PARAM)pArgs)->u16CellID);
1512 ((PDVBT_GetCellID_PARAM)pArgs)->ret=bRet;
1513 break;
1514
1515 /*bryan temp mark*/
1516 #if(0)
1517 case DMD_DVBT_DRV_CMD_GetFreqOffset:
1518 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_GetFreqOffset\n"));
1519 bRet = psDVBTInstPri->fpDVBTGetFreqOffset(((PDVBT_GetFreqOffset_PARAM)pArgs)->pFreqOff);
1520 ((PDVBT_GetFreqOffset_PARAM)pArgs)->ret=bRet;
1521 break;
1522 #endif
1523 /*bryan temp mark*/
1524 #if(0)
1525 case DMD_DVBT_DRV_CMD_NORDIGSSITableWrite:
1526 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_NORDIG_SSI_Table_Write\n"));
1527 bRet = psDVBTInstPri->fpDVBTNORDIGSSITableWrite(((PDVBT_NORDIGSSITableWrite_PARAM)pArgs)->constel, ((PDVBT_NORDIGSSITableWrite_PARAM)pArgs)->code_rate, ((PDVBT_NORDIGSSITableWrite_PARAM)pArgs)->write_value);
1528 ((PDVBT_NORDIGSSITableWrite_PARAM)pArgs)->ret=bRet;
1529 break;
1530 case DMD_DVBT_DRV_CMD_NORDIGSSITableRead:
1531 DMD_DBG(ULOGD("DEMOD","DVBTIoctl - MDrv_DMD_DVBT_NORDIG_SSI_Table_Read\n"));
1532 bRet = psDVBTInstPri->fpDVBTNORDIGSSITableRead(((PDVBT_NORDIGSSITableRead_PARAM)pArgs)->constel, ((PDVBT_NORDIGSSITableRead_PARAM)pArgs)->code_rate, ((PDVBT_NORDIGSSITableRead_PARAM)pArgs)->read_value);
1533 ((PDVBT_NORDIGSSITableRead_PARAM)pArgs)->ret=bRet;
1534 break;
1535 #endif
1536
1537 case DMD_DVBT_DRV_CMD_SetPowerState:
1538 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTIoctl - MDrv_DMD_DVBT_SetPowerState\n"));
1539 bRet = psDVBTInstPri->fpDVBTSetPowerState(((PDVBT_SetPowerState_PARAM)pArgs)->u16PowerState);
1540 ((PDVBT_SetPowerState_PARAM)pArgs)->ret=bRet;
1541 break;
1542 default:
1543 break;
1544 }
1545
1546 //jway suggest UtopiaResourceRelease(pResource);
1547
1548 return (bRet ? UTOPIA_STATUS_SUCCESS : UTOPIA_STATUS_FAIL);
1549 }
1550
DVBTClose(void * pInstance)1551 MS_U32 DVBTClose(void* pInstance)
1552 {
1553 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTClose\n"));
1554
1555 UtopiaInstanceDelete(pInstance);
1556
1557 return UTOPIA_STATUS_SUCCESS;
1558 }
1559
DVBTStr(MS_U32 u32PowerState,void * pModule)1560 MS_U32 DVBTStr(MS_U32 u32PowerState, void* pModule)
1561 {
1562 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
1563 MS_U32 u32Ret = 0;
1564
1565 //UtopiaModuleGetSTRPrivate(pModule, (void**));
1566 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTStr\n"));
1567
1568 if (u32PowerState == E_POWER_SUSPEND)
1569 {
1570 /* Please Implement Module Suspend Flow Here. */
1571 u32Ret = DMD_DVBT_SetPowerState(E_POWER_SUSPEND);
1572
1573 if(u32Ret == TRUE)
1574 u32Return = UTOPIA_STATUS_SUCCESS;//SUSPEND_OK;
1575 else
1576 u32Return = UTOPIA_STATUS_FAIL;
1577
1578 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c][DVBTStr] SUSPEND !\n"));
1579 }
1580 else if (u32PowerState == E_POWER_RESUME)
1581 {
1582 /* Please Implement Module Resume Flow Here. */
1583 u32Ret = DMD_DVBT_SetPowerState(E_POWER_RESUME);
1584
1585 if(u32Ret == TRUE)
1586 u32Return = UTOPIA_STATUS_SUCCESS;//RESUME_OK;
1587 else
1588 u32Return = UTOPIA_STATUS_FAIL;
1589
1590 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c][DVBTStr] RESUME !\n"));
1591 }
1592 else
1593 {
1594 u32Return = UTOPIA_STATUS_FAIL;
1595 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c][DVBTStr] OTHERS !\n"));
1596 }
1597
1598 return u32Return;// for success
1599 }
1600
DVBTRegisterToUtopia(void)1601 void DVBTRegisterToUtopia(void)
1602 {
1603 // 1. deal with module
1604
1605 void* pUtopiaModule = NULL;
1606 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c]DVBTRegisterToUtopia\n"));
1607 // UtopiaModuleCreate(MODULE_DVBT, 8, &pUtopiaModule); //bryan: why this was taken out
1608 UtopiaModuleCreate(MODULE_DVBT, 8, &pUtopiaModule);
1609 UtopiaModuleRegister(pUtopiaModule);
1610 UtopiaModuleSetupFunctionPtr(pUtopiaModule, (FUtopiaOpen)DVBTOpen, (FUtopiaClose)DVBTClose, (FUtopiaIOctl)DVBTIoctl);
1611
1612 // Utopia2K STR
1613 #if defined(MSOS_TYPE_LINUX_KERNEL)
1614 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT_v2.c][DVBTRegisterToUtopia] KERNEL DVBTStr!\n"));
1615 UtopiaModuleSetupSTRFunctionPtr(pUtopiaModule,(FUtopiaSTR)DVBTStr);
1616 #endif
1617 }
1618
1619
1620