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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvAVD.c
98 /// @brief AVD Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106 // Common Definition
107 #ifdef MSOS_TYPE_LINUX_KERNEL
108 #include <linux/string.h>
109 #else
110 #include <string.h>
111 #include <stdio.h>
112 #include <math.h>
113 #endif
114
115 #include "MsCommon.h"
116 #include "MsVersion.h"
117 #include "MsOS.h"
118
119 // Internal Definition
120 //#include "regCHIP.h"
121 //#include "regAVD.h"
122 //#include "mapi_tuner.h"
123 #include "drvSYS.h"
124 #include "drvDMD_VD_MBX.h"
125 #include "drvDMD_INTERN_DVBT2.h"
126 #include "drvDMD_INTERN_DVBT2_v2.h"
127 #include "halDMD_INTERN_DVBT2.h"
128 #include "halDMD_INTERN_common.h"
129 #include "../../include/drvSAR.h" // for Utopia2
130 //#include "../sar/drvSAR.h"
131 #include "utopia.h"
132 #include "ULog.h"
133 //-------------------------------------------------------------------------------------------------
134 // Driver Compiler Options
135 //-------------------------------------------------------------------------------------------------
136
137
138 //-------------------------------------------------------------------------------------------------
139 // Local Defines
140 //-------------------------------------------------------------------------------------------------
141 #define DVBT2_BER_TH_HY 0.1
142 static float fBerFilteredDVBT2 = -1.0;
143
144 static float dvbt2_ssi_dbm_nordigp1[][6] =
145 {
146 { -95.7, -94.4, -93.6, -92.6, -92.0, -91.5},
147 { -90.8, -89.1, -87.9, -86.7, -85.8, -85.2},
148 { -86.9, -84.6, -83.2, -81.4, -80.3, -79.7},
149 { -83.5, -80.4, -78.6, -76.0, -74.4, -73.3},
150 };
151
152 // cr, 3/5(1), 2/3(2), 3/4 (3)
153 float fT2_SSI_formula[][12]=
154 {
155 {1.0/5, 97.0, 3.0/2, 82.0, 16.0/5, 50.0, 29.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/5
156 {2.0/3, 95.0, 9.0/5, 77.0, 17.0/5, 43.0, 14.0/5.0, 15.0, 13.0/15, 2.0, 2.0/5, 0.0}, // CR2/3
157 {1.0/2, 93.0, 19.0/10, 74.0, 31.0/10, 43.0, 22.0/10.0, 21.0, 18.0/15, 3.0, 3.0/5, 0.0}, // CR3/4
158 };
159
160 //arthur
161 static float dvbt2_sqi_db_nordigp1[][6] =
162 {
163 { 3.5, 4.7, 5.6, 6.6, 7.2, 7.7},
164 { 8.7, 10.1, 11.4, 12.5, 13.3, 13.8},
165 { 13.0, 14.8, 16.2, 17.7, 18.7, 19.4},
166 { 17.0, 19.4, 20.8, 22.9, 24.3, 25.1},
167 };
168 //-------------------------------------------------------------------------------------------------
169 // Local Structurs
170 //-------------------------------------------------------------------------------------------------
171
172
173 //-------------------------------------------------------------------------------------------------
174 // Global Variables
175 //-------------------------------------------------------------------------------------------------
176 #define DMD_LOCK() \
177 do{ \
178 MS_ASSERT(MsOS_In_Interrupt() == FALSE); \
179 if (_u8DMDDbgLevel == DMD_T2_DBGLV_DEBUG) printf("%s lock mutex\n", __FUNCTION__);\
180 MsOS_ObtainMutex(_s32DMD_DVBT2_Mutex, MSOS_WAIT_FOREVER);\
181 }while(0)
182
183 #define DMD_UNLOCK() \
184 do{ \
185 MsOS_ReleaseMutex(_s32DMD_DVBT2_Mutex);\
186 if (_u8DMDDbgLevel == DMD_T2_DBGLV_DEBUG) printf("%s unlock mutex\n", __FUNCTION__); \
187 }while(0)
188
189 //-------------------------------------------------------------------------------------------------
190 // Local Variables
191 //-------------------------------------------------------------------------------------------------
192 #if 1
193 /*static MSIF_Version _drv_dmd_dvbt2_intern_version = {
194 .MW = { DMD_DVBT2_INTERN_VER, },
195 };*/
196 #else
197 static MSIF_Version _drv_dmd_dvbt_intern_version;
198 #endif
199
200 #if 0
201 //static DMD_DVBT2_InitData _sDMD_DVBT2_InitData;
202 static DMD_DVBT2_InitData_Transform _sDMD_DVBT2_InitData;
203 static DMD_T2_DbgLv _u8DMDDbgLevel=DMD_T2_DBGLV_NONE;
204 static MS_S32 _s32DMD_DVBT2_Mutex=-1;
205 static DMD_DVBT2_Info sDMD_DVBT2_Info;
206 //static MS_U16 u16DMD_DVBT2_P1_Timeout = 600, u16DMD_DVBT2_FEC_Timeout=6000;
207 static MS_U16 u16DMD_DVBT2_P1_Timeout = 1000, u16DMD_DVBT2_FEC_Timeout=6000;
208 static MS_U32 u32DMD_DVBT2_IfFrequency = 5000L, u32DMD_DVBT2_FsFrequency = 24000L;
209 //static MS_U8 u8DMD_DVBT2_IQSwap=0;
210 static DMD_DVBT2_RF_CHANNEL_BANDWIDTH eDMD_DVBT2_BandWidth=E_DMD_T2_RF_BAND_8MHz;
211 MS_U32 u32DMD_DVBT2_DRAM_START_ADDR;
212 MS_U32 u32DMD_DVBT2_EQ_START_ADDR;
213 MS_U32 u32DMD_DVBT2_TDI_START_ADDR;
214 MS_U32 u32DMD_DVBT2_DJB_START_ADDR;
215 MS_U32 u32DMD_DVBT2_FW_START_ADDR;
216 #endif
217 //-------------------------------------------------------------------------------------------------
218 // Debug Functions
219 //-------------------------------------------------------------------------------------------------
220 #ifdef MS_DEBUG
221 #define DMD_DBG(x) (x)
222 #else
223 #define DMD_DBG(x) (x)
224 #endif
225 //-------------------------------------------------------------------------------------------------
226 // Local Functions
227 //-------------------------------------------------------------------------------------------------
228 static void* ppDVBT2Instant = NULL;
229 static MS_U32 u32DVBT2open = 0;
230 static MS_U8 u8DVBT2UtopiaOpen = 0; //for SetStillImagePara is earlier called than Init
231
232 //-------------------------------------------------------------------------------------------------
233 // Global Functions
234 //-------------------------------------------------------------------------------------------------
MDrv_DMD_DVBT2_Init(DMD_DVBT2_InitData * pDMD_DVBT2_InitData,MS_U32 u32InitDataLen)235 MS_BOOL MDrv_DMD_DVBT2_Init(DMD_DVBT2_InitData *pDMD_DVBT2_InitData, MS_U32 u32InitDataLen)
236 {
237 void* pAttribte = NULL;
238
239 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_Init\n"));
240
241 DVBT2_INIT_PARAM Drv_DVBT2_INIT_PARAM;
242 DMD_DVBT2_InitData_Transform Init_Para_Temp;
243 Drv_DVBT2_INIT_PARAM.ret=false;
244
245 Init_Para_Temp.u8DMD_DVBT2_DSPRegInitExt=pDMD_DVBT2_InitData->u8DMD_DVBT2_DSPRegInitExt;
246 Init_Para_Temp.u8DMD_DVBT2_DSPRegInitSize=pDMD_DVBT2_InitData->u8DMD_DVBT2_DSPRegInitSize;
247 Init_Para_Temp.u8DMD_DVBT2_InitExt=pDMD_DVBT2_InitData->u8DMD_DVBT2_InitExt;
248 Init_Para_Temp.u8SarChannel=pDMD_DVBT2_InitData->u8SarChannel;
249 Init_Para_Temp.u32EqStartAddr=pDMD_DVBT2_InitData->u32EqStartAddr;
250 Init_Para_Temp.u32TdiStartAddr=pDMD_DVBT2_InitData->u32TdiStartAddr;
251 Init_Para_Temp.u32DjbStartAddr=pDMD_DVBT2_InitData->u32DjbStartAddr;
252 Init_Para_Temp.u32FwStartAddr=pDMD_DVBT2_InitData->u32FwStartAddr;
253
254 Drv_DVBT2_INIT_PARAM.pDMD_DVBT2_InitData=&Init_Para_Temp;
255 Drv_DVBT2_INIT_PARAM.u32InitDataLen=sizeof(Init_Para_Temp);
256
257 if(u8DVBT2UtopiaOpen == 0) // First time open
258 {
259 if(UtopiaOpen(MODULE_DVBT2/*|KERNEL_MODE*/ , &ppDVBT2Instant, 0, pAttribte) == UTOPIA_STATUS_SUCCESS) //kernel space
260 //if(UtopiaOpen(MODULE_DVBT , &ppDVBTInstant, 0, pAttribte) == UTOPIA_STATUS_SUCCESS) //user space
261 {
262 u32DVBT2open = 1;
263 // DMD_DBG(ULOGD("DEMOD","\r\n ======== DVBT2 Open Successful %x =========", (WORD)u32DVBT2open));
264 DMD_DBG(ULOGD("DEMOD","\r\n ======== DVBT2 Open Successful ========= \n"));
265 }
266 else
267 {
268 // DMD_DBG(ULOGD("DEMOD","\r\n ======== DVBT2 Open Fail %x =========", (WORD)u32DVBT2open));
269 DMD_DBG(ULOGD("DEMOD","\r\n ======== DVBT2 Open Fail =========\n"));
270 return false;
271 }
272
273 u8DVBT2UtopiaOpen = 1;
274 }
275
276 UtopiaIoctl(ppDVBT2Instant,DMD_DVBT2_DRV_CMD_Init,&Drv_DVBT2_INIT_PARAM);
277 return Drv_DVBT2_INIT_PARAM.ret;
278
279 #if 0
280 char pDMD_DVBT2_MutexString[16];
281 MS_U8 u8ADCIQMode = 0, u8PadSel = 0, bPGAEnable = 0, u8PGAGain = 5;
282 MS_BOOL bRFAGCTristateEnable = 1;
283 MS_BOOL bIFAGCTristateEnable = 0;
284
285 if (_s32DMD_DVBT2_Mutex != -1)
286 {
287 DMD_DBG(printf("MDrv_DMD_DVBT2_Init more than once\n"));
288 return FALSE;
289 }
290
291 if (NULL == strncpy(pDMD_DVBT2_MutexString,"Mutex DMD DVBT2",16))
292 {
293 DMD_DBG(printf("MDrv_DMD_DVBT2_Init strcpy Fail\n"));
294 return FALSE;
295 }
296 _s32DMD_DVBT2_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, pDMD_DVBT2_MutexString, MSOS_PROCESS_SHARED);
297 if (_s32DMD_DVBT2_Mutex == -1)
298 {
299 DMD_DBG(printf("MDrv_DMD_DVBT2_Init Create Mutex Fail\n"));
300 return FALSE;
301 }
302 //_u8DMDDbgLevel = DMD_DBGLV_DEBUG;
303 #ifdef MS_DEBUG
304 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_INFO)
305 {
306 printf("MDrv_DMD_DVBT2_Init\n");
307 }
308 #endif
309
310 if ( sizeof(_sDMD_DVBT2_InitData) == u32InitDataLen)
311 {
312 memcpy(&_sDMD_DVBT2_InitData, pDMD_DVBT2_InitData, u32InitDataLen);
313 }
314 else
315 {
316 DMD_DBG(printf("MDrv_DMD_DVBT2_Init input data structure incorrect\n"));
317 return FALSE;
318 }
319
320 if (_sDMD_DVBT2_InitData.u8SarChannel != 0xFF)
321 {
322 MDrv_SAR_Adc_Config(_sDMD_DVBT2_InitData.u8SarChannel, TRUE);
323 }
324
325 DMD_LOCK();
326 MDrv_SYS_DMD_VD_MBX_SetType(E_DMD_VD_MBX_TYPE_DVBT2);
327 HAL_DMD_RegInit();
328
329 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt != NULL)
330 {
331 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[0]>=2)
332 {
333 bRFAGCTristateEnable = (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[3] & (BIT_(0))) ? TRUE : FALSE; // RFAGC tristate control
334 bIFAGCTristateEnable = (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[3] & (BIT_(4))) ? TRUE : FALSE; // IFAGC tristate control
335 }
336 else
337 {
338 bRFAGCTristateEnable = 1;
339 bIFAGCTristateEnable = 0;
340 }
341 }
342 else
343 {
344 bRFAGCTristateEnable = 1;
345 bIFAGCTristateEnable = 0;
346 }
347
348 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt != NULL)
349 {
350 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[0]>=3)
351 {
352 u32DMD_DVBT2_IfFrequency = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[4]; // IF frequency
353 u32DMD_DVBT2_IfFrequency = (u32DMD_DVBT2_IfFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[5]; // IF frequency
354 u32DMD_DVBT2_IfFrequency = (u32DMD_DVBT2_IfFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[6]; // IF frequency
355 u32DMD_DVBT2_IfFrequency = (u32DMD_DVBT2_IfFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[7]; // IF frequency
356 u32DMD_DVBT2_FsFrequency = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[8]; // FS frequency
357 u32DMD_DVBT2_FsFrequency = (u32DMD_DVBT2_FsFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[9]; // FS frequency
358 u32DMD_DVBT2_FsFrequency = (u32DMD_DVBT2_FsFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[10]; // FS frequency
359 u32DMD_DVBT2_FsFrequency = (u32DMD_DVBT2_FsFrequency<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[11]; // FS frequency
360 //u8DMD_DVBT2_IQSwap = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[12]; // IQ Swap
361
362 u8ADCIQMode = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[13]; // u8ADCIQMode : 0=I path, 1=Q path, 2=both IQ
363 u8PadSel = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[14]; // u8PadSel : 0=Normal, 1=analog pad
364 bPGAEnable = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[15]; // bPGAEnable : 0=disable, 1=enable
365 u8PGAGain = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[16]; // u8PGAGain : default 5
366 }
367 else
368 {
369
370 }
371 }
372 else
373 {
374
375 }
376 #ifdef MS_DEBUG
377 printf("u32DMD_DVBT2_IfFrequency %ld\n",u32DMD_DVBT2_IfFrequency);
378 printf("u32DMD_DVBT2_FsFrequency %ld\n",u32DMD_DVBT2_FsFrequency);
379 #endif
380
381 u16DMD_DVBT2_P1_Timeout = 1000; //600;
382 u16DMD_DVBT2_FEC_Timeout = 6000;
383 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt != NULL)
384 {
385 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[0]>=4)
386 {
387 u16DMD_DVBT2_P1_Timeout = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[17]; // P1 timeout in ms
388 u16DMD_DVBT2_P1_Timeout = (u16DMD_DVBT2_P1_Timeout<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[18];
389 if (u16DMD_DVBT2_P1_Timeout < 600) u16DMD_DVBT2_P1_Timeout=600;
390 //printf("u16DMD_DVBT2_P1_Timeout %d\n",u16DMD_DVBT2_P1_Timeout);
391
392 u16DMD_DVBT2_FEC_Timeout = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[19]; // FEC timeout in ms
393 u16DMD_DVBT2_FEC_Timeout = (u16DMD_DVBT2_FEC_Timeout<<8)+_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[20];
394 if (u16DMD_DVBT2_FEC_Timeout < 6000) u16DMD_DVBT2_FEC_Timeout=6000;
395 //printf("u16DMD_DVBT2_FEC_Timeout %d\n",u16DMD_DVBT2_FEC_Timeout);
396 }
397 else
398 {
399 }
400 }
401 else
402 {
403 }
404
405 //u32DMD_DVBT2_DRAM_START_ADDR = _sDMD_DVBT2_InitData.u32DramStartAddr;
406 u32DMD_DVBT2_EQ_START_ADDR = _sDMD_DVBT2_InitData.u32EqStartAddr;
407 u32DMD_DVBT2_TDI_START_ADDR = _sDMD_DVBT2_InitData.u32TdiStartAddr;
408 u32DMD_DVBT2_DJB_START_ADDR = _sDMD_DVBT2_InitData.u32DjbStartAddr;
409 u32DMD_DVBT2_FW_START_ADDR = _sDMD_DVBT2_InitData.u32FwStartAddr;
410
411 if (bIFAGCTristateEnable)
412 {
413 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET_ALL_OFF);
414 }
415 else
416 {
417 MDrv_SYS_SetAGCPadMux(E_SYS_DTV_AGC_PAD_SET);
418 }
419
420 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_DSPRegInitExt != NULL)
421 {
422 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_DSPRegInitExt[0]>=1)
423 {
424 INTERN_DVBT2_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, _sDMD_DVBT2_InitData.u8DMD_DVBT2_DSPRegInitExt, _sDMD_DVBT2_InitData.u8DMD_DVBT2_DSPRegInitSize);
425 }
426 else
427 {
428 printf("u8DMD_DVBT2_DSPRegInitExt Error\n");
429 }
430 }
431 else
432 {
433 INTERN_DVBT2_Power_On_Initialization(bRFAGCTristateEnable, u8ADCIQMode, u8PadSel, bPGAEnable, u8PGAGain, NULL, 0);
434 }
435
436 INTERN_DVBT2_Version(&sDMD_DVBT2_Info.u16Version);
437 DMD_UNLOCK();
438 #ifdef MS_DEBUG
439 printf("firmware version: %x\n",sDMD_DVBT2_Info.u16Version);
440 #endif
441 return TRUE;
442 #endif
443 }
444
MDrv_DMD_DVBT2_Exit(void)445 MS_BOOL MDrv_DMD_DVBT2_Exit(void)
446 {
447 DVBT2_EXIT_PARAM Drv_DVBT2_EXIT_PARAM;
448 Drv_DVBT2_EXIT_PARAM.ret=false;
449
450 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_Exit\n"));
451
452 if(u32DVBT2open==1)
453 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_Exit, &Drv_DVBT2_EXIT_PARAM);
454 else
455 return false;
456
457 return Drv_DVBT2_EXIT_PARAM.ret;
458 #if 0
459 #ifdef MS_DEBUG
460 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
461 {
462 printf("MDrv_DMD_DVBT2_Exit\n");
463 }
464 #endif
465 DMD_LOCK();
466 INTERN_DVBT2_Exit();
467 DMD_UNLOCK();
468 MsOS_DeleteMutex(_s32DMD_DVBT2_Mutex);
469 _s32DMD_DVBT2_Mutex= -1;
470 return TRUE;
471 #endif
472 }
473
MDrv_DMD_DVBT2_SetDbgLevel(DMD_T2_DbgLv u8DbgLevel)474 MS_BOOL MDrv_DMD_DVBT2_SetDbgLevel(DMD_T2_DbgLv u8DbgLevel)
475 {
476 DVBT2_SETDBGLEVEL_PARAM Drv_DVBT2_SETDBG_LEVEL_PARAM;
477 Drv_DVBT2_SETDBG_LEVEL_PARAM.u8DbgLevel=u8DbgLevel;
478 Drv_DVBT2_SETDBG_LEVEL_PARAM.ret=false;
479
480 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT.c]MDrv_DMD_DVBT2_SetDbgLevel\n"));
481
482 if(u32DVBT2open==1)
483 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_SetDbgLevel, &Drv_DVBT2_SETDBG_LEVEL_PARAM);
484 else
485 return false;
486
487 return Drv_DVBT2_SETDBG_LEVEL_PARAM.ret;
488 #if 0
489 DMD_LOCK();
490 _u8DMDDbgLevel = u8DbgLevel;
491 DMD_UNLOCK();
492 return TRUE;
493 #endif
494 }
495
MDrv_DMD_DVBT2_GetInfo(DMD_DVBT2_INFO_TYPE eInfoType)496 DMD_DVBT2_Info* MDrv_DMD_DVBT2_GetInfo(DMD_DVBT2_INFO_TYPE eInfoType)
497 {
498 //MS_BOOL return_val;
499 DVBT2_GETINFO_PARAM Drv_DVBT2_GETINFO_PARAM;
500 Drv_DVBT2_GETINFO_PARAM.eInfoType=eInfoType;
501 Drv_DVBT2_GETINFO_PARAM.pInfo=NULL;
502
503 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetInfo\n"));
504
505 if(u32DVBT2open==1)
506 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetInfo, &Drv_DVBT2_GETINFO_PARAM);
507
508 return Drv_DVBT2_GETINFO_PARAM.pInfo;
509
510 #if 0
511 DMD_LOCK();
512 switch (eInfoType)
513 {
514 case E_DMD_DVBT2_MODULATION_INFO:
515 INTERN_DVBT2_Show_Modulation_info();
516 break;
517 case E_DMD_DVBT2_DEMOD_INFO:
518 INTERN_DVBT2_Show_Demod_Info();
519 break;
520 case E_DMD_DVBT2_LOCK_INFO:
521 INTERN_DVBT2_Show_Lock_Info();
522 break;
523 case E_DMD_DVBT2_PRESFO_INFO:
524 INTERN_DVBT2_Show_PRESFO_Info();
525 break;
526 case E_DMD_DVBT2_LOCK_TIME_INFO:
527 INTERN_DVBT2_Show_Lock_Time_Info();
528 break;
529 case E_DMD_DVBT2_BER_INFO:
530 INTERN_DVBT2_Show_BER_Info();
531 break;
532 case E_DMD_DVBT2_AGC_INFO:
533 INTERN_DVBT2_Show_AGC_Info();
534 break;
535 default:
536 #ifdef MS_DEBUG
537 printf("MDrv_DMD_DVBT2_GetInfo %d Error\n", eInfoType);
538 #endif
539 break;
540 }
541 DMD_UNLOCK();
542 return &sDMD_DVBT2_Info;
543 #endif
544 }
545
MDrv_DMD_DVBT2_GetLibVer(const MSIF_Version ** ppVersion)546 MS_BOOL MDrv_DMD_DVBT2_GetLibVer(const MSIF_Version **ppVersion)
547 {
548 DVBT2_GETLIBVER_PARAM Drv_DVBT2_GETLIBVER_PARAM;
549 Drv_DVBT2_GETLIBVER_PARAM.ppVersion=ppVersion;
550 Drv_DVBT2_GETLIBVER_PARAM.ret=false;
551
552 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetLibVer\n"));
553 if(u32DVBT2open==1)
554 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetLibVer, &Drv_DVBT2_GETLIBVER_PARAM);
555 else
556 return false;
557
558 return Drv_DVBT2_GETLIBVER_PARAM.ret;
559 #if 0
560 DMD_LOCK();
561 if (!ppVersion)
562 {
563 return FALSE;
564 }
565
566 *ppVersion = &_drv_dmd_dvbt2_intern_version;
567 DMD_UNLOCK();
568 return TRUE;
569 #endif
570 }
571
MDrv_DMD_DVBT2_GetFWVer(MS_U16 * ver)572 MS_BOOL MDrv_DMD_DVBT2_GetFWVer(MS_U16 *ver)
573 {
574 //MS_BOOL return_val;
575 DVBT2_GETFWVER_PARAM Drv_DVBT2_GETFWVER_PARAM;
576 Drv_DVBT2_GETFWVER_PARAM.ver=ver;
577 Drv_DVBT2_GETFWVER_PARAM.ret=false;
578
579 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2GetFWVer\n"));
580 if(u32DVBT2open==1)
581 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetFWVer, &Drv_DVBT2_GETFWVER_PARAM);
582 else
583 return false;
584
585 return Drv_DVBT2_GETFWVER_PARAM.ret;
586 #if 0
587 MS_BOOL bRet;
588
589 DMD_LOCK();
590
591 bRet = INTERN_DVBT2_Version(ver);
592 //printf("MDrv_DMD_DVBT2_GetFWVer %x\n",*ver);
593 DMD_UNLOCK();
594
595 return bRet;
596 #endif
597 }
598
MDrv_DMD_DVBT2_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)599 MS_BOOL MDrv_DMD_DVBT2_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
600 {
601 MS_BOOL bRet;
602
603 DVBT2_GETREG_PARAM Drv_DVBT2_GETREG_PARAM;
604 Drv_DVBT2_GETREG_PARAM.u16Addr=u16Addr;
605 Drv_DVBT2_GETREG_PARAM.pu8Data=pu8Data;
606
607 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetReg\n"));
608
609 bRet=UtopiaIoctl(ppDVBT2Instant,DMD_DVBT2_DRV_CMD_GetReg,&Drv_DVBT2_GETREG_PARAM);
610 return bRet;
611 #if 0
612 MS_BOOL bRet;
613
614 DMD_LOCK();
615 bRet=MDrv_SYS_DMD_VD_MBX_ReadReg(u16Addr, pu8Data);
616 DMD_UNLOCK();
617
618 #ifdef MS_DEBUG
619 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
620 {
621 printf("MDrv_DMD_DVBT2_GetReg %x %x\n", u16Addr, *pu8Data);
622 }
623 #endif
624
625 return bRet;
626 #endif
627 }
628
MDrv_DMD_DVBT2_SetReg(MS_U16 u16Addr,MS_U8 u8Data)629 MS_BOOL MDrv_DMD_DVBT2_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
630 {
631 MS_BOOL return_val;
632
633 DVBT2_SETREG_PARAM Drv_DVBT2_SETREG_PARAM;
634 Drv_DVBT2_SETREG_PARAM.u16Addr=u16Addr;
635 Drv_DVBT2_SETREG_PARAM.u8Data=u8Data;
636
637 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_SetReg\n"));
638 return_val=UtopiaIoctl(ppDVBT2Instant,DMD_DVBT2_DRV_CMD_SetReg,&Drv_DVBT2_SETREG_PARAM);
639 return return_val;
640 #if 0
641 MS_BOOL bRet;
642
643 #ifdef MS_DEBUG
644 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
645 {
646 printf("MDrv_DMD_DVBT2_SetReg %x %x\n", u16Addr, u8Data);
647 }
648 #endif
649
650 DMD_LOCK();
651 bRet=MDrv_SYS_DMD_VD_MBX_WriteReg(u16Addr, u8Data);
652 DMD_UNLOCK();
653 return bRet;
654 #endif
655 }
656
MDrv_DMD_DVBT2_SetSerialControl(MS_BOOL bEnable)657 MS_BOOL MDrv_DMD_DVBT2_SetSerialControl(MS_BOOL bEnable)
658 {
659 //MS_BOOL return_val;
660 DVBT2_SETSERIALCONTROL_PARAM Drv_DVBT2_SetSerialControl_PARAM;
661 Drv_DVBT2_SetSerialControl_PARAM.bEnable=bEnable;
662 Drv_DVBT2_SetSerialControl_PARAM.ret=false;
663
664 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_SetSerialControl\n"));
665
666 if(u32DVBT2open==1)
667 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_SetSerialControl, &Drv_DVBT2_SetSerialControl_PARAM);
668 else
669 return false;
670
671 return Drv_DVBT2_SetSerialControl_PARAM.ret;
672 #if 0
673 MS_BOOL bRet;
674 MS_U8 u8TSClk;
675
676 #ifdef MS_DEBUG
677 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
678 {
679 printf("MDrv_DMD_DVBT2_SetSerialControl %x\n", bEnable);
680 }
681 #endif
682
683 DMD_LOCK();
684 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt != NULL)
685 {
686 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[0]>=1)
687 {
688 u8TSClk = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[2]; // TS_CLK
689 }
690 else
691 {
692 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
693 }
694 }
695 else
696 {
697 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
698 }
699 bRet=INTERN_DVBT2_Serial_Control(bEnable, u8TSClk);
700 DMD_UNLOCK();
701 return bRet;
702 #endif
703 }
704
MDrv_DMD_DVBT2_SetReset(void)705 MS_BOOL MDrv_DMD_DVBT2_SetReset(void)
706 {
707 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_SetReset\n"));
708
709 if(u32DVBT2open==1)
710 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_SetReset, NULL);
711 else
712 return false;
713
714 return true;
715 #if 0
716 MS_BOOL bRet;
717
718 DMD_LOCK();
719 bRet = INTERN_DVBT2_SoftReset();
720 DMD_UNLOCK();
721
722 return bRet;
723 #endif
724 }
725
MDrv_DMD_DVBT2_SetConfig(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW,MS_BOOL bSerialTS,MS_U8 u8PlpID)726 MS_BOOL MDrv_DMD_DVBT2_SetConfig(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8PlpID)
727 {
728 //MS_BOOL return_val;
729 DVBT2_SETCONFIG_PARAM Drv_DVBT2_SetConfig_PARAM;
730 Drv_DVBT2_SetConfig_PARAM.BW=BW;
731 Drv_DVBT2_SetConfig_PARAM.bSerialTS=bSerialTS;
732 Drv_DVBT2_SetConfig_PARAM.u8PlpID=u8PlpID;
733 Drv_DVBT2_SetConfig_PARAM.ret=false;
734
735 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_SetConfig\n"));
736
737 if(u32DVBT2open==1)
738 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_SetConfig, &Drv_DVBT2_SetConfig_PARAM);
739 else
740 return false;
741
742 return Drv_DVBT2_SetConfig_PARAM.ret;
743 #if 0
744 //return MDrv_DMD_DVBT2_SetConfigHPLPSetIF(BW, bSerialTS, bPalBG, 0, u32DMD_DVBT2_IfFrequency, u32DMD_DVBT2_FsFrequency, u8DMD_DVBT2_IQSwap);
745 MS_BOOL bRet;
746 MS_U8 u8TSClk;
747
748 #ifdef MS_DEBUG
749 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
750 {
751 printf("MDrv_DMD_DVBT2_SetConfig %d %d %d\n", BW, bSerialTS, u8PlpID);
752 }
753 #endif
754
755 DMD_LOCK();
756 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt != NULL)
757 {
758 if (_sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[0]>=1)
759 {
760 u8TSClk = _sDMD_DVBT2_InitData.u8DMD_DVBT2_InitExt[2]; // TS_CLK
761 }
762 else
763 {
764 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
765 }
766 }
767 else
768 {
769 u8TSClk = 0xFF; // parallel mode: 0x0513 => ts_clk=288/(2*(0x16+1))=6.26MHz //@@++--
770 }
771
772 bRet=INTERN_DVBT2_Config(BW, bSerialTS, u8TSClk, u32DMD_DVBT2_IfFrequency, u8PlpID);
773 eDMD_DVBT2_BandWidth=BW;
774 DMD_UNLOCK();
775 return bRet;
776 #endif
777 }
778
MDrv_DMD_DVBT2_SetActive(MS_BOOL bEnable)779 MS_BOOL MDrv_DMD_DVBT2_SetActive(MS_BOOL bEnable)
780 {
781 //MS_BOOL return_val;
782 DVBT2_SETACTIVE_PARAM Drv_DVBT2_SetActive_PARAM;
783 Drv_DVBT2_SetActive_PARAM.bEnable=bEnable;
784 Drv_DVBT2_SetActive_PARAM.ret=false;
785
786 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_SetActive\n"));
787 if(u32DVBT2open==1)
788 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_SetActive, &Drv_DVBT2_SetActive_PARAM);
789 else
790 return false;
791
792 return Drv_DVBT2_SetActive_PARAM.ret;
793 #if 0
794 MS_BOOL bRet;
795
796 #ifdef MS_DEBUG
797 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
798 {
799 printf("MDrv_DMD_DVBT2_SetActive %d\n", bEnable);
800 }
801 #endif
802
803 DMD_LOCK();
804 bRet=INTERN_DVBT2_Active(bEnable);
805 DMD_UNLOCK();
806 return bRet;
807 #endif
808 }
809
MDrv_DMD_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eType,DMD_T2_LOCK_STATUS * eLockStatus)810 MS_BOOL MDrv_DMD_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eType, DMD_T2_LOCK_STATUS *eLockStatus)
811 {
812 //MS_BOOL return_val;
813 DVBT2_GETLOCK_PARAM Drv_DVBT2_GetLock_PARAM;
814 Drv_DVBT2_GetLock_PARAM.eType=eType;
815 Drv_DVBT2_GetLock_PARAM.eLockStatus=eLockStatus;
816 Drv_DVBT2_GetLock_PARAM.ret=false;
817 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetLock\n"));
818
819 if(u32DVBT2open==1)
820 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetLock, &Drv_DVBT2_GetLock_PARAM);
821 else
822 return false;
823
824 return Drv_DVBT2_GetLock_PARAM.ret;
825 #if 0
826 MS_BOOL bRet=TRUE;
827 DMD_LOCK();
828
829 if ( eType == E_DMD_DVBT2_GETLOCK ) // for channel scan
830 {
831 *eLockStatus = INTERN_DVBT2_Lock(u16DMD_DVBT2_P1_Timeout, u16DMD_DVBT2_FEC_Timeout);
832 }
833 else
834 {
835 if (INTERN_DVBT2_GetLock(eType) == TRUE)
836 {
837 *eLockStatus = E_DMD_T2_LOCK;
838 }
839 else
840 {
841 *eLockStatus = E_DMD_T2_UNLOCK;
842 }
843 }
844 DMD_UNLOCK();
845
846 #ifdef MS_DEBUG
847 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
848 {
849 printf("MDrv_DMD_DVBT2_GetLock %d\n", bRet);
850 }
851 #endif
852 return bRet;
853 #endif
854 }
855
856 // Floating computation/data. Need to move to upper layer to action for kerel mode.
857 #ifndef MSOS_TYPE_LINUX_KERNEL
MDrv_DMD_DVBT2_GetSignalStrength(MS_U16 * u16Strength)858 MS_BOOL MDrv_DMD_DVBT2_GetSignalStrength(MS_U16 *u16Strength)
859 {
860 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetSignalStrength\n"));
861
862 return MDrv_DMD_DVBT2_GetSignalStrengthWithRFPower(u16Strength, 200.0f);
863
864 #if 0
865 return MDrv_DMD_DVBT2_GetSignalStrengthWithRFPower(u16Strength, 200.0f);
866 #endif
867 }
868
869 #if 0
870 MS_BOOL MDrv_DMD_DVBT2_GetSignalStrengthWithRFPower(MS_U16 *u16Strength, float fRFPowerDbm)
871 {
872 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetSignalStrengthWithRFPower\n"));
873
874 #if(0)
875 DVBT2_GETSIGNALSTRENGTHWITHRFPOWER_PARAM Drv_DVBT2_GetSignalStrengthWithRFPower_PARAM;
876 Drv_DVBT2_GetSignalStrengthWithRFPower_PARAM.u16Strength=u16Strength;
877 Drv_DVBT2_GetSignalStrengthWithRFPower_PARAM.fRFPowerDbm=fRFPowerDbm;
878
879 if(u32DVBT2open==1)
880 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetSignalStrengthWithRFPower, &Drv_DVBT2_GetSignalStrengthWithRFPower_PARAM);
881 else
882 return false;
883
884 return Drv_DVBT2_GetSignalStrengthWithRFPower_PARAM.ret;
885 #else
886 *u16Strength=100;
887 return true;
888 #endif
889
890 #if 0
891 MS_U8 u8SarValue;
892 MS_BOOL bRet;
893
894 DMD_LOCK();
895 if (_sDMD_DVBT2_InitData.u8SarChannel != 0xFF)
896 {
897 u8SarValue=MDrv_SAR_Adc_GetValue(_sDMD_DVBT2_InitData.u8SarChannel);
898 }
899 else
900 {
901 u8SarValue=0xFF;
902 }
903 bRet=INTERN_DVBT2_GetSignalStrength(u16Strength, (const DMD_DVBT2_InitData *)(&_sDMD_DVBT2_InitData), u8SarValue, fRFPowerDbm);
904 DMD_UNLOCK();
905
906 #ifdef MS_DEBUG
907 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
908 {
909 printf("MDrv_DMD_DVBT2_GetSignalStrength %d\n", *u16Strength);
910 }
911 #endif
912 return bRet;
913 #endif
914 }
915 #else
MDrv_DMD_DVBT2_GetSignalStrengthWithRFPower(MS_U16 * u16Strength,float fRFPowerDbm)916 MS_BOOL MDrv_DMD_DVBT2_GetSignalStrengthWithRFPower(MS_U16 *u16Strength, float fRFPowerDbm)
917 {
918 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetSignalStrengthWithRFPower\n"));
919
920 MS_U8 status = true;
921 float ch_power_db = 0.0f;
922 float ch_power_ref = 11.0f;
923 float ch_power_rel = 0.0f;
924 //MS_U8 u8_index = 0;
925 MS_U16 L1_info_qam, L1_info_cr;
926 // MS_U8 demodState = 0;
927 DMD_T2_LOCK_STATUS eLockStatus;
928
929 if(u32DVBT2open==1)
930 {
931 MDrv_DMD_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK, &eLockStatus);
932 if (E_DMD_T2_LOCK != eLockStatus)
933 {
934 *u16Strength = 0;
935 return TRUE;
936 }
937
938 #if 0
939 // use pointer of IFAGC table to identify
940 // case 1: RFAGC from SAR, IFAGC controlled by demod
941 // case 2: RFAGC from tuner, ,IFAGC controlled by demod
942 status &= HAL_DMD_GetRFLevel(&ch_power_db, fRFPowerDbm, u8SarValue,
943 sDMD_DVBT2_InitData->pTuner_RfagcSsi, sDMD_DVBT2_InitData->u16Tuner_RfagcSsi_Size,
944 sDMD_DVBT2_InitData->pTuner_IfagcSsi_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_HiRef_Size,
945 sDMD_DVBT2_InitData->pTuner_IfagcSsi_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcSsi_LoRef_Size,
946 sDMD_DVBT2_InitData->pTuner_IfagcErr_HiRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_HiRef_Size,
947 sDMD_DVBT2_InitData->pTuner_IfagcErr_LoRef, sDMD_DVBT2_InitData->u16Tuner_IfagcErr_LoRef_Size);
948 #endif
949 ch_power_db = fRFPowerDbm; // get dBm from tuner now.
950
951 if(MDrv_DMD_DVBT2_GetL1Info(&L1_info_qam, T2_MODUL_MODE) == FALSE)
952 DMD_DBG(ULOGD("DEMOD","QAM parameter retrieve failure\n "));
953
954 if(MDrv_DMD_DVBT2_GetL1Info(&L1_info_cr, T2_CODE_RATE) == FALSE)
955 DMD_DBG(ULOGD("DEMOD","code rate parameter retrieve failure\n "));
956
957 /*
958 while(dvbt2_ssi_dbm_nordigp1[u8_index].constel != _UNKNOW_QAM)
959 {
960 if ( (dvbt2_ssi_dbm_nordigp1[u8_index].constel == (DMD_T2_CONSTEL)L1_info_qam)
961 && (dvbt2_ssi_dbm_nordigp1[u8_index].code_rate == (DMD_T2_CODERATE)L1_info_cr))
962 {
963 ch_power_ref = dvbt2_ssi_dbm_nordigp1[u8_index].p_ref;
964 break;
965 }
966 else
967 {
968 u8_index++;
969 }
970 }
971 */
972 ch_power_ref = dvbt2_ssi_dbm_nordigp1[(MS_U8)L1_info_qam][(MS_U8)L1_info_cr];
973
974 // status &= MDrv_SYS_DMD_VD_MBX_ReadReg(TOP_REG_BASE + (0x62*2), &demodState);
975
976 if (ch_power_ref > 10.0f)
977 *u16Strength = 0;
978 else
979 {
980 // For Nordig's SSI test items
981 if ( (L1_info_qam == 3) //256qam
982 && (L1_info_cr > 0 && L1_info_cr < 4) // CR 3/5,2/3,3/4
983 )
984 {
985 MS_U8 u8_x = L1_info_cr - 1;
986 float f_ssi = 0.0;
987
988 if(ch_power_db >= -45)f_ssi = 100;
989 else if (ch_power_db >= -50) f_ssi = fT2_SSI_formula[u8_x][0]*(ch_power_db + 50) + fT2_SSI_formula[u8_x][1];
990 else if (ch_power_db >= -60) f_ssi = fT2_SSI_formula[u8_x][2]*(ch_power_db + 60) + fT2_SSI_formula[u8_x][3];
991 else if (ch_power_db >= -70) f_ssi = fT2_SSI_formula[u8_x][4]*(ch_power_db + 70) + fT2_SSI_formula[u8_x][5];
992 else if (ch_power_db >= -80) f_ssi = fT2_SSI_formula[u8_x][6]*(ch_power_db + 80) + fT2_SSI_formula[u8_x][7];
993 else if (ch_power_db >= -95) f_ssi = fT2_SSI_formula[u8_x][8]*(ch_power_db + 95) + fT2_SSI_formula[u8_x][9];
994 else if (ch_power_db >= -100) f_ssi = fT2_SSI_formula[u8_x][10]*(ch_power_db + 100) + fT2_SSI_formula[u8_x][11];
995
996 if (f_ssi > 100) *u16Strength = 100;
997 else if (f_ssi < 0) *u16Strength = 0;
998 else *u16Strength = (MS_U16)(f_ssi+0.5);
999
1000 DMD_DBG(ULOGD("DEMOD"," SSI... RF_level=%d, f_ssi=%d, ssi=%d, cr=%d, mod=%d\n", (MS_S16)ch_power_db, (MS_S16)f_ssi, (MS_S16)(*u16Strength), L1_info_cr, L1_info_qam));
1001 }
1002 else
1003 {
1004 ch_power_rel = ch_power_db - ch_power_ref;
1005 /*
1006 if (demodState != 0x09)
1007 {
1008 ch_power_rel = ch_power_db - (-50.0f);
1009 }
1010 else
1011 {
1012 ch_power_rel = ch_power_db - ch_power_ref;
1013 }
1014 */
1015 if ( ch_power_rel < -15.0f )
1016 {
1017 *u16Strength = 0;
1018 }
1019 else if ( ch_power_rel < 0.0f )
1020 {
1021 *u16Strength = (MS_U16)(2.0f/3*(ch_power_rel + 15.0f));
1022 }
1023 else if ( ch_power_rel < 20 )
1024 {
1025 *u16Strength = (MS_U16)(4.0f*ch_power_rel + 10.0f);
1026 }
1027 else if ( ch_power_rel < 35.0f )
1028 {
1029 *u16Strength = (MS_U16)(2.0f/3*(ch_power_rel - 20.0f) + 90.0f);
1030 }
1031 else
1032 {
1033 *u16Strength = 100;
1034 }
1035 }
1036 }
1037
1038 DMD_DBG(ULOGD("DEMOD","ch_power_ref(dB) = %d , ch_power_db(dB) = %d, ch_power_rel(dB) = %d\n", (MS_S16)ch_power_ref, (MS_S16)ch_power_db, (MS_S16)ch_power_rel));
1039 DMD_DBG(ULOGD("DEMOD","SSI_CH_PWR(dB) = %d , Score = %d\n", (MS_S16)ch_power_db, *u16Strength));
1040 DMD_DBG(ULOGD("DEMOD","SSI = %d \n", *u16Strength));
1041 }
1042 return status;
1043 }
1044 #endif
1045
MDrv_DMD_DVBT2_GetSignalQuality(MS_U16 * u16Quality)1046 MS_BOOL MDrv_DMD_DVBT2_GetSignalQuality(MS_U16 *u16Quality)
1047 {
1048 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetSignalQuality\n"));
1049
1050 return MDrv_DMD_DVBT2_GetSignalQualityWithRFPower(u16Quality, 200.0f);
1051 #if 0
1052 return MDrv_DMD_DVBT2_GetSignalQualityWithRFPower(u16Quality, 200.0f);
1053 #endif
1054 }
1055
1056 #if 1
1057 /****************************************************************************
1058 Subject: To get the DVT Signal quility
1059 Function: INTERN_DVBT2_GetSignalQuality
1060 Parmeter: Quility
1061 Return: E_RESULT_SUCCESS
1062 E_RESULT_FAILURE
1063 Remark: Here we have 4 level range
1064 <1>.First Range => Quility =100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_100)
1065 <2>.2th Range => 60 < Quality < 100 (You can define it by INTERN_DVBT2_SIGNAL_BASE_60)
1066 <3>.3th Range => 10 < Quality < 60 (You can define it by INTERN_DVBT2_SIGNAL_BASE_10)
1067 <4>.4th Range => Quality <10
1068 *****************************************************************************/
MDrv_DMD_DVBT2_GetSignalQualityWithRFPower(MS_U16 * u16Quality,float fRFPowerDbm)1069 MS_BOOL MDrv_DMD_DVBT2_GetSignalQualityWithRFPower(MS_U16 *u16Quality, float fRFPowerDbm)
1070 //MS_BOOL INTERN_DVBT2_GetSignalQuality(MS_U16 *quality, const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm)
1071 {
1072 // float ber_sqi, SQI;
1073 float fber = 0;
1074 float cn_rec = 0;
1075 float cn_ref = 0;
1076 float cn_rel = 0;
1077 float fBerTH1[] = {1E-4, 1E-4*(1.0-DVBT2_BER_TH_HY), 1E-4*(1.0+DVBT2_BER_TH_HY), 1E-4};
1078 float fBerTH2[] = {3E-7, 3E-7, 3E-7*(1.0-DVBT2_BER_TH_HY), 3E-7*(1.0+DVBT2_BER_TH_HY)};
1079 float BER_SQI = (float)0.0;
1080 float SQI = (float)0.0;
1081 static MS_U8 u8SQIState = 0;
1082 DMD_T2_LOCK_STATUS eLockStatus;
1083
1084 MS_U8 status = true;
1085 MS_U16 L1_info_qam = 0, L1_info_cr = 0;
1086
1087 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetSignalQualityWithRFPower\n"));
1088
1089 if(u32DVBT2open==1)
1090 {
1091 MDrv_DMD_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK, &eLockStatus);
1092 if (E_DMD_T2_LOCK == eLockStatus)
1093 {
1094 #if 1 // copy from msb1240
1095 if (fBerFilteredDVBT2 < 0.0)
1096 {
1097 if (MDrv_DMD_DVBT2_GetPostLdpcBer(&fber) == FALSE)
1098 {
1099 DMD_DBG(ULOGD("DEMOD","INTERN_DVBT2 PostLDPCBER error \n "));
1100 return FALSE;
1101 }
1102 fBerFilteredDVBT2 = fber;
1103 }
1104 else
1105 {
1106 fber = fBerFilteredDVBT2;
1107 }
1108
1109 if (fber > fBerTH1[u8SQIState])
1110 {
1111 BER_SQI = 0.0;
1112 u8SQIState = 1;
1113 }
1114 else if (fber >=fBerTH2[u8SQIState])
1115 {
1116 BER_SQI = 100.0/15;
1117 u8SQIState = 2;
1118 }
1119 else
1120 {
1121 BER_SQI = 100.0/6;
1122 u8SQIState = 3;
1123 }
1124
1125 MDrv_DMD_DVBT2_GetSNR(&cn_rec);
1126
1127 if (cn_rec < 0.0)
1128 return FALSE;
1129
1130 ///////// Get Constellation and Code Rate to determine Ref. C/N //////////
1131 ///////// (refer to Teracom min. spec 2.0 4.1.1.7) /////
1132 cn_ref = (float)-1.0;
1133
1134 if(MDrv_DMD_DVBT2_GetL1Info(&L1_info_qam, T2_MODUL_MODE) == FALSE)
1135 DMD_DBG(ULOGD("DEMOD","QAM parameter retrieve failure\n "));
1136
1137 if(MDrv_DMD_DVBT2_GetL1Info(&L1_info_cr, T2_CODE_RATE) == FALSE)
1138 DMD_DBG(ULOGD("DEMOD","code rate parameter retrieve failure\n "));
1139
1140 // YP:Need to use init data. Tmp remove
1141 #if 0
1142 for(i = 0; i < sDMD_DVBT2_InitData->u16SqiCnNordigP1_Size; i++)
1143 {
1144 if ( (L1_info_qam == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].constel)
1145 && (L1_info_cr == sDMD_DVBT2_InitData->pSqiCnNordigP1[i].code_rate) )
1146 {
1147 cn_ref = sDMD_DVBT2_InitData->pSqiCnNordigP1[i].cn_ref;
1148 break;
1149 }
1150 }
1151 #endif
1152
1153 // arthur
1154 cn_ref = dvbt2_sqi_db_nordigp1[(MS_U8)L1_info_qam][(MS_U8)L1_info_cr];
1155
1156 if (cn_ref < 0.0)
1157 {
1158 SQI = (float)0.0;
1159 DMD_DBG(ULOGD("DEMOD","SQI is zero, 1\n"));
1160 }
1161 else
1162 {
1163 // 0.7, snr offset
1164 cn_rel = cn_rec - cn_ref + 0.7f;
1165 if (cn_rel > 3.0)
1166 SQI = 100;
1167 else if (cn_rel >= -3)
1168 {
1169 SQI = (cn_rel+3)*BER_SQI;
1170 if (SQI > 100.0) SQI = 100.0;
1171 else if (SQI < 0.0) SQI = 0.0;
1172 }
1173 else
1174 {
1175 SQI = (float)0.0;
1176 DMD_DBG(ULOGD("DEMOD","SQI is zero, 2\n"));
1177 }
1178 }
1179
1180 *u16Quality = (MS_U16)SQI;
1181 }
1182 else
1183 {
1184 *u16Quality = 0;
1185 }
1186
1187 DMD_DBG(ULOGD("DEMOD","SNR = %f, QAM = %d, code Rate = %d\n", cn_rec, L1_info_qam, L1_info_cr));
1188 DMD_DBG(ULOGD("DEMOD","BER = %8.3e\n", fber));
1189 DMD_DBG(ULOGD("DEMOD","Signal Quility = %d\n", *u16Quality));
1190 }
1191 return status;
1192 }
1193
1194 #else
1195 MS_BOOL MDrv_DMD_DVBT2_GetSignalQualityWithRFPower(MS_U16 *u16Quality, float fRFPowerDbm)
1196 {
1197 //MS_BOOL return_val;
1198 DVBT2_GETSIGNALQUALITYWITHRFPOWER_PARAM Drv_DVBT2_GetSignalQualityWithRFPower_PARAM;
1199 Drv_DVBT2_GetSignalQualityWithRFPower_PARAM.u16Quality=u16Quality;
1200 Drv_DVBT2_GetSignalQualityWithRFPower_PARAM.fRFPowerDbm=fRFPowerDbm;
1201
1202 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetSignalQualityWithRFPower\n"));
1203 /*bryan temp mark */
1204 #if(0)
1205 if(u32DVBT2open==1)
1206 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetSignalQualityWithRFPower, &Drv_DVBT2_GetSignalQualityWithRFPower_PARAM);
1207 else
1208 return false;
1209 #else
1210 Drv_DVBT2_GetSignalQualityWithRFPower_PARAM.ret=true;
1211 #endif
1212
1213 return Drv_DVBT2_GetSignalQualityWithRFPower_PARAM.ret;
1214
1215 #if 0
1216 MS_U8 u8SarValue=0;
1217 MS_BOOL bRet=0;
1218
1219 DMD_LOCK();
1220 if (_sDMD_DVBT2_InitData.u8SarChannel != 0xFF)
1221 {
1222 u8SarValue=MDrv_SAR_Adc_GetValue(_sDMD_DVBT2_InitData.u8SarChannel);
1223 }
1224 else
1225 {
1226 u8SarValue=0xFF;
1227 }
1228 bRet=INTERN_DVBT2_GetSignalQuality(u16Quality, (const DMD_DVBT2_InitData *)(&_sDMD_DVBT2_InitData), u8SarValue, fRFPowerDbm);
1229 DMD_UNLOCK();
1230
1231 #ifdef MS_DEBUG
1232 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
1233 {
1234 printf("MDrv_DMD_DVBT2_GetSignalQuality %d\n", *u16Quality);
1235 }
1236 #endif
1237 return bRet;
1238 #endif
1239 }
1240 #endif
1241
MDrv_DMD_DVBT2_GetSNR(float * fSNR)1242 MS_BOOL MDrv_DMD_DVBT2_GetSNR(float *fSNR)
1243 {
1244 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetSNR\n"));
1245
1246 #if(1)
1247 MS_U16 u16_snr100;
1248 MS_U8 snr_cali;
1249 MS_U8 u8_gi;
1250
1251 DVBT2_GETSNR_PARAM Drv_DVBT2_GetSNR_PARAM;
1252 Drv_DVBT2_GetSNR_PARAM.u16_snr100 = &u16_snr100;
1253 Drv_DVBT2_GetSNR_PARAM.snr_cali = &snr_cali;
1254 Drv_DVBT2_GetSNR_PARAM.u8_gi = &u8_gi;
1255 Drv_DVBT2_GetSNR_PARAM.ret = false;
1256
1257 if(u32DVBT2open==1)
1258 {
1259 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetSNR, &Drv_DVBT2_GetSNR_PARAM);
1260
1261 *fSNR = (float)u16_snr100/100.0;
1262
1263 if (snr_cali == 1)
1264 {
1265 float snr_offset = 0.0;
1266 float snr_cali = 0.0;
1267
1268 if (u8_gi == 0) snr_offset = 0.157;
1269 else if(u8_gi == 1) snr_offset = 0.317;
1270 else if(u8_gi == 2) snr_offset = 0.645;
1271 else if(u8_gi == 3) snr_offset = 1.335;
1272 else if(u8_gi == 4) snr_offset = 0.039;
1273 else if(u8_gi == 5) snr_offset = 0.771;
1274 else if(u8_gi == 6) snr_offset = 0.378;
1275
1276 snr_cali = *fSNR - snr_offset;
1277 if (snr_cali > 0.0) *fSNR = snr_cali;
1278 }
1279 //use Polynomial curve fitting to fix snr
1280 //snr_poly = 0.0027945*pow(*fSNR,3) - 0.2266*pow(*fSNR,2) + 6.0101*(*fSNR) - 53.3621;
1281 //f_snr = f_snr + snr_poly;
1282
1283 #endif
1284 }
1285 else
1286 return false;
1287
1288 return Drv_DVBT2_GetSNR_PARAM.ret;
1289 #else
1290 //Drv_DVBT_GetSNR_PARAM.ret=true;
1291 *fSNR=30;
1292 return true;
1293 #endif
1294
1295 #if 0
1296 DMD_LOCK();
1297 *fSNR=INTERN_DVBT2_GetSNR();
1298 DMD_UNLOCK();
1299
1300 return TRUE;
1301 #endif
1302 }
1303
MDrv_DMD_DVBT2_GetPostLdpcBer(float * ber)1304 MS_BOOL MDrv_DMD_DVBT2_GetPostLdpcBer(float *ber)
1305 {
1306 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetPostLdpcBer\n"));
1307
1308 #if(1)
1309 MS_U16 BitErrPeriod_reg;
1310 MS_U32 BitErr_reg;
1311 MS_U16 FecType;
1312
1313 DVBT2_GETPOSTLDPCBER_PARAM Drv_DVBT2_GetPostLdpcBer_PARAM;
1314 Drv_DVBT2_GetPostLdpcBer_PARAM.BitErr_reg = &BitErr_reg;
1315 Drv_DVBT2_GetPostLdpcBer_PARAM.BitErrPeriod_reg = &BitErrPeriod_reg;
1316 Drv_DVBT2_GetPostLdpcBer_PARAM.FecType = &FecType;
1317 Drv_DVBT2_GetPostLdpcBer_PARAM.ret=false;
1318
1319 if(u32DVBT2open==1)
1320 {
1321 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetPostLdpcBer, &Drv_DVBT2_GetPostLdpcBer_PARAM);
1322
1323 if (BitErrPeriod_reg == 0)
1324 //protect 0
1325 BitErrPeriod_reg = 1;
1326
1327 if (FecType & 0x0180)
1328 {
1329 if (BitErr_reg == 0)
1330 *ber = (float)0.5 / (float)(BitErrPeriod_reg * 64800);
1331 else
1332 *ber = (float)BitErr_reg / (float)(BitErrPeriod_reg * 64800);
1333 }
1334 else
1335 {
1336 if (BitErr_reg == 0)
1337 *ber = (float)0.5 / (float)(BitErrPeriod_reg * 16200);
1338 else
1339 *ber = (float)BitErr_reg / (float)(BitErrPeriod_reg * 16200);
1340 }
1341 DMD_DBG(ULOGD("DEMOD","INTERN_DVBT2 PostLDPCBER = %8.3e \n ", *ber));
1342 }
1343 else
1344 return false;
1345
1346 return Drv_DVBT2_GetPostLdpcBer_PARAM.ret;
1347 #else
1348 //Pre_DVBT_GetPostViterbiBer_PARAM.ret=true;
1349 *ber=0;
1350 return true;
1351 #endif
1352
1353 #if 0
1354 MS_BOOL bRet;
1355
1356 DMD_LOCK();
1357 bRet=INTERN_DVBT2_GetPostLdpcBer(ber);
1358 DMD_UNLOCK();
1359
1360 return bRet;
1361 #endif
1362 }
1363
MDrv_DMD_DVBT2_GetPreLdpcBer(float * ber)1364 MS_BOOL MDrv_DMD_DVBT2_GetPreLdpcBer(float *ber)
1365 {
1366 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetPreLdpcBer\n"));
1367
1368 #if(1)
1369 MS_U16 BitErrPeriod_reg;
1370 MS_U32 BitErr_reg;
1371 MS_U16 FecType;
1372
1373 DVBT2_GETPRELDPCBERPARAM Drv_DVBT2_GetPreLdpcBer_PARAM;
1374 Drv_DVBT2_GetPreLdpcBer_PARAM.BitErr_reg = &BitErr_reg;
1375 Drv_DVBT2_GetPreLdpcBer_PARAM.BitErrPeriod_reg = &BitErrPeriod_reg;
1376 Drv_DVBT2_GetPreLdpcBer_PARAM.FecType = &FecType;
1377 Drv_DVBT2_GetPreLdpcBer_PARAM.ret=false;
1378
1379 if(u32DVBT2open==1)
1380 {
1381 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetPreLdpcBer, &Drv_DVBT2_GetPreLdpcBer_PARAM);
1382
1383 if (BitErrPeriod_reg == 0)
1384 //protect 0
1385 BitErrPeriod_reg = 1;
1386
1387 if (FecType & 0x0180)
1388 {
1389 if (BitErr_reg == 0)
1390 *ber = (float)0.5 / (float)(BitErrPeriod_reg * 64800);
1391 else
1392 *ber = (float)BitErr_reg / (float)(BitErrPeriod_reg * 64800);
1393 }
1394 else
1395 {
1396 if (BitErr_reg == 0)
1397 *ber = (float)0.5 / (float)(BitErrPeriod_reg * 16200);
1398 else
1399 *ber = (float)BitErr_reg / (float)(BitErrPeriod_reg * 16200);
1400 }
1401 DMD_DBG(ULOGD("DEMOD","INTERN_DVBT2 PreLDPCBER = %8.3e \n ", *ber));
1402 }
1403 else
1404 return false;
1405
1406 return Drv_DVBT2_GetPreLdpcBer_PARAM.ret;
1407 #else
1408 //Pre_DVBT_GetPostViterbiBer_PARAM.ret=true;
1409 *ber=0;
1410 return true;
1411 #endif
1412
1413 #if 0
1414 MS_BOOL bRet;
1415
1416 DMD_LOCK();
1417 bRet=INTERN_DVBT2_GetPreLdpcBer(ber);
1418 DMD_UNLOCK();
1419
1420 return bRet;
1421 #endif
1422 }
1423
MDrv_DMD_DVBT2_GetFreqOffset(float * pFreqOff)1424 MS_BOOL MDrv_DMD_DVBT2_GetFreqOffset(float *pFreqOff)
1425 {
1426 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetFreqOffset\n"));
1427 #if(1)
1428 MS_U32 CfoTd_reg;
1429 MS_U32 CfoFd_reg;
1430 MS_U32 Icfo_reg;
1431 MS_U8 fft_reg;
1432
1433 DVBT2_GETFREQOFFSET_PARAM Drv_DVBT2_GetFreqOffset_PARAM;
1434 Drv_DVBT2_GetFreqOffset_PARAM.CfoTd_reg = &CfoTd_reg;
1435 Drv_DVBT2_GetFreqOffset_PARAM.CfoFd_reg = &CfoFd_reg;
1436 Drv_DVBT2_GetFreqOffset_PARAM.Icfo_reg = &Icfo_reg;
1437 Drv_DVBT2_GetFreqOffset_PARAM.fft_reg = &fft_reg;
1438 Drv_DVBT2_GetFreqOffset_PARAM.ret = false;
1439
1440 if(u32DVBT2open==1)
1441 {
1442 float N = 0.0, FreqB = 0.0;
1443 float FreqCfoTd = 0.0, FreqCfoFd = 0.0, FreqIcfo = 0.0;
1444 MS_U8 u8BW = 8;
1445
1446 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetFreqOffset, &Drv_DVBT2_GetFreqOffset_PARAM);
1447
1448 FreqB = (float)u8BW * 8 / 7;
1449
1450 FreqCfoTd = (float)CfoTd_reg;
1451
1452 if (CfoTd_reg & 0x800000)
1453 FreqCfoTd = FreqCfoTd - (float)0x1000000;
1454
1455 FreqCfoTd = FreqCfoTd * FreqB * 0.00011642;
1456
1457 FreqCfoFd = (float)CfoFd_reg;
1458
1459 if (CfoFd_reg & 0x800000)
1460 FreqCfoFd = FreqCfoFd - (float)0x1000000;
1461
1462 FreqCfoFd = FreqCfoFd * FreqB * 0.00011642;
1463
1464 FreqIcfo = (float)Icfo_reg;
1465
1466 if (Icfo_reg & 0x400)
1467 FreqIcfo = FreqIcfo - (float)0x800;
1468
1469 switch (fft_reg)
1470 {
1471 case 0x00: N = 2048; break;
1472 case 0x20: N = 4096; break;
1473 case 0x10:
1474 default: N = 8192; break;
1475 }
1476
1477 FreqIcfo = FreqIcfo * FreqB / N * 1000; //unit: kHz
1478
1479
1480 //*pFreqOff = FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000;
1481 *pFreqOff = (-1.0f)*(FreqIcfo + (FreqCfoFd + FreqCfoTd)/1000);
1482 // DBG_GET_SIGNAL(printf("FCFO = %f\n", FreqCfoFd));
1483 // DBG_GET_SIGNAL(printf("TCFO = %f\n", FreqCfoTd));
1484 // DBG_GET_SIGNAL(printf("ICFO = %f\n", FreqIcfo));
1485 DMD_DBG(ULOGD("DEMOD","INTERN_DVBT2 FreqOffset = %8.3e \n ", *pFreqOff));
1486 }
1487
1488 return Drv_DVBT2_GetFreqOffset_PARAM.ret;
1489 #if 0
1490 #if(0)
1491 DVBT2_GETFREQOFFSET_PARAM Drv_DVBT2_GetFreqOffset_PARAM;
1492 Drv_DVBT2_GetFreqOffset_PARAM.pFreqOff=pFreqOff;
1493 if(u32DVBT2open==1)
1494 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetFreqOffset, &Drv_DVBT2_GetFreqOffset_PARAM);
1495 else
1496 return false;
1497
1498 return Drv_DVBT2_GetFreqOffset_PARAM.ret;
1499 #else
1500 //Drv_DVBT_GetFreqOffset_PARAM.ret=true;
1501 *pFreqOff = 0;
1502 return true;
1503 #endif
1504 #endif
1505 }
1506 #endif
1507
MDrv_DMD_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel,DMD_T2_CODERATE code_rate,float write_value)1508 MS_BOOL MDrv_DMD_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value)
1509 {
1510 // MS_BOOL return_val;
1511 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_NORDIG_SSI_Table_Write\n"));
1512
1513 dvbt2_ssi_dbm_nordigp1[constel][code_rate] = write_value;
1514 return TRUE;
1515
1516 #if 0
1517 #if(0)
1518 DVBT2_NORDIG_SSI_TABLE_WRITE_PARAM Drv_DVBT2_NORDIGSSITableWrite_PARAM;
1519 Drv_DVBT2_NORDIGSSITableWrite_PARAM.constel=constel;
1520 Drv_DVBT2_NORDIGSSITableWrite_PARAM.code_rate=code_rate;
1521 Drv_DVBT2_NORDIGSSITableWrite_PARAM.write_value=write_value;
1522
1523 if(u32DVBT2open==1)
1524 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_NORDIG_SSI_Table_Write, &Drv_DVBT2_NORDIGSSITableWrite_PARAM);
1525 else
1526 return false;
1527
1528 return Drv_DVBT2_NORDIGSSITableWrite_PARAM.ret;
1529 #else
1530 // Drv_DVBT_NORDIGSSITableWrite_PARAM.ret=true;
1531 return true;
1532 #endif
1533 #endif
1534 }
1535
MDrv_DMD_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel,DMD_T2_CODERATE code_rate,float * read_value)1536 MS_BOOL MDrv_DMD_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value)
1537 {
1538 // MS_BOOL return_val;
1539 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_NORDIG_SSI_Table_Read\n"));
1540
1541 *read_value = dvbt2_ssi_dbm_nordigp1[constel][code_rate];
1542 return TRUE;
1543 #if 0
1544 #if(0)
1545 DVBT2_NORDIG_SSI_TABLE_READ_PARAM Drv_DVBT2_NORDIGSSITableRead_PARAM;
1546 Drv_DVBT2_NORDIGSSITableRead_PARAM.constel=constel;
1547 Drv_DVBT2_NORDIGSSITableRead_PARAM.code_rate=code_rate;
1548 Drv_DVBT2_NORDIGSSITableRead_PARAM.read_value=read_value;
1549
1550 if(u32DVBT2open==1)
1551 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_NORDIG_SSI_Table_Read, &Drv_DVBT2_NORDIGSSITableRead_PARAM);
1552 else
1553 return false;
1554
1555 return Drv_DVBT2_NORDIGSSITableRead_PARAM.ret;
1556 #else
1557 // Drv_DVBT_NORDIGSSITableWrite_PARAM.ret=true;
1558 return true;
1559 #endif
1560 #endif
1561 }
1562
1563 #endif
1564
MDrv_DMD_DVBT2_GetPacketErr(MS_U16 * pktErr)1565 MS_BOOL MDrv_DMD_DVBT2_GetPacketErr(MS_U16 *pktErr)
1566 {
1567 // MS_BOOL return_val;
1568 DVBT2_GETPACKETERRPARAM Drv_DVBT2_GetPacketErr_PARAM;
1569 Drv_DVBT2_GetPacketErr_PARAM.pktErr=pktErr;
1570 Drv_DVBT2_GetPacketErr_PARAM.ret=false;
1571
1572 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetPacketErr\n"));
1573 if(u32DVBT2open==1)
1574 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetPacketErr, &Drv_DVBT2_GetPacketErr_PARAM);
1575 else
1576 return false;
1577
1578 return Drv_DVBT2_GetPacketErr_PARAM.ret;
1579
1580 #if 0
1581 MS_BOOL bRet;
1582 float fBER;
1583
1584 DMD_LOCK();
1585 INTERN_DVBT2_GetPostLdpcBer(&fBER);
1586 bRet=INTERN_DVBT2_GetPacketErr(pktErr);
1587 if ((*pktErr ==1) && (fBER<= 0.000001)) // for no signal case, from Oga
1588 {
1589 *pktErr = 0x3FF;
1590 }
1591 #ifdef MS_DEBUG
1592 if (_u8DMDDbgLevel >= DMD_T2_DBGLV_DEBUG)
1593 {
1594 printf("MDrv_DMD_DVBT2_GetPacketErr %d\n", *pktErr);
1595 }
1596 #endif
1597 DMD_UNLOCK();
1598
1599 return bRet;
1600 #endif
1601 }
1602
MDrv_DMD_DVBT2_GetL1Info(MS_U16 * u16Info,DMD_DVBT2_SIGNAL_INFO eSignalType)1603 MS_BOOL MDrv_DMD_DVBT2_GetL1Info(MS_U16 *u16Info, DMD_DVBT2_SIGNAL_INFO eSignalType)
1604 {
1605 DVBT2_GETL1INFO_PARAM Drv_DVBT2_GetL1Info_PARAM;
1606 Drv_DVBT2_GetL1Info_PARAM.u16Info=u16Info;
1607 Drv_DVBT2_GetL1Info_PARAM.eSignalType=eSignalType;
1608 Drv_DVBT2_GetL1Info_PARAM.ret=false;
1609
1610 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetL1Info\n"));
1611 if(u32DVBT2open==1)
1612 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetL1Info, &Drv_DVBT2_GetL1Info_PARAM);
1613 else
1614 return false;
1615
1616 return Drv_DVBT2_GetL1Info_PARAM.ret;
1617
1618 #if 0
1619 MS_BOOL bRet;
1620
1621 DMD_LOCK();
1622 bRet=INTERN_DVBT2_Get_L1_Parameter(u16Info, eSignalType );
1623 DMD_UNLOCK();
1624
1625 return bRet;
1626 #endif
1627 }
1628
MDrv_DMD_DVBT2_SetPowerState(EN_POWER_MODE u16PowerState)1629 MS_U32 MDrv_DMD_DVBT2_SetPowerState(EN_POWER_MODE u16PowerState)
1630 {
1631 // MS_BOOL return_val;
1632 DVBT2_SETPOWERSTATE_PARAM Drv_DVBT2_SetPowerState_PARAM;
1633 Drv_DVBT2_SetPowerState_PARAM.u16PowerState=u16PowerState;
1634 Drv_DVBT2_SetPowerState_PARAM.ret=false;
1635
1636 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_SetPowerState\n"));
1637 if(u32DVBT2open==1)
1638 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_SetPowerState, &Drv_DVBT2_SetPowerState_PARAM);
1639 else
1640 return false;
1641
1642 return Drv_DVBT2_SetPowerState_PARAM.ret;
1643
1644 #if 0
1645 static EN_POWER_MODE _prev_u16PowerState = E_POWER_MECHANICAL;
1646 MS_U32 u32Return = UTOPIA_STATUS_FAIL;
1647 u32Return = u32Return;
1648 if (u16PowerState == E_POWER_SUSPEND)
1649 {
1650 MDrv_DMD_DVBT2_Exit();
1651 _prev_u16PowerState = u16PowerState;
1652 u32Return = UTOPIA_STATUS_SUCCESS;//SUSPEND_OK;
1653 }
1654 else if (u16PowerState == E_POWER_RESUME)
1655 {
1656 if (_prev_u16PowerState == E_POWER_SUSPEND)
1657 {
1658 MDrv_DMD_DVBT2_Init(&_sDMD_DVBT2_InitData, sizeof(_sDMD_DVBT2_InitData));
1659 _prev_u16PowerState = u16PowerState;
1660 u32Return = UTOPIA_STATUS_SUCCESS;//RESUME_OK;
1661 }
1662 else
1663 {
1664 printf("[%s,%5d]It is not suspended yet. We shouldn't resume\n",__FUNCTION__,__LINE__);
1665 u32Return = UTOPIA_STATUS_FAIL;//SUSPEND_FAILED;
1666 }
1667 }
1668 else
1669 {
1670 printf("[%s,%5d]Do Nothing: %d\n",__FUNCTION__,__LINE__,u16PowerState);
1671 u32Return = FALSE;
1672 }
1673 return UTOPIA_STATUS_SUCCESS;
1674 #endif
1675 }
1676
MDrv_DMD_DVBT2_GetPlpBitMap(MS_U8 * u8PlpBitMap)1677 MS_BOOL MDrv_DMD_DVBT2_GetPlpBitMap(MS_U8* u8PlpBitMap)
1678 {
1679 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetPlpBitMap\n"));
1680
1681 DVBT2_GETPLPBITMAP_PARAM Drv_DVBT2_GetPlpBitMap_PARAM;
1682 Drv_DVBT2_GetPlpBitMap_PARAM.u8PlpBitMap=u8PlpBitMap;
1683 Drv_DVBT2_GetPlpBitMap_PARAM.ret=false;
1684
1685 if(u32DVBT2open==1)
1686 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetPlpBitMap, &Drv_DVBT2_GetPlpBitMap_PARAM);
1687 else
1688 return false;
1689
1690 return Drv_DVBT2_GetPlpBitMap_PARAM.ret;
1691
1692 #if 0
1693 return INTERN_DVBT2_GetPlpBitMap(u8PlpBitMap);
1694 #endif
1695 }
1696
MDrv_DMD_DVBT2_GetPlpGroupID(MS_U8 u8PlpID,MS_U8 * u8GroupID)1697 MS_BOOL MDrv_DMD_DVBT2_GetPlpGroupID(MS_U8 u8PlpID, MS_U8* u8GroupID)
1698 {
1699 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_GetPlpGroupID\n"));
1700
1701 DVBT2_GETPLPGROUPID_PARAM Drv_DVBT2_GetPlpGroupID_PARAM;
1702 Drv_DVBT2_GetPlpGroupID_PARAM.u8PlpID=u8PlpID;
1703 Drv_DVBT2_GetPlpGroupID_PARAM.u8GroupID=u8GroupID;
1704 Drv_DVBT2_GetPlpGroupID_PARAM.ret=false;
1705
1706 if(u32DVBT2open==1)
1707 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_GetPlpGroupID, &Drv_DVBT2_GetPlpGroupID_PARAM);
1708 else
1709 return false;
1710
1711 return Drv_DVBT2_GetPlpGroupID_PARAM.ret;
1712
1713 #if 0
1714 return INTERN_DVBT2_GetPlpGroupID(u8PlpID, u8GroupID);
1715 #endif
1716 }
1717
MDrv_DMD_DVBT2_SetPlpID(MS_U8 u8PlpID,MS_U8 u8GroupID)1718 MS_BOOL MDrv_DMD_DVBT2_SetPlpID(MS_U8 u8PlpID, MS_U8 u8GroupID)
1719 {
1720 DMD_DBG(ULOGD("DEMOD","[drvDMD_INTERN_DVBT2.c]MDrv_DMD_DVBT2_SetPlpID\n"));
1721
1722 DMD_DVBT2_SETPLPID_PARAM Drv_DVBT2_SetPlpID_PARAM;
1723 Drv_DVBT2_SetPlpID_PARAM.u8PlpID=u8PlpID;
1724 Drv_DVBT2_SetPlpID_PARAM.u8GroupID=u8GroupID;
1725 Drv_DVBT2_SetPlpID_PARAM.ret=false;
1726
1727 if(u32DVBT2open==1)
1728 UtopiaIoctl(ppDVBT2Instant, DMD_DVBT2_DRV_CMD_SetPlpID, &Drv_DVBT2_SetPlpID_PARAM);
1729 else
1730 return false;
1731
1732 return Drv_DVBT2_SetPlpID_PARAM.ret;
1733
1734 #if 0
1735 MS_BOOL bRet = FALSE;
1736
1737 if (INTERN_DVBT2_GetLock(E_DMD_DVBT2_FEC_LOCK) == TRUE)
1738 {
1739 if (u8PlpID != 0xFF)
1740 {
1741 MS_U16 u16Retry = 0;
1742 MS_U8 u8GroupId = 0;
1743 MsOS_DelayTask(500);
1744
1745 bRet = INTERN_DVBT2_GetPlpGroupID(u8PlpID, &u8GroupId);
1746 while ((bRet == FALSE) && (u16Retry < 60))
1747 {
1748 u16Retry++;
1749 printf("DoSet_DVBT2 get groupid retry %d \n", u16Retry);
1750 MsOS_DelayTask(100);
1751 bRet = INTERN_DVBT2_GetPlpGroupID(u8PlpID, &u8GroupId);
1752 }
1753 if (bRet == FALSE)
1754 {
1755 printf("DoSet_DVBT2() INTERN_DVBT2_GetPlpGroupID(%d) Error \n", u8PlpID);
1756 return FALSE;
1757 }
1758
1759 bRet = INTERN_DVBT2_SetPlpGroupID(u8PlpID, u8GroupId);
1760 if (bRet == FALSE)
1761 {
1762 printf("DoSet_DVBT2() INTERN_DVBT2_SetPlpGroupID(%d,%d) Error", u8PlpID, u8GroupId);
1763 return FALSE;
1764 }
1765 }
1766 }
1767 else
1768 {
1769 return FALSE;
1770 }
1771
1772 return TRUE;
1773 #endif
1774 }