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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file halDAC.c
98 /// @author MStar Semiconductor Inc.
99 /// @brief DAC Utility HAL
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102 #define HAL_DAC_C
103
104 //-------------------------------------------------------------------------------------------------
105 // Include Files
106 //-------------------------------------------------------------------------------------------------
107
108 #include "MsCommon.h"
109 #include "MsIRQ.h"
110 #include "drvDAC.h"
111 #include "halDAC.h"
112
113 #include "hdgen_table.c"
114 #include "hwreg_dac.h"
115
116 #include "mdrv_dac_tbl.h"
117 #include "UFO.h"
118 #ifdef MSOS_TYPE_LINUX_KERNEL
119 #include <linux/string.h>
120 #include <linux/delay.h>
121 #include <asm/div64.h>
122 #else
123 #include "string.h"
124 #define do_div(x,y) ((x)/=(y))
125 #endif
126
127 #include "drvSYS.h"
128 //-------------------------------------------------------------------------------------------------
129 // Driver Compiler Options
130 //-------------------------------------------------------------------------------------------------
131
132
133 //-------------------------------------------------------------------------------------------------
134 // Local Defines
135 //-------------------------------------------------------------------------------------------------
136 #define DAC_DETECT_DELAY 1000
137 #define DAC_DETECT_COUNT 3
138 #define DAC_DETECT_COUNT_HALF 0x1FE //FULL is 0x3FC
139 #define DAC_DETECT_TIMEOUT 10
140 #define DAC_DETECT_G_Channel 0
141 #define DAC_DETECT_B_Channel BIT(8)
142 #define DAC_DETECT_R_Channel BIT(9)
143 #define DAC_TAB_MAX_SIZE 2048
144 #define DAC_DBG(msg) //msg
145 //#define DAC_DETECT_ISR_ENABLE 1
146
147 #define DAC_HDDAC_DEFAULT_OUTPUTSWAPSEL DAC_R_G_B
148 #define DAC_SDDAC_DEFAULT_OUTPUTSWAPSEL DAC_R_G_B
149
150 #define DAC_ASSERT(_cnd, _fmt, _args...) \
151 if (!(_cnd)) { \
152 printf("DAC ASSERT: %s %d:"_fmt, __FILE__, __LINE__, ##_args); \
153 while(1); \
154 }
155
156
157 #ifndef UNUSED
158 #define UNUSED(x) (void)(x)
159 #endif
160
161 MS_BOOL bDacIRQInit = FALSE;
162 MS_VIRT gu32DacRiuBaseAddr = 0;
163 static MS_BOOL bIsSDDACInited = FALSE;
164 static MS_BOOL bIsHDDACInited = FALSE;
165
166 static E_DAC_PANEL_INDEX _geDACPanel_index = DAC_PANEL_480I_60;
167 extern DAC_TAB_INFO DACPANEL_MainTbl[DAC_PANEL_NUMS];
_Hal_DAC_GetTabSize(MS_U8 * pDacTab,MS_U16 u16tabtype,MS_U32 * pu32DacTabsize)168 static void _Hal_DAC_GetTabSize(MS_U8 *pDacTab, MS_U16 u16tabtype, MS_U32 *pu32DacTabsize)
169 {
170 MS_U8 u8Colslen = 0;
171 MS_U16 u16timeout = 0x3FFF;
172 MS_U16 u16Addr;
173 if (pDacTab == NULL)
174 {
175 DAC_ASSERT(0, "[%s] DacTable error \n.", __FUNCTION__);
176 return;
177 }
178 switch(u16tabtype )
179 {
180 case DAC_TABTYPE_INIT:
181 case DAC_TABTYPE_INIT_GPIO:
182 case DAC_TABTYPE_INIT_SC:
183 case DAC_TABTYPE_INIT_MOD:
184 case DAC_TABTYPE_INIT_HDGEN:
185 case DAC_TABTYPE_INIT_HDMITX_8BIT:
186 case DAC_TABTYPE_INIT_HDMITX_10BIT:
187 case DAC_TABTYPE_INIT_HDMITX_12BIT:
188 case DAC_TABTYPE_INIT_HDMITX_16BIT:
189 case DAC_TABTYPE_INIT_HDMITX_8BIT_Divider:
190 case DAC_TABTYPE_INIT_HDMITX_10BIT_Divider:
191 case DAC_TABTYPE_INIT_HDMITX_12BIT_Divider:
192 case DAC_TABTYPE_INIT_HDMITX_16BIT_Divider:
193 case DAC_TABTYPE_SC1_INIT:
194 case DAC_TABTYPE_SC1_INIT_SC:
195 u8Colslen = 4;
196 break;
197 // case DAC_TABTYPE_POWER_SEQUENCE_ON:
198 // case DAC_TABTYPE_POWER_SEQUENCE_OFF:
199 // u8Colslen = 7;
200 // break;
201 default:
202 DAC_ASSERT(0, "[%s] GetTable Size :unknown Tab Size \n.", __FUNCTION__);
203 return ;
204 }
205 while (--u16timeout)
206 {
207 u16Addr = (pDacTab[*pu32DacTabsize]<<8) + pDacTab[(*pu32DacTabsize +1)];
208 if (u16Addr == REG_TABLE_END) // check end of table
209 {
210 *pu32DacTabsize = *pu32DacTabsize + 4;
211 break;
212 }
213 *pu32DacTabsize = *pu32DacTabsize + u8Colslen;
214 }
215 if (u16timeout==0)
216 {
217 DAC_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
218 }
219
220 DAC_DBG(printf("<<*pu32DacTabsize= %ld>>\n", *pu32DacTabsize));
221
222 if(*pu32DacTabsize > DAC_TAB_MAX_SIZE)
223 {
224 DAC_ASSERT(0, "[%s] Tab size too large than DAC_TAB_MAX_SIZE = %d \n.", __FUNCTION__, DAC_TAB_MAX_SIZE);
225 }
226 }
227
_Hal_DAC_DumpGENRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])228 static void _Hal_DAC_DumpGENRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])
229 {
230 MS_U32 u32tabIdx = 0;
231 MS_U16 u16timeout = 0x3FFF;
232 MS_U32 u32Addr;
233 MS_U16 u16Mask;
234 MS_U16 u16Value;
235
236 DAC_DBG(printf("tab: gen \n"));
237
238 if (u8DacTab == NULL)
239 {
240 DAC_ASSERT(0, "[%s] DacTable error \n.", __FUNCTION__);
241 return;
242 }
243
244 while (--u16timeout)
245 {
246 u32Addr = ((u8DacTab[u32tabIdx]<<8) + u8DacTab[(u32tabIdx +1)]) & 0xFFFF;
247 u16Mask = u8DacTab[(u32tabIdx +2)] & 0xFF;
248 u16Value = u8DacTab[(u32tabIdx +3)] & 0xFF;
249
250 if (u32Addr == REG_TABLE_END) // check end of table
251 break;
252
253 DAC_DBG(printf("[addr=%04lx, msk=%02x, val=%02x] \n", u32Addr, u16Mask, u16Value));
254
255 u32Addr|=0x100000; //Convert to NonPM address
256
257 if (u32Addr & 0x1)
258 {
259 u32Addr --;
260 W2BYTE_TAB(u32Addr, (u16Value << 8), (u16Mask << 8));
261 }
262 else
263 {
264 W2BYTE_TAB(u32Addr, u16Value, u16Mask);
265 }
266 u32tabIdx = u32tabIdx + 4;
267 }
268
269 if (u16timeout==0)
270 {
271 DAC_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
272 }
273 }
274
275
_Hal_DAC_DumpHDMITxRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])276 static void _Hal_DAC_DumpHDMITxRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])
277 {
278 MS_U32 u32tabIdx = 0;
279 MS_U16 u16timeout = 0x3FFF;
280 MS_U32 u32Addr;
281 MS_U16 u16Mask;
282 MS_U16 u16Value;
283
284 DAC_DBG(printf( "tab: gen HDMITX\n"));
285
286 if (u8DacTab == NULL)
287 {
288 DAC_ASSERT(0, "[%s] DACTable error \n.", __FUNCTION__);
289 return;
290 }
291
292 while (--u16timeout)
293 {
294 u32Addr = ((u8DacTab[u32tabIdx]<<8) + u8DacTab[(u32tabIdx +1)]) & 0xFFFF;
295 u16Mask = u8DacTab[(u32tabIdx +2)] & 0xFF;
296 u16Value = u8DacTab[(u32tabIdx +3)] & 0xFF;
297
298 if ((((u8DacTab[u32tabIdx]<<8) + u8DacTab[(u32tabIdx +1)]) & 0xFFFF) == REG_TABLE_END) // check end of table
299 break;
300
301 DAC_DBG(printf( "[addr=%04lx, msk=%02x, val=%02x] \n", u32Addr, u16Mask, u16Value));
302 //printf("_MDrv_DAC_DumpHighbyteRegTab [addr=%lx, msk=%02x, val=%02x] \n", u32Addr, u16Mask, u16Value);
303
304 if(((u32Addr | DAC_PLL_ADDR_OFFSET) & 0xFFFF00) == DAC_PLL_BASE)
305 {
306 u32Addr |= DAC_PLL_ADDR_OFFSET;
307 }
308 else
309 {
310 u32Addr |= HDMITX_DIV_ADDR_OFFSET; //Convert to NonPM address
311 }
312 if (u32Addr & 0x1)
313 {
314 u32Addr --;
315 W2BYTE_TAB(u32Addr, (u16Value << 8), (u16Mask << 8));
316 }
317 else
318 {
319 W2BYTE_TAB(u32Addr, u16Value, u16Mask);
320 }
321
322 u32tabIdx = u32tabIdx + 4;
323
324 }
325
326 if (u16timeout==0)
327 {
328 DAC_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
329 }
330 }
331
332
_Hal_DAC_DumpHDMITxDivRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])333 static void _Hal_DAC_DumpHDMITxDivRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])
334 {
335 MS_U32 u32tabIdx = 0;
336 MS_U16 u16timeout = 0x3FFF;
337 MS_U32 u32Addr;
338 MS_U16 u16Mask;
339 MS_U16 u16Value;
340
341 DAC_DBG(printf( "tab: gen HDMITX\n"));
342
343 if (u8DacTab == NULL)
344 {
345 DAC_ASSERT(0, "[%s] DACTable error \n.", __FUNCTION__);
346 return;
347 }
348
349 while (--u16timeout)
350 {
351 u32Addr = ((u8DacTab[u32tabIdx]<<8) + u8DacTab[(u32tabIdx +1)]) & 0xFFFF;
352 u16Mask = u8DacTab[(u32tabIdx +2)] & 0xFF;
353 u16Value = u8DacTab[(u32tabIdx +3)] & 0xFF;
354
355 if ((((u8DacTab[u32tabIdx]<<8) + u8DacTab[(u32tabIdx +1)]) & 0xFFFF) == REG_TABLE_END) // check end of table
356 break;
357
358 DAC_DBG(printf( "[addr=%04lx, msk=%02x, val=%02x] \n", u32Addr, u16Mask, u16Value));
359 //printf("_MDrv_DAC_DumpHighbyteRegTab [addr=%lx, msk=%02x, val=%02x] \n", u32Addr, u16Mask, u16Value);
360
361 if(((u32Addr | DAC_PLL_ADDR_OFFSET) & 0xFFFF00) == DAC_PLL_BASE)
362 {
363 u32Addr |= DAC_PLL_ADDR_OFFSET;
364 }
365 else
366 {
367 u32Addr |= HDMITX_DIV_ADDR_OFFSET; //Convert to PM or NonPM address
368 }
369 if (u32Addr & 0x1)
370 {
371 u32Addr --;
372 W2BYTE_TAB(u32Addr, (u16Value << 8), (u16Mask << 8));
373 }
374 else
375 {
376 W2BYTE_TAB(u32Addr, u16Value, u16Mask);
377 }
378
379 u32tabIdx = u32tabIdx + 4;
380
381 }
382
383 if (u16timeout==0)
384 {
385 DAC_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
386 }
387 }
388
389
_Hal_DAC_DumpSCRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])390 static void _Hal_DAC_DumpSCRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])
391 {
392 MS_U32 u32tabIdx = 0;
393 MS_U16 u16timeout = 0x3FFF;
394 MS_U32 u32Addr;
395 MS_U16 u16CurBank;
396 MS_U16 u16LastBank = 0xff;
397 MS_U8 u8Mask;
398 MS_U8 u8Value;
399
400 MS_U16 u16Bank;
401
402 u16Bank = (R2BYTE_TAB(XC_SC_BK_SELECT, 0xFF) & 0xFF);
403
404 DAC_DBG(printf( "tab: sc \n"));
405
406 if (u8DacTab == NULL)
407 {
408 DAC_ASSERT(0, "[%s] DACTable error \n.", __FUNCTION__);
409 return;
410 }
411
412 while (--u16timeout)
413 {
414 u32Addr = (((u8DacTab[u32tabIdx]<<8) + u8DacTab[(u32tabIdx +1)]) & 0xFFFF);
415 u8Mask = u8DacTab[(u32tabIdx +2)] & 0xFF;
416 u8Value = u8DacTab[(u32tabIdx +3)] & 0xFF;
417
418 if (u32Addr == REG_TABLE_END) // check end of table
419 break;
420
421 u16CurBank = ((u32Addr & 0xFFFF) >> 8);
422 if (u16CurBank != u16LastBank)
423 {
424 DAC_DBG(printf( "<<bankswitch=%02x>> \n", u16CurBank));
425 W2BYTE_TAB(XC_SC_BK_SELECT, u16CurBank, 0xFF);
426 u16LastBank = u16CurBank;
427 }
428 DAC_DBG(printf( "[addr=%04lx, msk=%02x, val=%02x] \n", BK_SC((u32Addr & 0x00FF)), u8Mask, u8Value));
429
430 W1BYTE_TAB( (BK_SC((u32Addr & 0x00FF))|0x100000), u8Value, u8Mask);
431
432 u32tabIdx = u32tabIdx + 4;
433 }
434 W2BYTE_TAB(XC_SC_BK_SELECT, u16Bank, 0xFF);
435 if (u16timeout==0)
436 {
437 DAC_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
438 }
439 }
440
_Hal_DAC_DumpHDGENRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])441 static void _Hal_DAC_DumpHDGENRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])
442 {
443 MS_U32 u32tabIdx = 0;
444 MS_U16 u16timeout = 0x3FFF;
445 MS_U32 u32Addr;
446 MS_U8 u8Mask;
447 MS_U8 u8Value;
448 MS_U16 u16CurBank;
449 MS_U16 u16LastBank = 0xff;
450
451 MS_U16 u16Bank;
452
453 u16Bank = (R2BYTE_TAB(HDGEN_BK_SELECT, 0xFF) & 0xFF);
454
455 DAC_DBG(printf( "tab: HDGEN \n"));
456
457 if (u8DacTab == NULL)
458 {
459 DAC_ASSERT(0, "[%s] DACTable error \n.", __FUNCTION__);
460 return;
461 }
462
463 while (--u16timeout)
464 {
465 u32Addr = ((u8DacTab[u32tabIdx]<<8) + u8DacTab[(u32tabIdx +1)]) & 0xFFFF;
466 u8Mask = u8DacTab[(u32tabIdx +2)] & 0xFF;
467 u8Value = u8DacTab[(u32tabIdx +3)] & 0xFF;
468
469 if (u32Addr == REG_TABLE_END) // check end of table
470 break;
471
472 u16CurBank = ((u32Addr & 0xFFFF) >> 8);
473 if (u16CurBank != u16LastBank)
474 {
475 DAC_DBG(printf( "<<bankswitch=%02x>> \n", u16CurBank));
476 W2BYTE_TAB(HDGEN_BK_SELECT, u16CurBank, 0xFF);
477 u16LastBank = u16CurBank;
478 }
479
480 DAC_DBG(printf( "[addr=%04lx, msk=%02x, val=%02x] \n", BK_HDGEN((u32Addr & 0x00FF)), u8Mask, u8Value));
481 //printf("[addr=%04lx, msk=%02x, val=%02x] \n", BK_HDGEN((u32Addr & 0x00FF))|bHiByte, u16Mask, u16Value);
482
483 W1BYTE_TAB( (BK_HDGEN((u32Addr & 0x00FF))|0x100000), u8Value, u8Mask);
484 u32tabIdx = u32tabIdx + 4;
485 }
486 W2BYTE_TAB(HDGEN_BK_SELECT, u16Bank, 0xFF);
487 if (u16timeout==0)
488 {
489 DAC_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
490 }
491 }
492
_Hal_DAC_DumpMODRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])493 static void _Hal_DAC_DumpMODRegTab(MS_U8 u8DacTab[DAC_TAB_MAX_SIZE])
494 {
495 MS_U32 u32tabIdx = 0;
496 MS_U16 u16timeout = 0x3FFF;
497 MS_U32 u32Addr;
498 MS_U16 u16Mask;
499 MS_U16 u16Value;
500 MS_U16 u16CurBank;
501 MS_U16 u16LastBank = 0xff;
502 MS_BOOL bHiByte;
503
504 MS_U16 u16Bank;
505
506 u16Bank = (R2BYTE_TAB(XC_MOD_BK_SELECT, 0xFF) & 0xFF);
507
508 DAC_DBG(printf( "tab: mod \n"));
509
510 if (u8DacTab == NULL)
511 {
512 DAC_ASSERT(0, "[%s] DACable error \n.", __FUNCTION__);
513 return;
514 }
515
516 while (--u16timeout)
517 {
518 u32Addr = ((u8DacTab[u32tabIdx]<<8) + u8DacTab[(u32tabIdx +1)]) & 0xFFFF;
519 u16Mask = u8DacTab[(u32tabIdx +2)] & 0xFF;
520 u16Value = u8DacTab[(u32tabIdx +3)] & 0xFF;
521
522 if (u32Addr == REG_TABLE_END) // check end of table
523 break;
524
525 u16CurBank = ((u32Addr & 0x7FFF) >> 8);
526 bHiByte = (u32Addr & 0x8000) ? TRUE : FALSE;
527 if (u16CurBank != u16LastBank)
528 {
529 DAC_DBG(printf( "<<bankswitch=%02x>> \n", u16CurBank));
530 W2BYTE_TAB(XC_MOD_BK_SELECT, u16CurBank, 0xFF);
531 u16LastBank = u16CurBank;
532 }
533 DAC_DBG(printf( "[addr=%04lx, msk=%02x, val=%02x] \n", BK_MOD((u32Addr & 0x00FF))|bHiByte, u16Mask, u16Value));
534
535 if (bHiByte)
536 {
537 W2BYTE_TAB( (BK_MOD((u32Addr & 0x00FF))|0x100000), (u16Value << 8), (u16Mask << 8));
538 }
539 else
540 {
541 W2BYTE_TAB( (BK_MOD((u32Addr & 0x00FF))|0x100000) , u16Value, u16Mask);
542 }
543 u32tabIdx = u32tabIdx + 4;
544 }
545 W2BYTE_TAB(XC_MOD_BK_SELECT, u16Bank, 0xFF);
546 if (u16timeout==0)
547 {
548 DAC_ASSERT(0, "[%s] fails: timeout \n.", __FUNCTION__);
549 }
550 }
551
552
_HAL_DAC_HpdIsr(InterruptNum eIntNum,void * dev_id)553 void _HAL_DAC_HpdIsr(InterruptNum eIntNum, void* dev_id)
554 {
555 //eIntNum = eIntNum; // prevent compile warning
556
557
558 //MS_U16 regval = R2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), 15:0);
559 //DAC_DBG(printf("detect ISR: 0x%04x\n", regval));
560
561 //HD Dac plug in
562 if(R2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), 8:8) == 0x0100)
563 {
564 DAC_DBG(printf("Detect HD DAC plug in !!\n"));
565
566 //change register to detect HD DAC plug out
567 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 12:12);
568 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 14:14);
569 W2BYTE(BK_DAC(REG_DAC_HD_DETECT_CTRL), 0x2422, 15:0);
570 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x0002, 3:0);
571 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x000a, 15:12);
572 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 13:11);
573
574 //toggle to clear final status
575 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), TRUE, 4:4);
576 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), FALSE, 4:4);
577 }
578 //HD DAC plug out
579 else if(R2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), 9:9) == 0x0200)
580 {
581 DAC_DBG(printf("Detect HD DAC plug out !!\n"));
582
583 //change register to detect HD DAC plug in
584 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 12:12);
585 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 14:14);
586 W2BYTE(BK_DAC(REG_DAC_HD_DETECT_CTRL), 0xff21, 15:0);
587 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 13:11);
588
589 //toggle to clear final status
590 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), TRUE, 5:5);
591 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), FALSE, 5:5);
592 }
593
594
595 //SD DAC plug in
596 if(R2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), 10:10) == 0x0400)
597 {
598 DAC_DBG(printf("Detect SD DAC plug in !!\n"));
599
600 //change register to detect SD DAC plug out
601 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 13:13);
602 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), FALSE, 15:15);
603 W2BYTE(BK_DAC(REG_DAC_SD_DETECT_CTRL), 0x0B12, 15:0);
604 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x0002, 3:0);
605 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0x000a, 11:8);
606 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 10:8);
607
608 //toggle to clear final status
609 W2BYTE(BK_DAC(REG_DAC_SD_IRQ_CTRL), TRUE, 4:4);
610 W2BYTE(BK_DAC(REG_DAC_SD_IRQ_CTRL), FALSE, 4:4);
611 }
612 //SD DAC plug out
613 else if(R2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), 11:11) == 0x0800)
614 {
615 DAC_DBG(printf("Detect SD DAC plug out !!\n"));
616
617 //change register to detect HD DAC plug in
618 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 13:13);
619 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 15:15);
620 W2BYTE(BK_DAC(REG_DAC_SD_DETECT_CTRL), 0xff11, 15:0);
621 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 10:8);
622
623 //toggle to clear final status
624 W2BYTE(BK_DAC(REG_DAC_SD_IRQ_CTRL), TRUE, 5:5);
625 W2BYTE(BK_DAC(REG_DAC_SD_IRQ_CTRL), FALSE, 5:5);
626 }
627
628
629 MsOS_EnableInterrupt(E_INT_IRQ_IDAC_PLUG_DET);
630 }
631
_HAL_DAC_InitHpdInt(void)632 static void _HAL_DAC_InitHpdInt(void)
633 {
634 //init register for detect HD DAC plug in
635 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 12:12);
636 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 14:14);
637 W2BYTE(BK_DAC(REG_DAC_HD_DETECT_CTRL), 0xff21, 15:0);
638 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 13:11);
639
640 //init register for detect SD DAC detect plug in
641 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 13:13);
642 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 15:15);
643 W2BYTE(BK_DAC(REG_DAC_SD_DETECT_CTRL), 0xff11, 15:0);
644 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 10:8);
645
646 //HD DAC plug in/out threshld
647 W2BYTE(BK_DAC(REG_DAC_HD_PLUG_IN_THD), 0x001F, 9:0);
648 W2BYTE(BK_DAC(REG_DAC_HD_PLUG_OUT_THD), 0x03E0, 9:0);
649
650 //SD DAC plug in/out threshld
651 W2BYTE(BK_DAC(REG_DAC_SD_PLUG_IN_THD), 0x001F, 9:0);
652 W2BYTE(BK_DAC(REG_DAC_SD_PLUG_OUT_THD), 0x03E0, 9:0);
653
654 //Clear interrupt mask of HD DAC
655 W2BYTE(BK_DAC(REG_DAC_HD_IRQ_CTRL), 0x0000, 1:0);
656 //Clear interrupt mask of SD DAC
657 W2BYTE(BK_DAC(REG_DAC_SD_IRQ_CTRL), 0x0000, 1:0);
658
659 //enable interrupt
660 MsOS_AttachInterrupt(E_INT_IRQ_IDAC_PLUG_DET, (InterruptCb)_HAL_DAC_HpdIsr);
661 MsOS_EnableInterrupt(E_INT_IRQ_IDAC_PLUG_DET);
662
663 }
664
Hal_DAC_Power_Saving(MS_BOOL POWER_SAVING)665 void Hal_DAC_Power_Saving(MS_BOOL POWER_SAVING)
666 {
667 if( 0 == POWER_SAVING )
668 {
669 W1BYTE(L_BK_CHIPTOP(0x59), 0x00, 0:0);
670 W1BYTE(H_BK_CHIPTOP(0x59), 0x00, 0:0);
671 W1BYTE(L_BK_CHIPTOP(0x58), 0x00, 0:0);
672 }
673 else
674 {
675 W1BYTE(L_BK_CHIPTOP(0x59), 0x01, 0:0);
676 W1BYTE(H_BK_CHIPTOP(0x59), 0x01, 0:0);
677 W1BYTE(L_BK_CHIPTOP(0x58), 0x01, 0:0);
678 }
679 }
680
Hal_DAC_SetIOMapBase(MS_VIRT u32NPMBase,MS_VIRT u32PMBase)681 void Hal_DAC_SetIOMapBase(MS_VIRT u32NPMBase, MS_VIRT u32PMBase)
682 {
683 gu32DacRiuBaseAddr = u32PMBase;
684 }
685
Hal_HDMITx_InitSeq(void)686 void Hal_HDMITx_InitSeq(void)
687 {
688 W1BYTE(L_BK_HDMITX(0x45), 0x00, 0:0);//enable PLL power control
689 W1BYTE(REG_DAC_04_H, 0x00, REG_EN_IDAC_SEL_REXT_MSK); //Disable External Resistor Selection
690 //DAC PLL
691 W1BYTE(L_BK_ANA_MISC_HDMI(0x01), 0x01, 0:0); //MPLL_432_IN=432MHz
692
693 //W1BYTE(REG_DAC_PLL_15_L, 0x00, 7:0);
694 //W1BYTE(REG_DAC_PLL_15_H, 0x00, 7:0);
695 W1BYTE(REG_DAC_PLL_35_L, 0x02, 7:0); //synth_ssc_mode[0] = 0, synth_ssc_sync[1] = 1
696 W1BYTE(REG_DAC_PLL_35_H, 0x00, 7:0);
697 W1BYTE(REG_DAC_PLL_33_L, 0x00, 7:0); //synth_ssc_step[11:0]=7
698 W1BYTE(REG_DAC_PLL_33_H, 0x00, 7:0);
699 W1BYTE(REG_DAC_PLL_34_L, 0x00, 7:0); //synth_ssc_span[13:0]=445
700 W1BYTE(REG_DAC_PLL_34_H, 0x00, 7:0);
701
702 W2BYTE(BK_DAC(REG_DAC_VSYNC_DETECT_CTRL), 1, 0:0); //Enable ECO: CVBS hotplug detect in VSync
703 W2BYTE(BK_DAC(REG_DAC_PLUG_INOUT_PERIOD), 0x00, 15:8);
704
705 }
706
707 // for DAC, SD means AV/SV output control, HD means YPbPr output control
708 // SD = AV/SV
709 // HD = YPbPr
Hal_DAC_Enable(MS_BOOL bEnable,MS_BOOL bIsYPbPr)710 void Hal_DAC_Enable(MS_BOOL bEnable, MS_BOOL bIsYPbPr)
711 {
712
713 //Enable IDAC ref.
714 W1BYTE(BK_DAC(REG_EN_IDAC_REF), 1, REG_EN_IDAC_REF_MSK);
715
716 //MS_U32 u32DACMode = R1BYTE(H_BK_CHIPTOP_TOP(0x60),15:0);
717 //printf("Dac Mode %d\n",u32DACMode);
718 //if(u32DACMode == DAC_MODE_VDAC) //VDAC
719 //{
720 // W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), 0xf200 , 15:0);
721 // W2BYTE(BK_DAC(REG_DAC_BIAS_CUR_CTRL), 0x0001 , 0:0);
722 // W2BYTE(BK_DAC(REG_DAC_CHN_BUF_EN), 0x000f , 4:0);
723 //}
724 //else
725 {
726 //iDAC Mode
727 //W2BYTE(BK_DAC(REG_DAC_SD_CTRL), 0x0001 , 1:1);
728 //W2BYTE(BK_DAC(REG_DAC_SD_CTRL), 0x0010 , 5:4);
729 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE , 9:9);
730 W2BYTE(BK_DAC(REG_DAC_BIAS_CUR_CTRL), 0x0000 , 0:0);
731 W2BYTE(BK_DAC(REG_DAC_CHN_BUF_EN), 0x0000 , 4:0);
732 }
733
734 if (bIsYPbPr)
735 {
736 //On/OFF clock to avoid garbage when TVSystem change
737 W2BYTE(L_BK_CHIPTOP(REG_CKG_DAC2), (~bEnable), REG_CKG_DAC2_DISABLE_MASK); //set clock MUX for R/G/B DAC (CLK_ODCLK_P)
738 MsOS_DelayTask(30);
739
740 //W2BYTE(L_BK_CHIPTOP(REG_CKG_DAC2), 0x00, REG_CKG_DAC2_MASK); //set clock MUX for R/G/B DAC (CLK_ODCLK_P)
741 W1BYTE(BK_DAC(REG_DAC_HD_CTRL), bEnable, REG_EN_IDAC_HDR_MSK);//enable or disable HDGEN YPbPr
742 W1BYTE(BK_DAC(REG_DAC_HD_CTRL), bEnable, REG_EN_IDAC_HDG_MSK);//enable or disable HDGEN YPbPr
743 W1BYTE(BK_DAC(REG_DAC_HD_CTRL), bEnable, REG_EN_IDAC_HDB_MSK);//enable or disable HDGEN YPbPr
744 W1BYTE(BK_DAC(REG_HD_DAT_CLK_INV), bEnable, REG_HD_DAT_CLK_INV_MSK);//enable or disable HDGEN YPbPr
745 W1BYTE(BK_DAC(REG_HD_DAT_CLK_DLY), 0, REG_HD_DAT_CLK_DLY_MSK);
746
747 //Disable HDGEN pattern Gen
748 MS_U16 u16Bank = (R2BYTE_TAB(HDGEN_BK_SELECT, 0xFF) & 0xFF);
749 W2BYTE_TAB(HDGEN_BK_SELECT, 0x2, 0xFF);
750 W1BYTE_TAB(BK_HDGEN(0x60), 0, 0x3);
751 //LPF and upsample
752 W2BYTE_TAB(HDGEN_BK_SELECT, 0x3, 0xFF);
753 W1BYTE_TAB(BK_HDGEN(0xC0), 1, 0x1);
754 W2BYTE_TAB(HDGEN_BK_SELECT, 0x2, 0xFF);
755 W1BYTE_TAB(BK_HDGEN(0x80), 0, 0x1);
756 W2BYTE_TAB(HDGEN_BK_SELECT, u16Bank, 0xFF);
757
758 //Set HD Output Swap Sel
759 if(!bIsHDDACInited)
760 {
761 Hal_DAC_SetOutputSwapSel(DAC_HDDAC_DEFAULT_OUTPUTSWAPSEL, bIsYPbPr);
762 }
763 }
764 else
765 {
766 //On/OFF clock to avoid garbage when TVSystem change
767 W1BYTE(L_BK_CHIPTOP(REG_CKG_DAC1), (~bEnable), REG_CKG_DAC1_DISABLE_MASK); //set clock MUX for X/Y/C DAC (CLK_VEDAC_P)
768 MsOS_DelayTask(30);
769
770 //W1BYTE(L_BK_CHIPTOP(REG_CKG_DAC1), 0x03, REG_CKG_DAC1_MASK); //set clock MUX for X/Y/C DAC (CLK_VEDAC_P)
771 // SD GAIN & Enable SD GAIN or not
772 W2BYTE(BK_DAC(REG_GCR_IDAC_GAINSD), 0, REG_GCR_IDAC_GAINSD_MSK);
773 W2BYTE(BK_DAC(REG_EN_REF_IDAC_GAINSD), 0, REG_EN_REF_IDAC_GAINSD_MSK);
774 // Clk inverse & phase
775 W1BYTE(BK_DAC(REG_SD_DAT_CLK_INV), 1, REG_SD_DAT_CLK_INV_MSK);
776 W1BYTE(BK_DAC(REG_SD_DAT_CLK_DLY), 0, REG_SD_DAT_CLK_DLY_MSK);
777
778 if (bEnable)
779 {
780 // [0] = CVBS, [1] = Y of S-video, [2] = C of S-video
781 // Enable C/Y/X,
782 W1BYTE(BK_DAC(REG_EN_IDAC_SDX), 1, REG_EN_IDAC_SDX_MSK);
783 W1BYTE(BK_DAC(REG_EN_IDAC_SDY), 1, REG_EN_IDAC_SDY_MSK);
784 W1BYTE(BK_DAC(REG_EN_IDAC_SDC), 1, REG_EN_IDAC_SDC_MSK);
785 }
786 else
787 {
788 // [0] = CVBS, [1] = Y of S-video, [2] = C of S-video
789 // Enable C/Y/X,
790 W1BYTE(BK_DAC(REG_EN_IDAC_SDX), 0, REG_EN_IDAC_SDX_MSK);
791 W1BYTE(BK_DAC(REG_EN_IDAC_SDY), 0, REG_EN_IDAC_SDY_MSK);
792 W1BYTE(BK_DAC(REG_EN_IDAC_SDC), 0, REG_EN_IDAC_SDC_MSK);
793 }
794
795 //Set SD Output Swap Sel
796 if(!bIsSDDACInited)
797 {
798 Hal_DAC_SetOutputSwapSel(DAC_SDDAC_DEFAULT_OUTPUTSWAPSEL, bIsYPbPr);
799 }
800 }
801
802 W1BYTE(BK_DAC(REG_EN_IDAC_REF), 1, 6:6);
803 W1BYTE(BK_DAC(REG_EN_IDAC_REF), 0, 6:6);
804
805 }
806
Hal_DAC_SetClkInv(MS_BOOL bEnable,MS_BOOL bIsYPbPr)807 void Hal_DAC_SetClkInv(MS_BOOL bEnable, MS_BOOL bIsYPbPr)
808 {
809 // if (bIsYPbPr)
810 {
811 W2BYTE(BK_DAC(REG_DAC_HD_CLK), bEnable, 0:0);
812 }
813 // else
814 {
815 W2BYTE(BK_DAC(REG_DAC_SD_CLK), bEnable, 0:0);
816 }
817 }
818
Hal_DAC_SetOutputSource(EN_DAC_OUTPUT_TYPE enOutputType,MS_BOOL bIsYPbPr)819 void Hal_DAC_SetOutputSource(EN_DAC_OUTPUT_TYPE enOutputType, MS_BOOL bIsYPbPr)
820 {
821 MS_U8 Output_type,DacClk;
822
823 switch(enOutputType)
824 {
825 case DAC_TO_HDGEN:
826 Output_type = 0x00;
827 DacClk = 0x00;
828 break;
829
830 case DAC_TO_VE:
831 Output_type = 0x01;
832 DacClk = 0x03;
833 break;
834
835 case DAC_TO_VE_YPBPR:
836 Output_type = 0x03;
837 DacClk = 0x03;
838 break;
839 default:
840 printf("Invalid DAC output %d", enOutputType);
841 return;
842 }
843 if (bIsYPbPr)
844 {
845 W1BYTE(BK_DAC(REG_DAC_HD_SEL), Output_type, 1:0);
846 W1BYTE(H_BK_CHIPTOP(REG_CKG_DAC2), DacClk, 3:2);
847 }
848 else
849 {
850 W1BYTE(BK_DAC(REG_DAC_SD_SEL), Output_type, 1:0);
851 W1BYTE(L_BK_CHIPTOP(REG_CKG_DAC1), DacClk, 3:2);
852 }
853
854
855 }
856
Hal_DAC_SetOutputLevel(EN_DAC_MAX_OUTPUT_LEVEL enLevel,MS_BOOL bIsYPbPr)857 void Hal_DAC_SetOutputLevel(EN_DAC_MAX_OUTPUT_LEVEL enLevel, MS_BOOL bIsYPbPr)
858 {
859 MS_U32 u32DACMode = R1BYTE(H_BK_CHIPTOP_TOP(0x60),15:0);
860
861 if(u32DACMode == DAC_MODE_VDAC) //VDAC
862 {
863 return; // VDAC mode need ignore this
864 }
865
866 if (bIsYPbPr)
867 {
868 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), (MS_BOOL)enLevel, 9:9);
869 }
870 else
871 {
872 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), (MS_BOOL)enLevel, 10:10);
873 }
874 }
875
Hal_DAC_SetOutputSwapSel(EN_DAC_SWAP_SEL enSwap,MS_BOOL bIsYPbPr)876 void Hal_DAC_SetOutputSwapSel(EN_DAC_SWAP_SEL enSwap,MS_BOOL bIsYPbPr)
877 {
878 if (bIsYPbPr)
879 {
880 W2BYTE(BK_DAC(REG_HD_DAC_SWAP_SEL), enSwap, 10:8);
881 }
882 else
883 {
884 W2BYTE(BK_DAC(REG_SD_DAC_SWAP_SEL), enSwap, 10:8);
885 }
886 }
887
Hal_DAC_OnOffSD(EN_DAC_SD_ENABLE_CTRL enBit)888 void Hal_DAC_OnOffSD(EN_DAC_SD_ENABLE_CTRL enBit)
889 {
890 W1BYTE(BK_DAC(REG_DAC_SD_CTRL),enBit , 2:0);
891 }
Hal_DAC_GetSDStatus(void)892 EN_DAC_SD_ENABLE_CTRL Hal_DAC_GetSDStatus(void)
893 {
894 return R1BYTE(BK_DAC(REG_DAC_SD_CTRL), 2:0);
895 }
Hal_DAC_OnOffHD(EN_DAC_HD_ENABLE_CTRL enBit)896 void Hal_DAC_OnOffHD(EN_DAC_HD_ENABLE_CTRL enBit)
897 {
898 W1BYTE(BK_DAC(REG_DAC_HD_CTRL),enBit , 2:0);
899 }
Hal_DAC_GetHDStatus(void)900 EN_DAC_HD_ENABLE_CTRL Hal_DAC_GetHDStatus(void)
901 {
902 return R1BYTE(BK_DAC(REG_DAC_HD_CTRL), 2:0);
903 }
Hal_HDGEN_SetTiming(EN_OUTPUT_VIDEO_TIMING_TYPE enTiming)904 void Hal_HDGEN_SetTiming(EN_OUTPUT_VIDEO_TIMING_TYPE enTiming)
905 {
906 #if 0 //use mdrv_dac_tbl instead
907
908 MS_U8 *pu8Table;
909 MS_U32 u32Addr = 0;
910
911 if (enTiming == RES_720x480I_60Hz)
912 {
913 pu8Table = (MS_U8 *)HDGEN_480I_60;
914 }
915 else if (enTiming == RES_720x480P_60Hz)
916 {
917 pu8Table = (MS_U8 *)HDGEN_480P_60;
918 }
919 else if (enTiming == RES_720x576I_50Hz)
920 {
921 pu8Table = (MS_U8 *)HDGEN_576I_50;
922 }
923 else if (enTiming == RES_720x576P_50Hz)
924 {
925 pu8Table = (MS_U8 *)HDGEN_576P_50;
926 }
927 else if (enTiming == RES_1280x720P_50Hz)
928 {
929 pu8Table = (MS_U8 *)HDGEN_720P_50;
930 }
931 else if (enTiming == RES_1280x720P_60Hz)
932 {
933 pu8Table = (MS_U8 *)HDGEN_720P_60;
934 }
935 else if (enTiming == RES_1920x1080I_50Hz)
936 {
937 pu8Table = (MS_U8 *)HDGEN_1080I_50;
938 }
939 else if (enTiming == RES_1920x1080I_60Hz)
940 {
941 pu8Table = (MS_U8 *)HDGEN_1080I_60;
942 }
943 else if (enTiming == RES_1920x1080P_50Hz)
944 {
945 pu8Table = (MS_U8 *)HDGEN_1080P_50;
946 }
947 else if (enTiming == RES_1920x1080P_60Hz)
948 {
949 pu8Table = (MS_U8 *)HDGEN_1080P_60;
950 }
951 else
952 {
953 printf("Invalid timing type %d", enTiming);
954 return;
955 }
956
957 while (1)
958 {
959 u32Addr = (pu8Table[0]<<8) + pu8Table[1];
960 if (u32Addr == 0xFFFF)
961 break;
962 //printf("%x: %x\n", (int)(NONPM_BASE+u32Addr), pu8Table[2]);
963 W1BYTE((NONPM_BASE+u32Addr), pu8Table[2], 7:0);
964 pu8Table += 4;
965 }
966 #else
967
968 //Use the timing to get the reference Dac Panel index
969 switch(enTiming)
970 {
971 case RES_720x480I_60Hz:
972 _geDACPanel_index = DAC_PANEL_480I_60;
973 break;
974 case RES_720x480P_60Hz:
975 _geDACPanel_index = DAC_PANEL_480P_60;
976 break;
977 case RES_720x576I_50Hz:
978 _geDACPanel_index = DAC_PANEL_576I_50;
979 break;
980 case RES_720x576P_50Hz:
981 _geDACPanel_index = DAC_PANEL_576P_50;
982 break;
983 case RES_1280x720P_50Hz:
984 _geDACPanel_index = DAC_PANEL_720P_50;
985 break;
986 case RES_1280x720P_60Hz:
987 _geDACPanel_index = DAC_PANEL_720P_60;
988 break;
989 case RES_1920x1080I_50Hz:
990 _geDACPanel_index = DAC_PANEL_1080I_50;
991 break;
992 case RES_1920x1080I_60Hz:
993 _geDACPanel_index = DAC_PANEL_1080I_60;
994 break;
995 case RES_1920x1080P_50Hz:
996 _geDACPanel_index = DAC_PANEL_1080P_50;
997 break;
998 case RES_1920x1080P_60Hz:
999 _geDACPanel_index = DAC_PANEL_1080P_60;
1000 break;
1001 case RES_1920x1080P_24Hz:
1002 _geDACPanel_index = DAC_PANEL_1080P_24;
1003 break;
1004 case RES_1920x1080P_25Hz:
1005 _geDACPanel_index = DAC_PANEL_1080P_25;
1006 break;
1007 case RES_1920x1080P_30Hz:
1008 _geDACPanel_index = DAC_PANEL_1080P_30;
1009 break;
1010 case RES_1920x2205P_24Hz:
1011 _geDACPanel_index = DAC_PANEL_1920x2205P_24;
1012 break;
1013 case RES_1280x1470P_50Hz:
1014 _geDACPanel_index = DAC_PANEL_1280x1470P_50;
1015 break;
1016 case RES_1280x1470P_60Hz:
1017 _geDACPanel_index = DAC_PANEL_1280x1470P_60;
1018 break;
1019 case RES_640x480P_60Hz:
1020 _geDACPanel_index = DAC_PANEL_640x480_60;
1021 break;
1022 case RES_3840x2160P_24Hz:
1023 _geDACPanel_index = DAC_PANEL_3840x2160P_24;
1024 break;
1025 case RES_3840x2160P_25Hz:
1026 _geDACPanel_index = DAC_PANEL_3840x2160P_25;
1027 break;
1028 case RES_3840x2160P_30Hz:
1029 _geDACPanel_index = DAC_PANEL_3840x2160P_30;
1030 break;
1031 case RES_3840x2160P_50Hz:
1032 _geDACPanel_index = DAC_PANEL_3840x2160P_50;
1033 break;
1034 case RES_3840x2160P_60Hz:
1035 _geDACPanel_index = DAC_PANEL_3840x2160P_60;
1036 break;
1037 case RES_4096x2160P_24Hz:
1038 _geDACPanel_index = DAC_PANEL_4096x2160P_24;
1039 break;
1040 case RES_4096x2160P_25Hz:
1041 _geDACPanel_index = DAC_PANEL_4096x2160P_25;
1042 break;
1043 case RES_4096x2160P_30Hz:
1044 _geDACPanel_index = DAC_PANEL_4096x2160P_30;
1045 break;
1046 case RES_4096x2160P_50Hz:
1047 _geDACPanel_index = DAC_PANEL_4096x2160P_50;
1048 break;
1049 case RES_4096x2160P_60Hz:
1050 _geDACPanel_index = DAC_PANEL_4096x2160P_60;
1051 break;
1052 case RES_3840x2160P420_30Hz:
1053 _geDACPanel_index = DAC_PANEL_3840x2160P420_30;
1054 break;
1055 case RES_3840x2160P420_50Hz:
1056 _geDACPanel_index = DAC_PANEL_3840x2160P420_50;
1057 break;
1058 case RES_3840x2160P420_60Hz:
1059 _geDACPanel_index = DAC_PANEL_3840x2160P420_60;
1060 break;
1061 case RES_4096x2160P420_30Hz:
1062 _geDACPanel_index = DAC_PANEL_4096x2160P420_30;
1063 break;
1064 case RES_4096x2160P420_50Hz:
1065 _geDACPanel_index = DAC_PANEL_4096x2160P420_50;
1066 break;
1067 case RES_4096x2160P420_60Hz:
1068 _geDACPanel_index = DAC_PANEL_4096x2160P420_60;
1069 break;
1070 case RES_1600x1200P_60Hz:
1071 _geDACPanel_index = DAC_PANEL_1600x1200P_60;
1072 break;
1073 case RES_1440x900P_60Hz:
1074 _geDACPanel_index = DAC_PANEL_1440x900P_60;
1075 break;
1076 case RES_1280x1024P_60Hz:
1077 _geDACPanel_index = DAC_PANEL_1280x1024P_60;
1078 break;
1079 case RES_1024x768P_60Hz:
1080 _geDACPanel_index = DAC_PANEL_1024x768P_60;
1081 break;
1082 default:
1083 printf("[%s][%d]Wrong Output Video Timing Type %d!!!\n",__FUNCTION__,__LINE__,enTiming);
1084 return;
1085 }
1086
1087 printf("DAC Panel Table Index =%d\n", _geDACPanel_index);
1088
1089 #endif
1090 }
1091
1092 //----------------------------------------------------------------
1093 // DAC - set half output current
1094 // @return none
1095 //----------------------------------------------------------------
Hal_DAC_SetIHalfOutput(MS_BOOL bEnable,MS_BOOL bIsYPbPr)1096 void Hal_DAC_SetIHalfOutput(MS_BOOL bEnable, MS_BOOL bIsYPbPr)
1097 {
1098 MS_U32 u32DACMode = R1BYTE(H_BK_CHIPTOP_TOP(0x60),15:0);
1099
1100 if(u32DACMode == DAC_MODE_VDAC) //VDAC
1101 {
1102 return; // VDAC mode need ignore this
1103 }
1104
1105 if (bIsYPbPr)
1106 {
1107 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), (MS_BOOL)bEnable, 12:12);
1108 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), DISABLE, 14:14);
1109 }
1110 else
1111 {
1112 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), (MS_BOOL)bEnable, 13:13);
1113 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), DISABLE, 15:15);
1114 }
1115 }
1116
1117 //----------------------------------------------------------------
1118 // DAC - set quart output current
1119 // @return none
1120 //----------------------------------------------------------------
Hal_DAC_SetQuartOutput(MS_BOOL bEnable,MS_BOOL bIsYPbPr)1121 void Hal_DAC_SetQuartOutput(MS_BOOL bEnable, MS_BOOL bIsYPbPr)
1122 {
1123 MS_U32 u32DACMode = R1BYTE(H_BK_CHIPTOP_TOP(0x60),15:0);
1124
1125 if(u32DACMode == DAC_MODE_VDAC) //VDAC
1126 {
1127 return; // VDAC mode need ignore this
1128 }
1129
1130 if (bIsYPbPr)
1131 {
1132 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), (MS_BOOL)bEnable, 12:12);
1133 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), (MS_BOOL)bEnable, 14:14);
1134 }
1135 else
1136 {
1137 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), (MS_BOOL)bEnable, 13:13);
1138 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), (MS_BOOL)bEnable, 15:15);
1139 }
1140 }
1141
1142 //----------------------------------------------------------------
1143 // Hal_DAC_SetDACState - Set DAC init state
1144 // @param: bEnable: TRUE for DAC is initialized, FALSE for not initialized
1145 // @param: bIsYPbPr: TRUE for YPbPr, FALSE for CVBS
1146 // @return none
1147 //----------------------------------------------------------------
Hal_DAC_SetDACState(MS_BOOL bEnable,MS_BOOL bIsYPbPr)1148 void Hal_DAC_SetDACState(MS_BOOL bEnable, MS_BOOL bIsYPbPr)
1149 {
1150 if (bIsYPbPr)
1151 {
1152 bIsHDDACInited = bEnable;
1153 }
1154 else
1155 {
1156 bIsSDDACInited = bEnable;
1157 }
1158 }
1159
1160 //----------------------------------------------------------------
1161 // Hal_DAC_GetDACState - Get DAC init state
1162 // @param: bIsYPbPr: TRUE for YPbPr, FALSE for CVBS
1163 // @return: TRUE is DAC is initialized
1164 //----------------------------------------------------------------
Hal_DAC_GetDACState(MS_BOOL bIsYPbPr)1165 MS_BOOL Hal_DAC_GetDACState(MS_BOOL bIsYPbPr)
1166 {
1167 if (bIsYPbPr)
1168 {
1169 return bIsHDDACInited;
1170 }
1171 else
1172 {
1173 return bIsSDDACInited;
1174 }
1175 }
1176
1177 //----------------------------------------------------------------
1178 // Hal_DAC_HotPlugDetect - Get DAC HotPlug state
1179 // @param: SelDAC: DAC_DETECT_HD, DAC_DETECT_SD
1180 // @param: DetectType: DAC_DETECT_PLUGIN, DAC_DETECT_PLUGOUT
1181 // @param: bIsSignIn: Report signal is in/out
1182 // @return: TRUE is working successful
1183 //----------------------------------------------------------------
Hal_DAC_HotPlugDetect(EN_DAC_DETECT SelDAC,EN_DAC_DETECT_TYPE DetectType,MS_BOOL * bIsSignIn)1184 MS_BOOL Hal_DAC_HotPlugDetect(EN_DAC_DETECT SelDAC, EN_DAC_DETECT_TYPE DetectType, MS_BOOL *bIsSignIn)
1185 {
1186 MS_U16 u16DetectCount = DAC_DETECT_COUNT;
1187 MS_U16 u16TimeoutCount = 0;
1188 MS_U16 Channel_Select = BIT(5);
1189
1190 if(bIsSignIn == NULL)
1191 {
1192 printf("[%s][%d]ERROR: Function pointer is NULL!!!\n",__FUNCTION__,__LINE__);
1193 return FALSE;
1194 }
1195
1196 *bIsSignIn = FALSE;
1197
1198 switch(R2BYTE(BK_DAC(REG_DAC_HD_SEL), 9:8))
1199 {
1200 case DAC_DETECT_R_Channel:
1201 Channel_Select = BIT(4);
1202 break;
1203 case DAC_DETECT_G_Channel:
1204 Channel_Select = BIT(5);
1205 break;
1206 case DAC_DETECT_B_Channel:
1207 Channel_Select = BIT(6);
1208 break;
1209 default:
1210 Channel_Select = BIT(5);
1211 break;
1212 }
1213
1214 if(SelDAC == DAC_DETECT_HD)
1215 {
1216 switch(DetectType)
1217 {
1218 case DAC_DETECT_PLUGIN:
1219 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 12:12);
1220 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 14:14);
1221 W2BYTE(BK_DAC(REG_DAC_HD_DETECT_CTRL), (0xff01|Channel_Select), 15:0);
1222 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 13:11);
1223 break;
1224 case DAC_DETECT_PLUGOUT:
1225 W2BYTE(BK_DAC(REG_DAC_HD_DETECT_CTRL), (0x2402|Channel_Select), 15:0);
1226 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0xaa02, 15:0);
1227 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 13:11);
1228 break;
1229 default:
1230 printf("[%s][%d]Wrong DAC DetectType %d!!!\n",__FUNCTION__,__LINE__,DetectType);
1231 return FALSE;
1232 }
1233
1234 MsOS_DelayTask(DAC_DETECT_DELAY); //delay for voltage stable
1235 while((u16DetectCount > 0)&&(u16TimeoutCount < DAC_DETECT_TIMEOUT)) // check detect timeout
1236 {
1237 if((R2BYTE(BK_DAC(REG_DAC_HD_CMP_RESULT), 15:6) >> 6) <= DAC_DETECT_COUNT_HALF) // check detect result
1238 {
1239 u16DetectCount--; //detect dac is using
1240 DAC_DBG(printf("[%s][%d]==HD=DELETE=%d===\n",__FUNCTION__,__LINE__,u16DetectCount));
1241 if(u16DetectCount == 0)
1242 {
1243 *bIsSignIn = true;
1244 if(DetectType == DAC_DETECT_PLUGIN)
1245 {
1246 W2BYTE(BK_DAC(REG_DAC_HD_DETECT_CTRL), FALSE, 5:5);
1247 }
1248 }
1249 }
1250
1251 DAC_DBG(printf("[%s][%d]==HD=u16TimeoutCount=%d===\n",__FUNCTION__,__LINE__,u16TimeoutCount));
1252 u16TimeoutCount++;
1253 }
1254 }
1255 else if(SelDAC == DAC_DETECT_SD)
1256 {
1257 switch(DetectType)
1258 {
1259 case DAC_DETECT_PLUGIN:
1260 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 13:13);
1261 W2BYTE(BK_DAC(REG_DAC_LEVEL_CTRL), TRUE, 15:15);
1262 W2BYTE(BK_DAC(REG_DAC_SD_DETECT_CTRL), 0xff11, 15:0);
1263 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 10:8);
1264 break;
1265 case DAC_DETECT_PLUGOUT:
1266 W2BYTE(BK_DAC(REG_DAC_SD_DETECT_CTRL), 0x0b12, 15:0);
1267 W2BYTE(BK_DAC(REG_DAC_Delay_Sel), 0xaa02, 15:0);
1268 W2BYTE(BK_DAC(REG_DAC_GCR_LEVEL_CTRL), 0x0000, 10:8);
1269 break;
1270 default:
1271 printf("[%s][%d]Wrong DAC DetectType %d!!!\n",__FUNCTION__,__LINE__,DetectType);
1272 return FALSE;
1273 }
1274
1275 MsOS_DelayTask(DAC_DETECT_DELAY); //delay for voltage stable
1276 while((u16DetectCount > 0)&&(u16TimeoutCount < DAC_DETECT_TIMEOUT)) // check detect timeout
1277 {
1278 if((R2BYTE(BK_DAC(REG_DAC_SD_CMP_RESULT), 15:6) >> 6) <= DAC_DETECT_COUNT_HALF) // check detect result
1279 {
1280 u16DetectCount--; //detect dac is using
1281 DAC_DBG(printf("[%s][%d]==SD=DELETE=%d===\n",__FUNCTION__,__LINE__,u16DetectCount));
1282 if(u16DetectCount == 0)
1283 {
1284 *bIsSignIn = true;
1285 if(DetectType == DAC_DETECT_PLUGIN)
1286 {
1287 W2BYTE(BK_DAC(REG_DAC_SD_DETECT_CTRL), FALSE, 4:4);
1288 }
1289 }
1290 }
1291
1292 DAC_DBG(printf("[%s][%d]==SD=u16TimeoutCount=%d===\n",__FUNCTION__,__LINE__,u16TimeoutCount));
1293 u16TimeoutCount++;
1294 }
1295 }
1296 else
1297 {
1298 printf("[%s][%d]Wrong DAC Type %d!!!\n",__FUNCTION__,__LINE__,SelDAC);
1299 return FALSE;
1300 }
1301
1302 return TRUE;
1303 }
1304 #ifdef UFO_XC_GETOUTPUTINTELACETIMING
1305 //----------------------------------------------------------------
1306 // Hal_DAC_GetOutputInterlaceTiming
1307 // @return: TRUE is interlace or not
1308 //----------------------------------------------------------------
Hal_DAC_GetOutputInterlaceTiming(void)1309 MS_BOOL Hal_DAC_GetOutputInterlaceTiming(void)
1310 {
1311 MS_U8 u8Ret = 0;
1312 u8Ret = R2BYTE(DAC_SC_OUTPUT_INTERLACE, 1:1);
1313 if(u8Ret == 0x02)
1314 {
1315 return TRUE;
1316 }
1317 else
1318 {
1319 return FALSE;
1320 }
1321 }
1322 #endif
1323 //----------------------------------------------------------------
1324 // Hal_DAC_EnableHotPlugDetectISR - Enable DAC HotPlug detect ISR
1325 // @return: TRUE is working successful
1326 //----------------------------------------------------------------
Hal_DAC_EnableHotPlugDetectISR(MS_BOOL bEnabled)1327 MS_BOOL Hal_DAC_EnableHotPlugDetectISR(MS_BOOL bEnabled)
1328 {
1329 if(bDacIRQInit == bEnabled)
1330 {
1331 return TRUE;
1332 }
1333
1334 if(bEnabled)
1335 {
1336 _HAL_DAC_InitHpdInt();
1337 bDacIRQInit = TRUE;
1338 }
1339 else
1340 {
1341 MsOS_DisableInterrupt(E_INT_IRQ_IDAC_PLUG_DET);
1342 MsOS_DetachInterrupt(E_INT_IRQ_IDAC_PLUG_DET);
1343 bDacIRQInit = FALSE;
1344 }
1345
1346 return TRUE;
1347 }
1348
1349 //----------------------------------------------------------------
1350 // Hal_DAC_DumpTable - Dump DAC tables
1351 // @param: pDACTable: pointer to DAC table
1352 // @param: u8DACtype: DAC table type
1353 //----------------------------------------------------------------
Hal_DAC_DumpTable(MS_U8 * pDACTable,MS_U8 u8DACtype)1354 void Hal_DAC_DumpTable(MS_U8 *pDACTable, MS_U8 u8DACtype)
1355 {
1356 MS_U8 u8DacTab[DAC_TAB_MAX_SIZE];
1357 MS_U32 u32DacTabsize = 0;
1358 DAC_TAB_INFO DacTbl;
1359
1360 DacTbl = DACPANEL_MainTbl[_geDACPanel_index];
1361
1362 MS_BOOL bForce8BitMode = FALSE;
1363 // we only support max 6G bandwidth, 4K2K 50/60 must force 8 bit mode(more than 8 bit will cause over 6G if not 420 timing))
1364 // This solution need sync with HDMI setting
1365 if ((_geDACPanel_index == DAC_PANEL_3840x2160P_50) ||
1366 (_geDACPanel_index == DAC_PANEL_3840x2160P_60) ||
1367 (_geDACPanel_index == DAC_PANEL_4096x2160P_50) ||
1368 (_geDACPanel_index == DAC_PANEL_4096x2160P_60))
1369 {
1370 bForce8BitMode = TRUE;
1371 }
1372
1373 switch(u8DACtype)
1374 {
1375 case DAC_TABTYPE_INIT:
1376 pDACTable = DacTbl.pDacINITTab;
1377 break;
1378 case DAC_TABTYPE_INIT_GPIO:
1379 pDACTable = DacTbl.pDacINIT_GPIOTab;
1380 break;
1381 case DAC_TABTYPE_INIT_SC:
1382 pDACTable = DacTbl.pDacINIT_SCTab;
1383 break;
1384 case DAC_TABTYPE_INIT_MOD:
1385 pDACTable = DacTbl.pDacINIT_MODTab;
1386 break;
1387 case DAC_TABTYPE_INIT_HDGEN:
1388 pDACTable = DacTbl.pDacINIT_HDGENTab;
1389 break;
1390 case DAC_TABTYPE_INIT_HDMITX_8BIT:
1391 pDACTable = DacTbl.pDacINIT_HDMITX_8BITTab;
1392 break;
1393 case DAC_TABTYPE_INIT_HDMITX_10BIT:
1394 if(TRUE == bForce8BitMode)
1395 {
1396 pDACTable = DacTbl.pDacINIT_HDMITX_8BITTab;
1397 }
1398 else
1399 {
1400 pDACTable = DacTbl.pDacINIT_HDMITX_10BITTab;
1401 }
1402 break;
1403 case DAC_TABTYPE_INIT_HDMITX_12BIT:
1404 if(TRUE == bForce8BitMode)
1405 {
1406 pDACTable = DacTbl.pDacINIT_HDMITX_8BITTab;
1407 }
1408 else
1409 {
1410 pDACTable = DacTbl.pDacINIT_HDMITX_12BITTab;
1411 }
1412 break;
1413 case DAC_TABTYPE_INIT_HDMITX_16BIT:
1414 if(TRUE == bForce8BitMode)
1415 {
1416 pDACTable = DacTbl.pDacINIT_HDMITX_8BITTab;
1417 }
1418 else
1419 {
1420 pDACTable = DacTbl.pDacINIT_HDMITX_16BITTab;
1421 }
1422 break;
1423 case DAC_TABTYPE_INIT_HDMITX_8BIT_Divider:
1424 pDACTable = DacTbl.pDacINIT_HDMITX_8BIT_DividerTab;
1425 break;
1426 case DAC_TABTYPE_INIT_HDMITX_10BIT_Divider:
1427 if(TRUE == bForce8BitMode)
1428 {
1429 pDACTable = DacTbl.pDacINIT_HDMITX_8BIT_DividerTab;
1430 }
1431 else
1432 {
1433 pDACTable = DacTbl.pDacINIT_HDMITX_10BIT_DividerTab;
1434 }
1435 break;
1436 case DAC_TABTYPE_INIT_HDMITX_12BIT_Divider:
1437 if(TRUE == bForce8BitMode)
1438 {
1439 pDACTable = DacTbl.pDacINIT_HDMITX_8BIT_DividerTab;
1440 }
1441 else
1442 {
1443 pDACTable = DacTbl.pDacINIT_HDMITX_12BIT_DividerTab;
1444 }
1445 break;
1446 case DAC_TABTYPE_INIT_HDMITX_16BIT_Divider:
1447 if(TRUE == bForce8BitMode)
1448 {
1449 pDACTable = DacTbl.pDacINIT_HDMITX_8BIT_DividerTab;
1450 }
1451 else
1452 {
1453 pDACTable = DacTbl.pDacINIT_HDMITX_16BIT_DividerTab;
1454 }
1455 break;
1456 case DAC_TABTYPE_SC1_INIT:
1457 pDACTable = DacTbl.pDacSC1_INITTab;
1458 break;
1459 case DAC_TABTYPE_SC1_INIT_SC:
1460 pDACTable = DacTbl.pDacSC1_INIT_SCTab;
1461 break;
1462 default:
1463 DAC_DBG(printf( "GetTable:unknown Tab type> \n"));
1464 return;
1465 }
1466
1467 _Hal_DAC_GetTabSize(pDACTable, u8DACtype, &u32DacTabsize);
1468 memcpy(u8DacTab, pDACTable, u32DacTabsize);
1469
1470 switch(u8DACtype)
1471 {
1472 case DAC_TABTYPE_INIT:
1473 case DAC_TABTYPE_INIT_GPIO:
1474 case DAC_TABTYPE_SC1_INIT:
1475 _Hal_DAC_DumpGENRegTab(u8DacTab);
1476 break;
1477 case DAC_TABTYPE_INIT_SC:
1478 _Hal_DAC_DumpSCRegTab(u8DacTab);
1479 break;
1480 case DAC_TABTYPE_INIT_MOD:
1481 _Hal_DAC_DumpMODRegTab(u8DacTab);
1482 break;
1483 case DAC_TABTYPE_INIT_HDGEN:
1484 _Hal_DAC_DumpHDGENRegTab(u8DacTab);
1485 break;
1486 case DAC_TABTYPE_INIT_HDMITX_8BIT:
1487 _Hal_DAC_DumpHDMITxRegTab(u8DacTab);
1488 break;
1489 case DAC_TABTYPE_INIT_HDMITX_10BIT:
1490 _Hal_DAC_DumpHDMITxRegTab(u8DacTab);
1491 break;
1492 case DAC_TABTYPE_INIT_HDMITX_12BIT:
1493 _Hal_DAC_DumpHDMITxRegTab(u8DacTab);
1494 break;
1495 case DAC_TABTYPE_INIT_HDMITX_8BIT_Divider:
1496 _Hal_DAC_DumpHDMITxDivRegTab(u8DacTab);
1497 break;
1498 case DAC_TABTYPE_INIT_HDMITX_10BIT_Divider:
1499 _Hal_DAC_DumpHDMITxDivRegTab(u8DacTab);
1500 break;
1501 case DAC_TABTYPE_INIT_HDMITX_12BIT_Divider:
1502 _Hal_DAC_DumpHDMITxDivRegTab(u8DacTab);
1503 break;
1504 case DAC_TABTYPE_SC1_INIT_SC:
1505 _Hal_DAC_DumpSCRegTab(u8DacTab);
1506 break;
1507 default:
1508 DAC_DBG(printf( "GetTable:unknown Tab type> \n"));
1509 break;
1510 }
1511
1512 }
1513
1514
Hal_DAC_SetDataReverse(MS_BOOL bTrue)1515 void Hal_DAC_SetDataReverse(MS_BOOL bTrue)
1516 {
1517 W2BYTE(BK_DAC(REG_DAC_BIAS_CUR_CTRL), bTrue, 0:0);
1518 }
1519
Hal_DAC_EnableChannelBuf(MS_BOOL bTrue)1520 void Hal_DAC_EnableChannelBuf(MS_BOOL bTrue)
1521 {
1522 W2BYTE(BK_DAC(REG_DAC_CHN_BUF_EN), bTrue, 0:0);
1523 W2BYTE(BK_DAC(REG_DAC_CHN_BUF_EN), bTrue, 1:1);
1524 W2BYTE(BK_DAC(REG_DAC_CHN_BUF_EN), bTrue, 2:2);
1525 W2BYTE(BK_DAC(REG_DAC_CHN_BUF_EN), bTrue, 3:3);
1526 }
1527
Hal_HDGEN_SetWSSOnOff(MS_BOOL bEnable)1528 void Hal_HDGEN_SetWSSOnOff(MS_BOOL bEnable)
1529 {
1530 //Not support
1531 UNUSED(bEnable);
1532 }
1533
Hal_HDGEN_GetWSSStatus(void)1534 MS_BOOL Hal_HDGEN_GetWSSStatus(void)
1535 {
1536 //Not support
1537 return TRUE;
1538 }
Hal_HDGEN_ResetWSSData(void)1539 void Hal_HDGEN_ResetWSSData(void)
1540 {
1541 //Not support
1542 }
1543
1544 ////////////////////////////////////////////////////////////////////////////////
1545 /// @brief \b Function \b Name: Hal_DAC_Set_WSS_data()
1546 /// @brief \b Function \b Description : Set the WSS data of YPbPr
1547 ///
1548 /// @param <IN> \b bEn : Enable, Disable
1549 /// @param <IN> \b u8WSSData : The WSS data
1550 /// @param <OUT> \b None :
1551 /// @param <RET> \b None :
1552 /// @param <GLOBAL> \b None :
1553 ////////////////////////////////////////////////////////////////////////////////
Hal_HDGEN_Set_WSS_data(MS_BOOL ben,EN_OUTPUT_VIDEO_TIMING_TYPE eVideo_Timing,MS_U16 u16wssdata)1554 MS_BOOL Hal_HDGEN_Set_WSS_data(MS_BOOL ben, EN_OUTPUT_VIDEO_TIMING_TYPE eVideo_Timing, MS_U16 u16wssdata)
1555 {
1556 //Not support
1557 UNUSED(ben);
1558 UNUSED(eVideo_Timing);
1559 UNUSED(u16wssdata);
1560 return TRUE;
1561 }
1562
Hal_HDGEN_Get_WSS_data(void)1563 MS_U16 Hal_HDGEN_Get_WSS_data(void)
1564 {
1565 //Not support
1566 return 0;
1567 }
1568
1569 ////////////////////////////////////////////////////////////////////////////////
1570 /// @brief \b Function \b Name: Hal_VE_set_wss525_data()
1571 /// @brief \b Function \b Description : Set the WSS data of video encoder for 525i System
1572 ///
1573 /// @param <IN> \b bEn : Enable, Disable
1574 /// @param <IN> \b u8WSSData : The WSS data
1575 /// @param <OUT> \b None :
1576 /// @param <RET> \b None :
1577 /// @param <GLOBAL> \b None :
1578 ////////////////////////////////////////////////////////////////////////////////
Hal_HDGEN_Set_WSS525_A_data(MS_BOOL ben,EN_OUTPUT_VIDEO_TIMING_TYPE eVideo_Timing,MS_U32 u32wssdata)1579 MS_BOOL Hal_HDGEN_Set_WSS525_A_data(MS_BOOL ben, EN_OUTPUT_VIDEO_TIMING_TYPE eVideo_Timing, MS_U32 u32wssdata)
1580 {
1581 //Not support
1582 UNUSED(ben);
1583 UNUSED(eVideo_Timing);
1584 UNUSED(u32wssdata);
1585 return TRUE;
1586 }
1587
Hal_HDGEN_Get_WSS525_A_data(void)1588 MS_U32 Hal_HDGEN_Get_WSS525_A_data(void)
1589 {
1590 //Not support
1591 return 0;
1592 }
1593
Hal_HDGEN_EnableICT(MS_BOOL bEnable)1594 MS_BOOL Hal_HDGEN_EnableICT(MS_BOOL bEnable)
1595 {
1596 //Not support
1597 UNUSED(bEnable);
1598 return TRUE;
1599 }
1600
1601
1602 //----------------------------------------------------------------
1603 // DAC - set VGA Hsync Vsync
1604 // @return none
1605 //----------------------------------------------------------------
Hal_DAC_SetVGAHsyncVsync(MS_BOOL bEnable)1606 void Hal_DAC_SetVGAHsyncVsync(MS_BOOL bEnable)
1607 {
1608 if (bEnable)
1609 {
1610 W1BYTE(L_BK_CHIPTOP_TOP(REG_HSYNC_VSYNC_EN), 0x03, 1:0); //Enable Hsync Vsync
1611 W2BYTE_TAB(HDGEN_BK_SELECT, 0x1, 0x1);
1612 W1BYTE_TAB(BK_HDGEN(0x7C), 0x1, 0x1); //select source of oversample filter : #1: vga out
1613 }
1614 else
1615 {
1616 W1BYTE(L_BK_CHIPTOP_TOP(REG_HSYNC_VSYNC_EN), 0x00, 1:0); //Disable Hsync Vsync
1617 W2BYTE_TAB(HDGEN_BK_SELECT, 0x1, 0x1);
1618 W1BYTE_TAB(BK_HDGEN(0x7C), 0x0, 0x1); //select source of oversample filter : #0: hdgen out
1619 }
1620 }
1621
1622