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MStar hereby reserves the 91*53ee8cc1Swenshuai.xi // rights to any and all damages, losses, costs and expenses resulting therefrom. 92*53ee8cc1Swenshuai.xi // 93*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////// 94*53ee8cc1Swenshuai.xi 95*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////////////////////////// 96*53ee8cc1Swenshuai.xi // file halCMDQ.h 97*53ee8cc1Swenshuai.xi // @brief CMDQ HAL 98*53ee8cc1Swenshuai.xi // @author MStar Semiconductor,Inc. 99*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////////////////////////////////////////// 100*53ee8cc1Swenshuai.xi #ifndef __HAL_CMDQ_H__ 101*53ee8cc1Swenshuai.xi #define __HAL_CMDQ_H__ 102*53ee8cc1Swenshuai.xi 103*53ee8cc1Swenshuai.xi #include "regCMDQ.h" 104*53ee8cc1Swenshuai.xi 105*53ee8cc1Swenshuai.xi // Trigger Bus Defination 106*53ee8cc1Swenshuai.xi #define HAL_GE_GE2CMDQ_TRI 0x0000 107*53ee8cc1Swenshuai.xi #define HAL_BDMA_INT_BDMA_0 0x0001 108*53ee8cc1Swenshuai.xi #define HAL_BDMA_INT_BDMA_1 0x0002 109*53ee8cc1Swenshuai.xi #define HAL_GPU_GPU2CMDQ_TRIG 0x0003 110*53ee8cc1Swenshuai.xi #define HAL_GOPG0_GOP_CMDQ_INT_0 0x0004 111*53ee8cc1Swenshuai.xi #define HAL_GOPG1_GOP_CMDQ_INT_1 0x0005 112*53ee8cc1Swenshuai.xi #define HAL_GOPG2_GOP_CMDQ_INT_2 0x0006 113*53ee8cc1Swenshuai.xi #define HAL_GOPG3_GOP_CMDQ_INT_3 0x0007 114*53ee8cc1Swenshuai.xi #define HAL_SCALAR_SC2CMDQ_TRIG_0 0x0008 115*53ee8cc1Swenshuai.xi #define HAL_SCALAR_SC2CMDQ_TRIG_1 0x0009 116*53ee8cc1Swenshuai.xi #define HAL_SCALAR_SC2CMDQ_TRIG_2 0x000B 117*53ee8cc1Swenshuai.xi #define HAL_SCALAR_SC2CMDQ_TRIG_3 0xFFFF // not support 118*53ee8cc1Swenshuai.xi #define HAL_AESDMA_CMDQDMA_FINISHED 0x000C 119*53ee8cc1Swenshuai.xi #define HAL_AESDMA_CMDQDMA_FINISHED_2 0x000F 120*53ee8cc1Swenshuai.xi #define HAL_VOP_DCM2GOP_VDE 0x000D 121*53ee8cc1Swenshuai.xi #define HAL_VOP_DCS2GOP_VDE 0x000E 122*53ee8cc1Swenshuai.xi #define HAL_XC_DIP_CMDQ_INT 0x000A 123*53ee8cc1Swenshuai.xi 124*53ee8cc1Swenshuai.xi 125*53ee8cc1Swenshuai.xi #define BUS_SHIFT 4 126*53ee8cc1Swenshuai.xi 127*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 128*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 129*53ee8cc1Swenshuai.xi // Macro of bit operations 130*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------- 131*53ee8cc1Swenshuai.xi #define HAS_FLAG(flag, bit) ((flag) & (bit)) 132*53ee8cc1Swenshuai.xi #define SET_FLAG(flag, bit) ((flag)|= (bit)) 133*53ee8cc1Swenshuai.xi #define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) 134*53ee8cc1Swenshuai.xi #define SET_FLAG1(flag, bit) ((flag)| (bit)) 135*53ee8cc1Swenshuai.xi #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) 136*53ee8cc1Swenshuai.xi //////////////////////////////////////////////// 137*53ee8cc1Swenshuai.xi // HAL API 138*53ee8cc1Swenshuai.xi //////////////////////////////////////////////// 139*53ee8cc1Swenshuai.xi void HAL_CMDQ_SetBank(MS_U32 hnd, MS_VIRT u32BankAddr); 140*53ee8cc1Swenshuai.xi void HAL_CMDQ_Enable(MS_U32 hnd); 141*53ee8cc1Swenshuai.xi void HAL_CMDQ_Stop(MS_U32 hnd); 142*53ee8cc1Swenshuai.xi void HAL_CMDQ_Reset(MS_U32 hnd); 143*53ee8cc1Swenshuai.xi void HAL_CMDQ_Set_Miu_Length(MS_U32 hnd, MS_U32 value); 144*53ee8cc1Swenshuai.xi void HAL_CMDQ_Set_Miu_Request(MS_U32 hnd, MS_U32 value); 145*53ee8cc1Swenshuai.xi MS_BOOL HAL_CMDQ_Set_Mode(MS_U32 hnd, MS_U32 ModeSel); 146*53ee8cc1Swenshuai.xi void HAL_CMDQ_Set_Start_Pointer(MS_U32 hnd, MS_PHY StartAddr); 147*53ee8cc1Swenshuai.xi void HAL_CMDQ_Set_End_Pointer(MS_U32 hnd, MS_PHY EndAddr); 148*53ee8cc1Swenshuai.xi void HAL_CMDQ_Set_Offset_Pointer(MS_U32 hnd, MS_U32 OffsetAddr); 149*53ee8cc1Swenshuai.xi void HAL_CMDQ_Set_Timer(MS_U32 hnd, MS_U32 time); 150*53ee8cc1Swenshuai.xi void HAL_CMDQ_Set_Ratio(MS_U32 hnd, MS_U32 ratio); 151*53ee8cc1Swenshuai.xi void HAL_CMDQ_Reset_Soft_Interrupt(MS_U32 hnd); 152*53ee8cc1Swenshuai.xi void HAL_CMDQ_Reset_Start_Pointer_bit(MS_U32 hnd); 153*53ee8cc1Swenshuai.xi void HAL_CMDQ_Read_Soft_Interrupt(MS_U32 hnd); 154*53ee8cc1Swenshuai.xi void HAL_CMDQ_Read_Dec_Done(MS_U32 hnd); 155*53ee8cc1Swenshuai.xi void HAL_CMDQ_Start(MS_U32 hnd); 156*53ee8cc1Swenshuai.xi MS_U32 HAL_CMDQ_Read_Dummy_Register(MS_U32 hnd); 157*53ee8cc1Swenshuai.xi void HAL_CMDQ_Write_Dummy_Register(MS_U32 hnd, MS_U32 DummyValue); 158*53ee8cc1Swenshuai.xi void HAL_CMDQ_Set_MIU_SELECT(MS_U32 hnd, MS_U32 miu_select); 159*53ee8cc1Swenshuai.xi MS_U32 HAL_CMDQ_Read_Start_Pointer(MS_U32 hnd); 160*53ee8cc1Swenshuai.xi MS_U32 HAL_CMDQ_Read_End_Pointer(MS_U32 hnd); 161*53ee8cc1Swenshuai.xi void HAL_CMDQ_Write_Dummy_Register_release_polling(MS_U32 hnd, MS_U32 Write_bit); 162*53ee8cc1Swenshuai.xi MS_U32 HAL_CMDQ_Error_Command(MS_U32 hnd, MS_U32 select_bit); 163*53ee8cc1Swenshuai.xi void HAL_CMDQ_Write_Pointer(MS_U32 hnd, MS_PHY Write_value); 164*53ee8cc1Swenshuai.xi MS_U32 HAL_CMDQ_Read_Pointer(MS_U32 hnd); 165*53ee8cc1Swenshuai.xi MS_U32 HAL_CMDQ_Get_Write_Pointer(MS_U32 hnd); 166*53ee8cc1Swenshuai.xi 167*53ee8cc1Swenshuai.xi 168*53ee8cc1Swenshuai.xi void HAL_CMDQ_Trigger_Wait(MS_U32 hnd, MS_U32 sigbits); 169*53ee8cc1Swenshuai.xi void HAL_CMDQ_Skip_Commands(MS_U32 hnd, MS_U32 skipbits); 170*53ee8cc1Swenshuai.xi MS_U32 HAL_CMDQ_Read_Misc_Status(MS_U32 hnd); 171*53ee8cc1Swenshuai.xi void HAL_CMDQ_Set_Debug_Step_Mode(MS_U32 hnd, MS_BOOL on); 172*53ee8cc1Swenshuai.xi MS_U32 HAL_CMDQ_Get_Debug_Step_Mode(MS_U32 hnd); 173*53ee8cc1Swenshuai.xi void HAL_CMDQ_Debug_One_Step(MS_U32 hnd); 174*53ee8cc1Swenshuai.xi void HAL_CMDQ_Reset2(MS_U32 hnd, MS_BOOL high); 175*53ee8cc1Swenshuai.xi 176*53ee8cc1Swenshuai.xi 177*53ee8cc1Swenshuai.xi 178*53ee8cc1Swenshuai.xi #endif // #ifndef _CMDQ_REG_MCU_H_ 179