xref: /utopia/UTPA2-700.0.x/modules/cmdq/hal/maldives/cmdq/halCMDQ.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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93 ////////////////////////////////////////////////////////////////////////////////
94 
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 // file   halCMDQ.c
97 // @brief  CMDQ HAL
98 // @author MStar Semiconductor,Inc.
99 ////////////////////////////////////////////////////////////////////////////////////////////////////
100 
101 #include "MsCommon.h"
102 #include "regCMDQ.h"
103 #include "halCMDQ.h"
104 
105 //--------------------------------------------------------------------------------------------------
106 //  Driver Compiler Option
107 //--------------------------------------------------------------------------------------------------
108 
109 //--------------------------------------------------------------------------------------------------
110 //  TSP Hardware Abstraction Layer
111 //--------------------------------------------------------------------------------------------------
112 static MS_U32               _u32RegBase = NULL;
113 static REG_CMDQCtrl        *_CMDQCtrl = (REG_CMDQCtrl*)REG_CMDQCTRL_BASE;
114 #define REG32_W(reg, value)     do {    \
115                                     (reg)->H = ((value) >> 16); \
116                                     (reg)->L = ((value) & 0x0000FFFF);  \
117                                 } while(0)
118 
119 //--------------------------------------------------------------------------------------------------
120 //  Macro of bit operations
121 //--------------------------------------------------------------------------------------------------
122 
123 //---------------------------------------------------------------------------
124 ///concatenate (reg)->H and (reg)->L
125 /// @param  reg                     \b IN: concatenate data
126 //---------------------------------------------------------------------------
_CMDQ_REG32_R(REG32 * reg)127 MS_U32 _CMDQ_REG32_R(REG32 *reg)
128 {
129     MS_U32     value;
130     value = (reg)->H << 16;
131     value |= (reg)->L;
132     return value;
133 }
134 
135 //--------------------------------------------------------------------------------------------------
136 //  Inline Function
137 //--------------------------------------------------------------------------------------------------
138 
HAL_CMDQ_SetBank(MS_U32 u32BankAddr)139 void HAL_CMDQ_SetBank(MS_U32 u32BankAddr)
140 {
141     _u32RegBase = u32BankAddr;
142     _CMDQCtrl = (REG_CMDQCtrl*)(_u32RegBase + REG_CMDQCTRL_BASE);
143 
144     printf("\033[35m[HAL_CMDQ_SetBank] Set Verify Code Setting...\033[m\n");
145     //*(MS_U32 *)(_u32RegBase + 0x0025C) = 0x0001;  // 0x2 0025C, open this for using write_mask(SN only), this is a RIU setting, set to 1 for enable 16-bit mask/16-bit data, set to 0 for 32-bit data only(mali will failed if set to 1)
146     //*(MS_U32 *)(_u32RegBase + 0x46A88) = 0x0080;  // 0x2 46A88
147     *(MS_U32 *)(_u32RegBase + 0x47204UL) = 0x0000;  // 0x2 47204, Enable CMDQ wirte RIU  0x247204 >> 1 ==> 0x123902
148 	                                              // bank 0x1239 h0001 set bit_12 to be 0(cmdq host access RIU will be secure, so that cmdq can access secure/non-secure bank)
149 }
150 
151 //---------------------------------------------------------------------------
152 ///set the element of _CMDQCtrl
153 ///  .CMDQ_Enable
154 ///  .CMDQ_Length_ReadMode
155 ///  .CMDQ_Mask_Setting
156 //---------------------------------------------------------------------------
HAL_CMDQ_Enable()157 void HAL_CMDQ_Enable()
158 {
159     REG32_W((&_CMDQCtrl[0].CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Enable) | (CMDQ_CMDQ_EN));
160     REG32_W((&_CMDQCtrl[0].CMDQ_Length_ReadMode), _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Length_ReadMode) | (CMDQ_REQ_LEN_MASK) | (CMDQ_REQ_TH_MASK) | (REQ_DMA_BURST_MODE));
161     REG32_W((&_CMDQCtrl[0].CMDQ_Mask_Setting), _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Mask_Setting) | (CMDQ_MASK_BIT));
162 
163 	// do not jump wait/polling_eq/polling_neq command while timer reaches, very important, set to 0
164 	REG32_W((&_CMDQCtrl[0].CMDQ_Tout_Base_Amount) , _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Tout_Base_Amount)&(TOUT_DO_NOT_JUMP));
165 }
166 
HAL_CMDQ_Stop(void)167 void HAL_CMDQ_Stop(void)
168 {
169     REG32_W((&_CMDQCtrl[0].CMDQ_Enable), _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Enable) | (CMDQ_CMDQ_DISEN));
170 }
171 
172 //---------------------------------------------------------------------------
173 ///set the element of _CMDQCtrl
174 ///  .CMDQ_En_Clk_Miu
175 //---------------------------------------------------------------------------
HAL_CMDQ_Reset(void)176 void HAL_CMDQ_Reset(void)
177 {
178     REG32_W((&_CMDQCtrl[0].CMDQ_En_Clk_Miu), _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_En_Clk_Miu) | (CMDQ_SOFT_RSTZ));
179 }
180 
HAL_CMDQ_Set_Mode(int ModeSel)181 MS_BOOL HAL_CMDQ_Set_Mode(int ModeSel)
182 {
183     if(ModeSel == 1)
184     {
185         REG32_W((&_CMDQCtrl[0].CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Trig_Mode) | (CMDQ_CMD_BUF_DIRECT_MODE));
186         return TRUE;
187     }
188     else if(ModeSel == 0)
189     {
190         REG32_W((&_CMDQCtrl[0].CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Trig_Mode) | (CMDQ_CMD_INCREAMENT_MODE));
191         return TRUE;
192     }
193 	else if(ModeSel == 4)
194 	{
195         REG32_W((&_CMDQCtrl[0].CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Trig_Mode) | (CMDQ_RING_BUFFER_MODE));
196         return TRUE;
197 	}
198     else
199     {
200         printf("\033[35mFunction = %s, Line = %d, HAL_CMDQ_Set_Mode ERROR!! Unknown mode, ModeSel = %d\033[m\n", __PRETTY_FUNCTION__, __LINE__, ModeSel); // joe.liu
201         return FALSE;
202     }
203 }
204 
HAL_CMDQ_Set_Start_Pointer(MS_U32 StartAddr)205 void HAL_CMDQ_Set_Start_Pointer(MS_U32 StartAddr)
206 {
207     REG32_W((&_CMDQCtrl[0].CMDQ_Cmd_St_Ptr), StartAddr);
208     printf("\033[35mFunction = %s, Line = %d, set SATRT_ADDR: 0x%X\033[m\n", __PRETTY_FUNCTION__, __LINE__, (unsigned int)StartAddr); // joe.liu
209 }
210 
HAL_CMDQ_Set_End_Pointer(MS_U32 EndAddr)211 void HAL_CMDQ_Set_End_Pointer(MS_U32 EndAddr)
212 {
213     REG32_W((&_CMDQCtrl[0].CMDQ_Cmd_End_Ptr), EndAddr);
214 	printf("\033[35mFunction = %s, Line = %d, set END_ADDR: 0x%X\033[m\n", __PRETTY_FUNCTION__, __LINE__, (unsigned int)EndAddr); // joe.liu
215 }
216 
HAL_CMDQ_Set_Offset_Pointer(MS_U32 OffsetAddr)217 void HAL_CMDQ_Set_Offset_Pointer(MS_U32 OffsetAddr)
218 {
219     REG32_W((&_CMDQCtrl[0].CMDQ_Cmd_End_Ptr) , OffsetAddr);
220 }
221 
HAL_CMDQ_Set_Timer(MS_U32 time)222 void HAL_CMDQ_Set_Timer(MS_U32 time)
223 {
224     REG32_W((&_CMDQCtrl[0].CMDQ_Poll_Ratio_Wait_Time) , _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Poll_Ratio_Wait_Time) | time);
225 	printf("\033[35mFunction = %s, Line = %d, Set Timer: 0x%X\033[m\n", __PRETTY_FUNCTION__, __LINE__, (unsigned int)time); // joe.liu
226 }
227 
HAL_CMDQ_Set_Ratio(MS_U32 Ratio)228 void HAL_CMDQ_Set_Ratio(MS_U32 Ratio)
229 {
230     REG32_W((&_CMDQCtrl[0].CMDQ_Poll_Ratio_Wait_Time) ,_CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Poll_Ratio_Wait_Time) | Ratio);
231 	printf("\033[35mFunction = %s, Line = %d, Set Ratio: 0x%X\033[m\n", __PRETTY_FUNCTION__, __LINE__, (unsigned int)Ratio); // joe.liu
232 }
233 
HAL_CMDQ_Reset_Soft_Interrupt(void)234 void HAL_CMDQ_Reset_Soft_Interrupt(void)
235 {
236     REG32_W((&_CMDQCtrl[0].CMDQ_Sw_Trig_Cap_Sel_Irq_Clr) , _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Sw_Trig_Cap_Sel_Irq_Clr)|(CMDQ_SOFT_INTER_CLR));
237 }
238 
HAL_CMDQ_Reset_Start_Pointer_bit(void)239 void HAL_CMDQ_Reset_Start_Pointer_bit(void)
240 {
241     REG32_W((&_CMDQCtrl[0].CMDQ_Trig_Mode) , _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Trig_Mode)|(CMDQ_RST_CMD_ST_PTR_TRIG));
242 }
243 
HAL_CMDQ_Read_Soft_Interrupt(void)244 void HAL_CMDQ_Read_Soft_Interrupt(void)
245 {
246     _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Raw_Irq_Final_Irq);
247 }
248 
HAL_CMDQ_Read_Dec_Done(void)249 void HAL_CMDQ_Read_Dec_Done(void)
250 {
251     _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Raw_Irq_Final_Irq);
252 }
253 
254 //---------------------------------------------------------------------------
255 ///Trigger for update start pointer and end pointer
256 //---------------------------------------------------------------------------
HAL_CMDQ_Start(void)257 void HAL_CMDQ_Start(void)
258 {
259     REG32_W((&_CMDQCtrl[0].CMDQ_Trig_Mode), _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Trig_Mode) | (CMDQ_MOV_CMD_PTR));
260 }
261 
HAL_CMDQ_Read_Dummy_Register(void)262 MS_U32 HAL_CMDQ_Read_Dummy_Register(void)
263 {
264     MS_U32 reg_value=0;
265     reg_value= _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_dummy);
266     return reg_value;
267 }
268 
HAL_CMDQ_Write_Dummy_Register(MS_U32 DummyValue)269 void HAL_CMDQ_Write_Dummy_Register(MS_U32 DummyValue)
270 {
271     REG32_W((&_CMDQCtrl[0].CMDQ_dummy), (_CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_dummy) & (CMDQ__DUMMY_WRITE_ZERO)) | DummyValue);
272 }
273 
HAL_CMDQ_Set_MIU_SELECT(MS_U32 miu_select)274 void HAL_CMDQ_Set_MIU_SELECT(MS_U32 miu_select)
275 {
276 	if(miu_select == 1)
277 	{
278 		printf("\033[35mFunction = %s, Line = %d, set miu_1\033[m\n", __PRETTY_FUNCTION__, __LINE__);
279 		REG32_W((&_CMDQCtrl[0].CMDQ_Length_ReadMode) , (_CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Length_ReadMode) | CMDQ_MIU_SELECT_MIU1));
280 	}
281 	else
282 	{
283 		printf("\033[35mFunction = %s, Line = %d, set miu_0\033[m\n", __PRETTY_FUNCTION__, __LINE__);
284 		REG32_W((&_CMDQCtrl[0].CMDQ_Length_ReadMode) , (_CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Length_ReadMode) & ~(CMDQ_MIU_SELECT_MIU1)));
285 	}
286 }
287 
HAL_CMDQ_Read_Start_Pointer(void)288 MS_U32 HAL_CMDQ_Read_Start_Pointer(void)
289 {
290     MS_U32 reg_value=0;
291     reg_value= _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Cmd_St_Ptr);
292     return reg_value;
293 }
294 
HAL_CMDQ_Read_End_Pointer(void)295 MS_U32 HAL_CMDQ_Read_End_Pointer(void)
296 {
297     MS_U32 reg_value = 0;
298     reg_value= _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Cmd_End_Ptr);
299     return reg_value;
300 }
301 
302 //---------------------------------------------------------------------------
303 ///Set Previous Dummy Register bit to be 1(which means this CAF is already write to DRAM)
304 //---------------------------------------------------------------------------
HAL_CMDQ_Write_Dummy_Register_release_polling(int Write_bit)305 void HAL_CMDQ_Write_Dummy_Register_release_polling(int Write_bit)
306 {
307     REG32_W((&_CMDQCtrl[0].CMDQ_dummy), SET_FLAG1(_CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_dummy), 0x0001 << Write_bit));
308 }
309 
HAL_CMDQ_Error_Command(MS_U32 select_bit)310 MS_U32 HAL_CMDQ_Error_Command(MS_U32 select_bit)
311 {
312     MS_U32 reg_value = 0;
313     REG32_W((&_CMDQCtrl[0].CMDQ_Cmd_Sel_Decode_State), select_bit);
314     reg_value = _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Dma_State_Rb_Cmd) & 0x0000ffff;
315     return reg_value;
316 }
317 
HAL_CMDQ_Write_Pointer(MS_U32 Write_value)318 void HAL_CMDQ_Write_Pointer(MS_U32 Write_value)
319 {
320     REG32_W((&_CMDQCtrl[0].CMDQ_Sw_Wr_Mi_Wadr), Write_value);
321 }
322 
323 //---------------------------------------------------------------------------
324 ///Set rd_mi_radr_trig to grab current read address pointer(rd_mi_radr will be store in CMDQ_Rd_Mi_Radr)
325 //---------------------------------------------------------------------------
HAL_CMDQ_Read_Pointer(void)326 MS_U32 HAL_CMDQ_Read_Pointer(void)
327 {
328     MS_U32 reg_value = 0;
329 	REG32_W((&_CMDQCtrl[0].CMDQ_Trig_Mode), _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Trig_Mode) | CMDQ_READ_TRIG);
330 	reg_value = _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Rd_Mi_Radr);
331 	return reg_value;
332 }
333 
334 //---------------------------------------------------------------------------
335 ///get the Write_Pointer(for multi-process, preventing write address is wrong(each process will start from Buffer_Start) ==> get current write_cmd ptr, next will write from here
336 //---------------------------------------------------------------------------
HAL_CMDQ_Get_Write_Pointer(void)337 MS_U32 HAL_CMDQ_Get_Write_Pointer(void)
338 {
339     MS_U32 reg_value = 0;
340 	reg_value = _CMDQ_REG32_R(&_CMDQCtrl[0].CMDQ_Sw_Wr_Mi_Wadr);
341 	return reg_value;
342 }
343 
344