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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 //////////////////////////////////////////////////////////////////////////////// 93 94 #ifndef _REGBDMA_H_ 95 #define _REGBDMA_H_ 96 97 //////////////////////////////////////////////////////////////////////////////// 98 // Header Files 99 //////////////////////////////////////////////////////////////////////////////// 100 101 //////////////////////////////////////////////////////////////////////////////// 102 // Define & data type 103 //////////////////////////////////////////////////////////////////////////////// 104 //v: value n: shift n bits 105 #define __BIT(x) ((MS_U8)(1UL << (x))) 106 #define __BIT0 __BIT(0UL) 107 #define __BIT1 __BIT(1UL) 108 #define __BIT2 __BIT(2UL) 109 #define __BIT3 __BIT(3UL) 110 #define __BIT4 __BIT(4UL) 111 #define __BIT5 __BIT(5UL) 112 #define __BIT6 __BIT(6UL) 113 #define __BIT7 __BIT(7UL) 114 115 #define BDMA_REG_BASE (0x0900UL) 116 #define BDMA_REG_CH0_BASE (BDMA_REG_BASE+0UL) 117 #define BDMA_CH_REG_OFFSET (0x20UL) 118 #define BDMA_SET_CH0_REG(x) (BDMA_REG_CH0_BASE+(x)) 119 #define BDMA_SET_CH1_REG(x) (BDMA_SET_CH0_REG(x)+BDMA_CH_REG_OFFSET) 120 121 #define BDMA_REG_CH0_CTRL BDMA_SET_CH0_REG(0UL) 122 #define BDMA_REG_CH0_STATUS BDMA_SET_CH0_REG(0x02UL) 123 #define BDMA_REG_CH0_SRC_SEL BDMA_SET_CH0_REG(0x04UL) 124 #define BDMA_REG_CH0_DST_SEL BDMA_SET_CH0_REG(0x05UL) 125 #define BDMA_REG_CH0_MISC BDMA_SET_CH0_REG(0x06UL) 126 #define BDMA_REG_CH0_DWUM_CNT BDMA_SET_CH0_REG(0x07UL) 127 #define BDMA_REG_CH0_SRC_ADDR_L BDMA_SET_CH0_REG(0x08UL) 128 #define BDMA_REG_CH0_SRC_ADDR_H BDMA_SET_CH0_REG(0x0AUL) 129 #define BDMA_REG_CH0_DST_ADDR_L BDMA_SET_CH0_REG(0x0CUL) 130 #define BDMA_REG_CH0_DST_ADDR_H BDMA_SET_CH0_REG(0x0EUL) 131 #define BDMA_REG_CH0_SIZE_L BDMA_SET_CH0_REG(0x10UL) 132 #define BDMA_REG_CH0_SIZE_H BDMA_SET_CH0_REG(0x12UL) 133 //Ch0 Special command 0 134 #define BDMA_REG_CH0_CMD0_L BDMA_SET_CH0_REG(0x14UL) 135 #define BDMA_REG_CH0_CMD0_H BDMA_SET_CH0_REG(0x16UL) 136 //Ch0 Special command 1 137 #define BDMA_REG_CH0_CMD1_L BDMA_SET_CH0_REG(0x18UL) 138 #define BDMA_REG_CH0_CMD1_H BDMA_SET_CH0_REG(0x1AUL) 139 //Ch0 Special command 2 140 #define BDMA_REG_CH0_CMD2_L BDMA_SET_CH0_REG(0x1CUL) 141 #define BDMA_REG_CH0_CMD2_H BDMA_SET_CH0_REG(0x1EUL) 142 143 //--------------------------------------------- 144 // definition for BDMA_REG_CH0_CTRL/BDMA_REG_CH1_CTRL 145 //--------------------------------------------- 146 #define BDMA_CH_TRIGGER __BIT0 147 #define BDMA_CH_STOP __BIT4 148 149 //--------------------------------------------- 150 // definition for REG_BDMA_CH0_STATUS/REG_BDMA_CH1_STATUS 151 //--------------------------------------------- 152 #define BDMA_CH_QUEUED __BIT0 153 #define BDMA_CH_BUSY __BIT1 154 #define BDMA_CH_INT __BIT2 155 #define BDMA_CH_DONE __BIT3 156 #define BDMA_CH_RESULT __BIT4 157 #define BDMA_CH_CLEAR_STATUS (BDMA_CH_INT|BDMA_CH_DONE|BDMA_CH_RESULT) 158 //--------------------------------------------- 159 // definition for REG_BDMA_CH0_MISC/REG_BDMA_CH1_MISC 160 //--------------------------------------------- 161 #define BDMA_CH_ADDR_DECDIR __BIT0 162 #define BDMA_CH_DONE_INT_EN __BIT1 163 #define BDMA_CH_CRC_REFLECTION __BIT4 164 #define BDMA_CH_MOBF_EN __BIT5 165 166 #endif 167