1 #ifndef _AUDIO_R2_SHM_H_ 2 #define _AUDIO_R2_SHM_H_ 3 4 /************************************************************************************************************************** 5 * 6 * SHARE MEMORY of DEC - R2 7 * 8 **************************************************************************************************************************/ 9 #define MBOX_DEC_R2_CTRL 0x0388 10 #define MBOX_DEC_R2_CTRL_LOCK_SHM_BIT 0x0001 //[0]: lock "share memory" update 11 12 #define MBOX_DEC_R2_STATUS 0x03A8 13 #define MBOX_DEC_R2_STATUS_UPDATING_SHM_BIT 0x0001 //[0]: R2 is updating "share memory" now. 14 15 #define DEC_R2_SHM_DDR_OFFSET 0x6000 16 #define DEC_R2_SHM_DDR_SIZE 0xA00 17 #define MAX_ADEC 2 18 #define MAX_ES 4 19 #define SHM_PARAM_BOOT_MAGIC_ID 0x12345677 20 typedef struct 21 { 22 23 AUR2_ADEC_ES_INFO_SHM adec_esInfo_shm[MAX_ES]; 24 AUR2_ADEC_ES_PARAM_SHM adec_esParam_shm[MAX_ES]; 25 26 AUR2_ADEC_INFO_SHM adec_info_shm[MAX_ADEC]; 27 AUR2_ADEC_PARAM_SHM adec_param_shm[MAX_ADEC]; 28 29 AUR2_ADEC_Ch_INFO_SHM adec_chInfo_shm; 30 31 MS_U32 RfSignalType; //0: DVB, 1: ATSC, 2: ISDB 32 33 unsigned int esPassThrough_delaySmp; 34 unsigned int esPassThrough_pcmSmpRate; 35 unsigned int esPassThrough_hdmiSmpRate; 36 37 MS_U32 SHM_magicID_end; 38 MS_U32 Security_Check; 39 40 } DEC_R2_SHARE_MEM; 41 42 #endif 43