1*53ee8cc1Swenshuai.xi #ifndef _AUDIO_R2_SHM_H_ 2*53ee8cc1Swenshuai.xi #define _AUDIO_R2_SHM_H_ 3*53ee8cc1Swenshuai.xi 4*53ee8cc1Swenshuai.xi /************************************************************************************************************************** 5*53ee8cc1Swenshuai.xi * 6*53ee8cc1Swenshuai.xi * SHARE MEMORY of DEC - R2 7*53ee8cc1Swenshuai.xi * 8*53ee8cc1Swenshuai.xi **************************************************************************************************************************/ 9*53ee8cc1Swenshuai.xi #define MBOX_DEC_R2_CTRL 0x0388 10*53ee8cc1Swenshuai.xi #define MBOX_DEC_R2_CTRL_LOCK_SHM_BIT 0x0001 //[0]: lock "share memory" update 11*53ee8cc1Swenshuai.xi 12*53ee8cc1Swenshuai.xi #define MBOX_DEC_R2_STATUS 0x03A8 13*53ee8cc1Swenshuai.xi #define MBOX_DEC_R2_STATUS_UPDATING_SHM_BIT 0x0001 //[0]: R2 is updating "share memory" now. 14*53ee8cc1Swenshuai.xi 15*53ee8cc1Swenshuai.xi #define DEC_R2_SHM_DDR_OFFSET 0x4000 16*53ee8cc1Swenshuai.xi #define DEC_R2_SHM_DDR_SIZE 0xA00 17*53ee8cc1Swenshuai.xi #define MAX_ADEC 2 18*53ee8cc1Swenshuai.xi #define MAX_ES 4 19*53ee8cc1Swenshuai.xi #define SHM_PARAM_BOOT_MAGIC_ID 0x12345677 20*53ee8cc1Swenshuai.xi typedef struct 21*53ee8cc1Swenshuai.xi { 22*53ee8cc1Swenshuai.xi 23*53ee8cc1Swenshuai.xi AUR2_ADEC_ES_INFO_SHM adec_esInfo_shm[MAX_ES]; 24*53ee8cc1Swenshuai.xi AUR2_ADEC_ES_PARAM_SHM adec_esParam_shm[MAX_ES]; 25*53ee8cc1Swenshuai.xi 26*53ee8cc1Swenshuai.xi AUR2_ADEC_INFO_SHM adec_info_shm[MAX_ADEC]; 27*53ee8cc1Swenshuai.xi AUR2_ADEC_PARAM_SHM adec_param_shm[MAX_ADEC]; 28*53ee8cc1Swenshuai.xi 29*53ee8cc1Swenshuai.xi AUR2_ADEC_Ch_INFO_SHM adec_chInfo_shm; 30*53ee8cc1Swenshuai.xi 31*53ee8cc1Swenshuai.xi MS_U32 RfSignalType; //0: DVB, 1: ATSC, 2: ISDB 32*53ee8cc1Swenshuai.xi MS_U32 SHM_magicID_end; 33*53ee8cc1Swenshuai.xi 34*53ee8cc1Swenshuai.xi } DEC_R2_SHARE_MEM; 35*53ee8cc1Swenshuai.xi 36*53ee8cc1Swenshuai.xi #endif 37