xref: /utopia/UTPA2-700.0.x/modules/audio/hal/mainz/audsp/DecoderInfo.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

//<MStar Software>
//******************************************************************************
// MStar Software
// Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
// All software, firmware and related documentation herein ("MStar Software") are
// intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
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////////////////////////////////////////////////////////////////////////////////

#ifndef _DECODER_INFO_H_
#define _DECODER_INFO_H_

//===========================================================================
// define supported decoder here
//===========================================================================
#ifndef CONFIG_MBOOT // Normal mode
    #define    DSP_SUPPORT_XPCM                1
    #define    DSP_SUPPORT_MP3                 1
    #define    DSP_SUPPORT_MPEG                1
    #define    DSP_SUPPORT_AC3P                1
    #define    DSP_SUPPORT_MS10_DDT            0
    #define    DSP_SUPPORT_GAAC                1
    #define    DSP_SUPPORT_WMA_PRO             1
    #define    DSP_SUPPORT_DTS_DMP             1
    #define    DSP_SUPPORT_DTS_LBR             0
    #define    DSP_SUPPORT_RA8LBR              1
    #define    DSP_SUPPORT_VORBIS              1
    #define    DSP_SUPPORT_AMR_NB              1
    #define    DSP_SUPPORT_AMR_WB              1
    #define    DSP_SUPPORT_DRAD                1
    #define    DSP_SUPPORT_FLAC                1
    #define    DSP_SUPPORT_PALSUM              1
    #define    DSP_SUPPORT_BTSC                1
    #define    DSP_SUPPORT_TSHD                1
    #define    DSP_SUPPORT_TSXT                1
    #define    DSP_SUPPORT_PURESND             1
    #define    DSP_SUPPORT_DEC                 1
    #define    DSP_SUPPORT_DDE                 0
    #define    DSP_SUPPORT_DBX                 1
    #define    DSP_SUPPORT_BONGIOVIDPS         1
#else //Mboot mode
    #define    DSP_SUPPORT_XPCM                0
    #define    DSP_SUPPORT_MP3                 1
    #define    DSP_SUPPORT_MPEG                0
    #define    DSP_SUPPORT_AC3P                0
    #define    DSP_SUPPORT_MS10_DDT            0
    #define    DSP_SUPPORT_GAAC                0
    #define    DSP_SUPPORT_WMA_PRO             0
    #define    DSP_SUPPORT_DTS_DMP             0
    #define    DSP_SUPPORT_DTS_LBR             0
    #define    DSP_SUPPORT_RA8LBR              0
    #define    DSP_SUPPORT_VORBIS              0
    #define    DSP_SUPPORT_AMR_NB              0
    #define    DSP_SUPPORT_AMR_WB              0
    #define    DSP_SUPPORT_DRAD                0
    #define    DSP_SUPPORT_FLAC                0
    #define    DSP_SUPPORT_PALSUM              0
    #define    DSP_SUPPORT_BTSC                0
    #define    DSP_SUPPORT_TSHD                0
    #define    DSP_SUPPORT_TSXT                0
    #define    DSP_SUPPORT_PURESND             0
    #define    DSP_SUPPORT_DBX                 0
    #define    DSP_SUPPORT_DEC                 0
    #define    DSP_SUPPORT_DDE                 0
    #define    DSP_SUPPORT_BONGIOVIDPS         0
#endif

//===========================================================================
// Include files
//===========================================================================

    #include    "dspcode_s/aucode_s.c"

#if(DSP_SUPPORT_XPCM)
    #include    "dspcode_s/aucode_xpcm.c"
#endif
#if(DSP_SUPPORT_MP3)
    #include    "dspcode_s/aucode_mp3.c"
#endif
#if(DSP_SUPPORT_MPEG)
    #include    "dspcode_s/aucode_mpeg.c"
#endif
#if(DSP_SUPPORT_AC3P)
    #include    "dspcode_s/aucode_ac3p.c"
#endif
#if(DSP_SUPPORT_MS10_DDT)
    #include    "dspcode_s/aucode_ms10_ddt.c"
#endif
#if(DSP_SUPPORT_GAAC)
    #include    "dspcode_s/aucode_gaac.c"
#endif
#if(DSP_SUPPORT_WMA_PRO)
    #include    "dspcode_s/aucode_wma_pro.c"
#endif
#if(DSP_SUPPORT_DTS_DMP)
    #include    "dspcode_s/aucode_dts_dmp.c"
#endif
#if(DSP_SUPPORT_DTS_LBR)
    #include    "dspcode_s/aucode_dts_lbr.c"
#endif
#if(DSP_SUPPORT_RA8LBR)
    #include    "dspcode_s/aucode_ra8lbr.c"
#endif
#if(DSP_SUPPORT_VORBIS)
    #include    "dspcode_s/aucode_vorbis.c"
#endif
#if(DSP_SUPPORT_AMR_NB)
    #include    "dspcode_s/aucode_amr_nb.c"
#endif
#if(DSP_SUPPORT_AMR_WB)
    #include    "dspcode_s/aucode_amr_wb.c"
#endif
#if(DSP_SUPPORT_DRAD)
    #include    "dspcode_s/aucode_drad.c"
#endif
#if(DSP_SUPPORT_FLAC)
    #include    "dspcode_s/aucode_flac.c"
#endif
#if(DSP_SUPPORT_PALSUM)
    #include    "dspcode_s/aucode_palsum.c"
#endif
#if(DSP_SUPPORT_BTSC)
    #include    "dspcode_s/aucode_btsc.c"
#endif
#if(DSP_SUPPORT_TSHD)
    #include    "dspcode_s/aucode_tshd.c"
#endif
#if(DSP_SUPPORT_TSXT)
    #include    "dspcode_s/aucode_tsxt.c"
#endif
#if(DSP_SUPPORT_PURESND)
    #include    "dspcode_s/aucode_puresnd.c"
#endif
#if(DSP_SUPPORT_DEC)
    #include    "dspcode_s/aucode_dec.c"
#endif
#if(DSP_SUPPORT_DDE)
    #include    "dspcode_s/aucode_dde.c"
#endif
#if(DSP_SUPPORT_DBX)
    #include    "dspcode_s/aucode_dbx.c"
#endif
#if(DSP_SUPPORT_BONGIOVIDPS)
    #include    "dspcode_s/aucode_dps.c"
#endif
//===========================================================
#ifndef    MST_CODEC_XPCM_PM1_ADDR
    #define    MST_CODEC_XPCM_PM1_ADDR              0
    #define    MST_CODEC_XPCM_PM1_SIZE              0
    #define    mst_codec_xpcm_pm1                   0
#endif
#ifndef    MST_CODEC_XPCM_PM2_ADDR
    #define    MST_CODEC_XPCM_PM2_ADDR              0
    #define    MST_CODEC_XPCM_PM2_SIZE              0
    #define    mst_codec_xpcm_pm2                   0
#endif
#ifndef    MST_CODEC_XPCM_PM3_ADDR
    #define    MST_CODEC_XPCM_PM3_ADDR              0
    #define    MST_CODEC_XPCM_PM3_SIZE              0
    #define    mst_codec_xpcm_pm3                   0
#endif
#ifndef    MST_CODEC_XPCM_PM4_ADDR
    #define    MST_CODEC_XPCM_PM4_ADDR              0
    #define    MST_CODEC_XPCM_PM4_SIZE              0
    #define    mst_codec_xpcm_pm4                   0
#endif
#ifndef    MST_CODEC_MP3_PM1_ADDR
    #define    MST_CODEC_MP3_PM1_ADDR               0
    #define    MST_CODEC_MP3_PM1_SIZE               0
    #define    mst_codec_mp3_pm1                    0
#endif
#ifndef    MST_CODEC_MP3_PM2_ADDR
    #define    MST_CODEC_MP3_PM2_ADDR               0
    #define    MST_CODEC_MP3_PM2_SIZE               0
    #define    mst_codec_mp3_pm2                    0
#endif
#ifndef    MST_CODEC_MP3_PM3_ADDR
    #define    MST_CODEC_MP3_PM3_ADDR               0
    #define    MST_CODEC_MP3_PM3_SIZE               0
    #define    mst_codec_mp3_pm3                    0
#endif
#ifndef    MST_CODEC_MP3_PM4_ADDR
    #define    MST_CODEC_MP3_PM4_ADDR               0
    #define    MST_CODEC_MP3_PM4_SIZE               0
    #define    mst_codec_mp3_pm4                    0
#endif
#ifndef    MST_CODEC_MPEG_PM1_ADDR
    #define    MST_CODEC_MPEG_PM1_ADDR              0
    #define    MST_CODEC_MPEG_PM1_SIZE              0
    #define    mst_codec_mpeg_pm1                   0
#endif
#ifndef    MST_CODEC_MPEG_PM2_ADDR
    #define    MST_CODEC_MPEG_PM2_ADDR              0
    #define    MST_CODEC_MPEG_PM2_SIZE              0
    #define    mst_codec_mpeg_pm2                   0
#endif
#ifndef    MST_CODEC_MPEG_PM3_ADDR
    #define    MST_CODEC_MPEG_PM3_ADDR              0
    #define    MST_CODEC_MPEG_PM3_SIZE              0
    #define    mst_codec_mpeg_pm3                   0
#endif
#ifndef    MST_CODEC_MPEG_PM4_ADDR
    #define    MST_CODEC_MPEG_PM4_ADDR              0
    #define    MST_CODEC_MPEG_PM4_SIZE              0
    #define    mst_codec_mpeg_pm4                   0
#endif
#ifndef    MST_CODEC_AC3P_PM1_ADDR
    #define    MST_CODEC_AC3P_PM1_ADDR              0
    #define    MST_CODEC_AC3P_PM1_SIZE              0
    #define    mst_codec_ac3p_pm1                   0
#endif
#ifndef    MST_CODEC_AC3P_PM2_ADDR
    #define    MST_CODEC_AC3P_PM2_ADDR              0
    #define    MST_CODEC_AC3P_PM2_SIZE              0
    #define    mst_codec_ac3p_pm2                   0
#endif
#ifndef    MST_CODEC_AC3P_PM3_ADDR
    #define    MST_CODEC_AC3P_PM3_ADDR              0
    #define    MST_CODEC_AC3P_PM3_SIZE              0
    #define    mst_codec_ac3p_pm3                   0
#endif
#ifndef    MST_CODEC_AC3P_PM4_ADDR
    #define    MST_CODEC_AC3P_PM4_ADDR              0
    #define    MST_CODEC_AC3P_PM4_SIZE              0
    #define    mst_codec_ac3p_pm4                   0
#endif
#ifndef    MST_CODEC_MS10_DDT_PM1_ADDR
    #define    MST_CODEC_MS10_DDT_PM1_ADDR          0
    #define    MST_CODEC_MS10_DDT_PM1_SIZE          0
    #define    mst_codec_ms10_ddt_pm1               0
#endif
#ifndef    MST_CODEC_MS10_DDT_PM2_ADDR
    #define    MST_CODEC_MS10_DDT_PM2_ADDR          0
    #define    MST_CODEC_MS10_DDT_PM2_SIZE          0
    #define    mst_codec_ms10_ddt_pm2               0
#endif
#ifndef    MST_CODEC_MS10_DDT_PM3_ADDR
    #define    MST_CODEC_MS10_DDT_PM3_ADDR          0
    #define    MST_CODEC_MS10_DDT_PM3_SIZE          0
    #define    mst_codec_ms10_ddt_pm3               0
#endif
#ifndef    MST_CODEC_MS10_DDT_PM4_ADDR
    #define    MST_CODEC_MS10_DDT_PM4_ADDR          0
    #define    MST_CODEC_MS10_DDT_PM4_SIZE          0
    #define    mst_codec_ms10_ddt_pm4               0
#endif
#ifndef    MST_CODEC_GAAC_PM1_ADDR
    #define    MST_CODEC_GAAC_PM1_ADDR              0
    #define    MST_CODEC_GAAC_PM1_SIZE              0
    #define    mst_codec_gaac_pm1                   0
#endif
#ifndef    MST_CODEC_GAAC_PM2_ADDR
    #define    MST_CODEC_GAAC_PM2_ADDR              0
    #define    MST_CODEC_GAAC_PM2_SIZE              0
    #define    mst_codec_gaac_pm2                   0
#endif
#ifndef    MST_CODEC_GAAC_PM3_ADDR
    #define    MST_CODEC_GAAC_PM3_ADDR              0
    #define    MST_CODEC_GAAC_PM3_SIZE              0
    #define    mst_codec_gaac_pm3                   0
#endif
#ifndef    MST_CODEC_GAAC_PM4_ADDR
    #define    MST_CODEC_GAAC_PM4_ADDR              0
    #define    MST_CODEC_GAAC_PM4_SIZE              0
    #define    mst_codec_gaac_pm4                   0
#endif
#ifndef    MST_CODEC_WMA_PRO_PM1_ADDR
    #define    MST_CODEC_WMA_PRO_PM1_ADDR           0
    #define    MST_CODEC_WMA_PRO_PM1_SIZE           0
    #define    mst_codec_wma_pro_pm1                0
#endif
#ifndef    MST_CODEC_WMA_PRO_PM2_ADDR
    #define    MST_CODEC_WMA_PRO_PM2_ADDR           0
    #define    MST_CODEC_WMA_PRO_PM2_SIZE           0
    #define    mst_codec_wma_pro_pm2                0
#endif
#ifndef    MST_CODEC_WMA_PRO_PM3_ADDR
    #define    MST_CODEC_WMA_PRO_PM3_ADDR           0
    #define    MST_CODEC_WMA_PRO_PM3_SIZE           0
    #define    mst_codec_wma_pro_pm3                0
#endif
#ifndef    MST_CODEC_WMA_PRO_PM4_ADDR
    #define    MST_CODEC_WMA_PRO_PM4_ADDR           0
    #define    MST_CODEC_WMA_PRO_PM4_SIZE           0
    #define    mst_codec_wma_pro_pm4                0
#endif
#ifndef    MST_CODEC_DTS_DMP_PM1_ADDR
    #define    MST_CODEC_DTS_DMP_PM1_ADDR           0
    #define    MST_CODEC_DTS_DMP_PM1_SIZE           0
    #define    mst_codec_dts_dmp_pm1                0
#endif
#ifndef    MST_CODEC_DTS_DMP_PM2_ADDR
    #define    MST_CODEC_DTS_DMP_PM2_ADDR           0
    #define    MST_CODEC_DTS_DMP_PM2_SIZE           0
    #define    mst_codec_dts_dmp_pm2                0
#endif
#ifndef    MST_CODEC_DTS_DMP_PM3_ADDR
    #define    MST_CODEC_DTS_DMP_PM3_ADDR           0
    #define    MST_CODEC_DTS_DMP_PM3_SIZE           0
    #define    mst_codec_dts_dmp_pm3                0
#endif
#ifndef    MST_CODEC_DTS_DMP_PM4_ADDR
    #define    MST_CODEC_DTS_DMP_PM4_ADDR           0
    #define    MST_CODEC_DTS_DMP_PM4_SIZE           0
    #define    mst_codec_dts_dmp_pm4                0
#endif
#ifndef    MST_CODEC_DTS_LBR_PM1_ADDR
    #define    MST_CODEC_DTS_LBR_PM1_ADDR           0
    #define    MST_CODEC_DTS_LBR_PM1_SIZE           0
    #define    mst_codec_dts_lbr_pm1                0
#endif
#ifndef    MST_CODEC_DTS_LBR_PM2_ADDR
    #define    MST_CODEC_DTS_LBR_PM2_ADDR           0
    #define    MST_CODEC_DTS_LBR_PM2_SIZE           0
    #define    mst_codec_dts_lbr_pm2                0
#endif
#ifndef    MST_CODEC_DTS_LBR_PM3_ADDR
    #define    MST_CODEC_DTS_LBR_PM3_ADDR           0
    #define    MST_CODEC_DTS_LBR_PM3_SIZE           0
    #define    mst_codec_dts_lbr_pm3                0
#endif
#ifndef    MST_CODEC_DTS_LBR_PM4_ADDR
    #define    MST_CODEC_DTS_LBR_PM4_ADDR           0
    #define    MST_CODEC_DTS_LBR_PM4_SIZE           0
    #define    mst_codec_dts_lbr_pm4                0
#endif
#ifndef    MST_CODEC_RA8LBR_PM1_ADDR
    #define    MST_CODEC_RA8LBR_PM1_ADDR            0
    #define    MST_CODEC_RA8LBR_PM1_SIZE            0
    #define    mst_codec_ra8lbr_pm1                 0
#endif
#ifndef    MST_CODEC_RA8LBR_PM2_ADDR
    #define    MST_CODEC_RA8LBR_PM2_ADDR            0
    #define    MST_CODEC_RA8LBR_PM2_SIZE            0
    #define    mst_codec_ra8lbr_pm2                 0
#endif
#ifndef    MST_CODEC_RA8LBR_PM3_ADDR
    #define    MST_CODEC_RA8LBR_PM3_ADDR            0
    #define    MST_CODEC_RA8LBR_PM3_SIZE            0
    #define    mst_codec_ra8lbr_pm3                 0
#endif
#ifndef    MST_CODEC_RA8LBR_PM4_ADDR
    #define    MST_CODEC_RA8LBR_PM4_ADDR            0
    #define    MST_CODEC_RA8LBR_PM4_SIZE            0
    #define    mst_codec_ra8lbr_pm4                 0
#endif
#ifndef    MST_CODEC_VORBIS_PM1_ADDR
    #define    MST_CODEC_VORBIS_PM1_ADDR            0
    #define    MST_CODEC_VORBIS_PM1_SIZE            0
    #define    mst_codec_vorbis_pm1                 0
#endif
#ifndef    MST_CODEC_VORBIS_PM2_ADDR
    #define    MST_CODEC_VORBIS_PM2_ADDR            0
    #define    MST_CODEC_VORBIS_PM2_SIZE            0
    #define    mst_codec_vorbis_pm2                 0
#endif
#ifndef    MST_CODEC_VORBIS_PM3_ADDR
    #define    MST_CODEC_VORBIS_PM3_ADDR            0
    #define    MST_CODEC_VORBIS_PM3_SIZE            0
    #define    mst_codec_vorbis_pm3                 0
#endif
#ifndef    MST_CODEC_VORBIS_PM4_ADDR
    #define    MST_CODEC_VORBIS_PM4_ADDR            0
    #define    MST_CODEC_VORBIS_PM4_SIZE            0
    #define    mst_codec_vorbis_pm4                 0
#endif
#ifndef    MST_CODEC_AMR_NB_PM1_ADDR
    #define    MST_CODEC_AMR_NB_PM1_ADDR            0
    #define    MST_CODEC_AMR_NB_PM1_SIZE            0
    #define    mst_codec_amr_nb_pm1                 0
#endif
#ifndef    MST_CODEC_AMR_NB_PM2_ADDR
    #define    MST_CODEC_AMR_NB_PM2_ADDR            0
    #define    MST_CODEC_AMR_NB_PM2_SIZE            0
    #define    mst_codec_amr_nb_pm2                 0
#endif
#ifndef    MST_CODEC_AMR_NB_PM3_ADDR
    #define    MST_CODEC_AMR_NB_PM3_ADDR            0
    #define    MST_CODEC_AMR_NB_PM3_SIZE            0
    #define    mst_codec_amr_nb_pm3                 0
#endif
#ifndef    MST_CODEC_AMR_NB_PM4_ADDR
    #define    MST_CODEC_AMR_NB_PM4_ADDR            0
    #define    MST_CODEC_AMR_NB_PM4_SIZE            0
    #define    mst_codec_amr_nb_pm4                 0
#endif
#ifndef    MST_CODEC_AMR_WB_PM1_ADDR
    #define    MST_CODEC_AMR_WB_PM1_ADDR            0
    #define    MST_CODEC_AMR_WB_PM1_SIZE            0
    #define    mst_codec_amr_wb_pm1                 0
#endif
#ifndef    MST_CODEC_AMR_WB_PM2_ADDR
    #define    MST_CODEC_AMR_WB_PM2_ADDR            0
    #define    MST_CODEC_AMR_WB_PM2_SIZE            0
    #define    mst_codec_amr_wb_pm2                 0
#endif
#ifndef    MST_CODEC_AMR_WB_PM3_ADDR
    #define    MST_CODEC_AMR_WB_PM3_ADDR            0
    #define    MST_CODEC_AMR_WB_PM3_SIZE            0
    #define    mst_codec_amr_wb_pm3                 0
#endif
#ifndef    MST_CODEC_AMR_WB_PM4_ADDR
    #define    MST_CODEC_AMR_WB_PM4_ADDR            0
    #define    MST_CODEC_AMR_WB_PM4_SIZE            0
    #define    mst_codec_amr_wb_pm4                 0
#endif
#ifndef    MST_CODEC_DRAD_PM1_ADDR
    #define    MST_CODEC_DRAD_PM1_ADDR              0
    #define    MST_CODEC_DRAD_PM1_SIZE              0
    #define    mst_codec_drad_pm1                   0
#endif
#ifndef    MST_CODEC_DRAD_PM2_ADDR
    #define    MST_CODEC_DRAD_PM2_ADDR              0
    #define    MST_CODEC_DRAD_PM2_SIZE              0
    #define    mst_codec_drad_pm2                   0
#endif
#ifndef    MST_CODEC_DRAD_PM3_ADDR
    #define    MST_CODEC_DRAD_PM3_ADDR              0
    #define    MST_CODEC_DRAD_PM3_SIZE              0
    #define    mst_codec_drad_pm3                   0
#endif
#ifndef    MST_CODEC_DRAD_PM4_ADDR
    #define    MST_CODEC_DRAD_PM4_ADDR              0
    #define    MST_CODEC_DRAD_PM4_SIZE              0
    #define    mst_codec_drad_pm4                   0
#endif
#ifndef    MST_CODEC_FLAC_PM1_ADDR
    #define    MST_CODEC_FLAC_PM1_ADDR              0
    #define    MST_CODEC_FLAC_PM1_SIZE              0
    #define    mst_codec_flac_pm1                   0
#endif
#ifndef    MST_CODEC_FLAC_PM2_ADDR
    #define    MST_CODEC_FLAC_PM2_ADDR              0
    #define    MST_CODEC_FLAC_PM2_SIZE              0
    #define    mst_codec_flac_pm2                   0
#endif
#ifndef    MST_CODEC_FLAC_PM3_ADDR
    #define    MST_CODEC_FLAC_PM3_ADDR              0
    #define    MST_CODEC_FLAC_PM3_SIZE              0
    #define    mst_codec_flac_pm3                   0
#endif
#ifndef    MST_CODEC_FLAC_PM4_ADDR
    #define    MST_CODEC_FLAC_PM4_ADDR              0
    #define    MST_CODEC_FLAC_PM4_SIZE              0
    #define    mst_codec_flac_pm4                   0
#endif
#ifndef    MST_CODEC_PALSUM_PM1_ADDR
    #define    MST_CODEC_PALSUM_PM1_ADDR            0
    #define    MST_CODEC_PALSUM_PM1_SIZE            0
    #define    mst_codec_palsum_pm1                 0
#endif
#ifndef    MST_CODEC_PALSUM_PM2_ADDR
    #define    MST_CODEC_PALSUM_PM2_ADDR            0
    #define    MST_CODEC_PALSUM_PM2_SIZE            0
    #define    mst_codec_palsum_pm2                 0
#endif
#ifndef    MST_CODEC_PALSUM_PM3_ADDR
    #define    MST_CODEC_PALSUM_PM3_ADDR            0
    #define    MST_CODEC_PALSUM_PM3_SIZE            0
    #define    mst_codec_palsum_pm3                 0
#endif
#ifndef    MST_CODEC_PALSUM_PM4_ADDR
    #define    MST_CODEC_PALSUM_PM4_ADDR            0
    #define    MST_CODEC_PALSUM_PM4_SIZE            0
    #define    mst_codec_palsum_pm4                 0
#endif
#ifndef    MST_CODEC_BTSC_PM1_ADDR
    #define    MST_CODEC_BTSC_PM1_ADDR              0
    #define    MST_CODEC_BTSC_PM1_SIZE              0
    #define    mst_codec_btsc_pm1                   0
#endif
#ifndef    MST_CODEC_BTSC_PM2_ADDR
    #define    MST_CODEC_BTSC_PM2_ADDR              0
    #define    MST_CODEC_BTSC_PM2_SIZE              0
    #define    mst_codec_btsc_pm2                   0
#endif
#ifndef    MST_CODEC_BTSC_PM3_ADDR
    #define    MST_CODEC_BTSC_PM3_ADDR              0
    #define    MST_CODEC_BTSC_PM3_SIZE              0
    #define    mst_codec_btsc_pm3                   0
#endif
#ifndef    MST_CODEC_BTSC_PM4_ADDR
    #define    MST_CODEC_BTSC_PM4_ADDR              0
    #define    MST_CODEC_BTSC_PM4_SIZE              0
    #define    mst_codec_btsc_pm4                   0
#endif
#ifndef    MST_CODEC_TSHD_PM1_ADDR
    #define    MST_CODEC_TSHD_PM1_ADDR              0
    #define    MST_CODEC_TSHD_PM1_SIZE              0
    #define    mst_codec_tshd_pm1                   0
#endif
#ifndef    MST_CODEC_TSHD_PM2_ADDR
    #define    MST_CODEC_TSHD_PM2_ADDR              0
    #define    MST_CODEC_TSHD_PM2_SIZE              0
    #define    mst_codec_tshd_pm2                   0
#endif
#ifndef    MST_CODEC_TSHD_PM3_ADDR
    #define    MST_CODEC_TSHD_PM3_ADDR              0
    #define    MST_CODEC_TSHD_PM3_SIZE              0
    #define    mst_codec_tshd_pm3                   0
#endif
#ifndef    MST_CODEC_TSHD_PM4_ADDR
    #define    MST_CODEC_TSHD_PM4_ADDR              0
    #define    MST_CODEC_TSHD_PM4_SIZE              0
    #define    mst_codec_tshd_pm4                   0
#endif
#ifndef    MST_CODEC_TSXT_PM1_ADDR
    #define    MST_CODEC_TSXT_PM1_ADDR              0
    #define    MST_CODEC_TSXT_PM1_SIZE              0
    #define    mst_codec_tsxt_pm1                   0
#endif
#ifndef    MST_CODEC_TSXT_PM2_ADDR
    #define    MST_CODEC_TSXT_PM2_ADDR              0
    #define    MST_CODEC_TSXT_PM2_SIZE              0
    #define    mst_codec_tsxt_pm2                   0
#endif
#ifndef    MST_CODEC_TSXT_PM3_ADDR
    #define    MST_CODEC_TSXT_PM3_ADDR              0
    #define    MST_CODEC_TSXT_PM3_SIZE              0
    #define    mst_codec_tsxt_pm3                   0
#endif
#ifndef    MST_CODEC_TSXT_PM4_ADDR
    #define    MST_CODEC_TSXT_PM4_ADDR              0
    #define    MST_CODEC_TSXT_PM4_SIZE              0
    #define    mst_codec_tsxt_pm4                   0
#endif
#ifndef    MST_CODEC_PURESND_PM1_ADDR
    #define    MST_CODEC_PURESND_PM1_ADDR           0
    #define    MST_CODEC_PURESND_PM1_SIZE           0
    #define    mst_codec_puresnd_pm1                0
#endif
#ifndef    MST_CODEC_PURESND_PM2_ADDR
    #define    MST_CODEC_PURESND_PM2_ADDR           0
    #define    MST_CODEC_PURESND_PM2_SIZE           0
    #define    mst_codec_puresnd_pm2                0
#endif
#ifndef    MST_CODEC_PURESND_PM3_ADDR
    #define    MST_CODEC_PURESND_PM3_ADDR           0
    #define    MST_CODEC_PURESND_PM3_SIZE           0
    #define    mst_codec_puresnd_pm3                0
#endif
#ifndef    MST_CODEC_PURESND_PM4_ADDR
    #define    MST_CODEC_PURESND_PM4_ADDR           0
    #define    MST_CODEC_PURESND_PM4_SIZE           0
    #define    mst_codec_puresnd_pm4                0
#endif
#ifndef    MST_CODEC_DPS_PM1_ADDR
    #define    MST_CODEC_DPS_PM1_ADDR               0
    #define    MST_CODEC_DPS_PM1_SIZE               0
    #define    mst_codec_dps_pm1                    0
#endif
#ifndef    MST_CODEC_DPS_PM2_ADDR
    #define    MST_CODEC_DPS_PM2_ADDR               0
    #define    MST_CODEC_DPS_PM2_SIZE               0
    #define    mst_codec_dps_pm2                    0
#endif
#ifndef    MST_CODEC_DPS_PM3_ADDR
    #define    MST_CODEC_DPS_PM3_ADDR               0
    #define    MST_CODEC_DPS_PM3_SIZE               0
    #define    mst_codec_dps_pm3                    0
#endif
#ifndef    MST_CODEC_DPS_PM4_ADDR
    #define    MST_CODEC_DPS_PM4_ADDR               0
    #define    MST_CODEC_DPS_PM4_SIZE               0
    #define    mst_codec_dps_pm4                    0
#endif

#ifndef    MST_CODEC_DEC_PM1_ADDR
    #define    MST_CODEC_DEC_PM1_ADDR               0
    #define    MST_CODEC_DEC_PM1_SIZE               0
    #define    mst_codec_dec_pm1                    0
#endif
#ifndef    MST_CODEC_DEC_PM2_ADDR
    #define    MST_CODEC_DEC_PM2_ADDR               0
    #define    MST_CODEC_DEC_PM2_SIZE               0
    #define    mst_codec_dec_pm2                    0
#endif
#ifndef    MST_CODEC_DEC_PM3_ADDR
    #define    MST_CODEC_DEC_PM3_ADDR               0
    #define    MST_CODEC_DEC_PM3_SIZE               0
    #define    mst_codec_dec_pm3                    0
#endif
#ifndef    MST_CODEC_DEC_PM4_ADDR
    #define    MST_CODEC_DEC_PM4_ADDR               0
    #define    MST_CODEC_DEC_PM4_SIZE               0
    #define    mst_codec_dec_pm4                    0
#endif
#ifndef    MST_CODEC_DDE_PM1_ADDR
    #define    MST_CODEC_DDE_PM1_ADDR               0
    #define    MST_CODEC_DDE_PM1_SIZE               0
    #define    mst_codec_dde_pm1                    0
#endif
#ifndef    MST_CODEC_DDE_PM2_ADDR
    #define    MST_CODEC_DDE_PM2_ADDR               0
    #define    MST_CODEC_DDE_PM2_SIZE               0
    #define    mst_codec_dde_pm2                    0
#endif
#ifndef    MST_CODEC_DDE_PM3_ADDR
    #define    MST_CODEC_DDE_PM3_ADDR               0
    #define    MST_CODEC_DDE_PM3_SIZE               0
    #define    mst_codec_dde_pm3                    0
#endif
#ifndef    MST_CODEC_DDE_PM4_ADDR
    #define    MST_CODEC_DDE_PM4_ADDR               0
    #define    MST_CODEC_DDE_PM4_SIZE               0
    #define    mst_codec_dde_pm4                    0
#endif

#ifndef    MST_CODEC_DBX_PM1_ADDR
    #define    MST_CODEC_DBX_PM1_ADDR               0
    #define    MST_CODEC_DBX_PM1_SIZE               0
    #define    mst_codec_dbx_pm1                    0
#endif
#ifndef    MST_CODEC_DBX_PM2_ADDR
    #define    MST_CODEC_DBX_PM2_ADDR               0
    #define    MST_CODEC_DBX_PM2_SIZE               0
    #define    mst_codec_dbx_pm2                    0
#endif
#ifndef    MST_CODEC_DBX_PM3_ADDR
    #define    MST_CODEC_DBX_PM3_ADDR               0
    #define    MST_CODEC_DBX_PM3_SIZE               0
    #define    mst_codec_dbx_pm3                    0
#endif
#ifndef    MST_CODEC_DBX_PM4_ADDR
    #define    MST_CODEC_DBX_PM4_ADDR               0
    #define    MST_CODEC_DBX_PM4_SIZE               0
    #define    mst_codec_dbx_pm4                    0
#endif


//===========================================================================
// DSP Load code Table
//===========================================================================
AUDIO_ALG_INFO    SE_SYSTEM_LoadCodeTable[ ]=
{        {
        MST_CODEC_PM1_ADDR, MST_CODEC_PM1_SIZE, mst_codec_pm1,
        MST_CODEC_PM2_ADDR, MST_CODEC_PM2_SIZE, mst_codec_pm2,
        MST_CODEC_PM3_ADDR, MST_CODEC_PM3_SIZE, mst_codec_pm3,
        MST_CODEC_PM4_ADDR, MST_CODEC_PM4_SIZE, mst_codec_pm4,
        "SE_SYSTEM",},
};

//==============================================
//==============================================
AUDIO_ALG_INFO    XPCM_LoadCodeTable[ ]=
{        {
        MST_CODEC_XPCM_PM1_ADDR, MST_CODEC_XPCM_PM1_SIZE, mst_codec_xpcm_pm1,
        MST_CODEC_XPCM_PM2_ADDR, MST_CODEC_XPCM_PM2_SIZE, mst_codec_xpcm_pm2,
        MST_CODEC_XPCM_PM3_ADDR, MST_CODEC_XPCM_PM3_SIZE, mst_codec_xpcm_pm3,
        MST_CODEC_XPCM_PM4_ADDR, MST_CODEC_XPCM_PM4_SIZE, mst_codec_xpcm_pm4,
        "XPCM",},
};
//==============================================
AUDIO_ALG_INFO    MP3_LoadCodeTable[ ]=
{        {
        MST_CODEC_MP3_PM1_ADDR, MST_CODEC_MP3_PM1_SIZE, mst_codec_mp3_pm1,
        MST_CODEC_MP3_PM2_ADDR, MST_CODEC_MP3_PM2_SIZE, mst_codec_mp3_pm2,
        MST_CODEC_MP3_PM3_ADDR, MST_CODEC_MP3_PM3_SIZE, mst_codec_mp3_pm3,
        MST_CODEC_MP3_PM4_ADDR, MST_CODEC_MP3_PM4_SIZE, mst_codec_mp3_pm4,
        "MP3",},
};
//==============================================
AUDIO_ALG_INFO    MPEG_LoadCodeTable[ ]=
{        {
        MST_CODEC_MPEG_PM1_ADDR, MST_CODEC_MPEG_PM1_SIZE, mst_codec_mpeg_pm1,
        MST_CODEC_MPEG_PM2_ADDR, MST_CODEC_MPEG_PM2_SIZE, mst_codec_mpeg_pm2,
        MST_CODEC_MPEG_PM3_ADDR, MST_CODEC_MPEG_PM3_SIZE, mst_codec_mpeg_pm3,
        MST_CODEC_MPEG_PM4_ADDR, MST_CODEC_MPEG_PM4_SIZE, mst_codec_mpeg_pm4,
        "MPEG",},
};
//==============================================
AUDIO_ALG_INFO    AC3P_LoadCodeTable[ ]=
{        {
        MST_CODEC_AC3P_PM1_ADDR, MST_CODEC_AC3P_PM1_SIZE, mst_codec_ac3p_pm1,
        MST_CODEC_AC3P_PM2_ADDR, MST_CODEC_AC3P_PM2_SIZE, mst_codec_ac3p_pm2,
        MST_CODEC_AC3P_PM3_ADDR, MST_CODEC_AC3P_PM3_SIZE, mst_codec_ac3p_pm3,
        MST_CODEC_AC3P_PM4_ADDR, MST_CODEC_AC3P_PM4_SIZE, mst_codec_ac3p_pm4,
        "AC3P",},
};
//==============================================
AUDIO_ALG_INFO    MS10_DDT_LoadCodeTable[ ]=
{        {
        MST_CODEC_MS10_DDT_PM1_ADDR, MST_CODEC_MS10_DDT_PM1_SIZE, mst_codec_ms10_ddt_pm1,
        MST_CODEC_MS10_DDT_PM2_ADDR, MST_CODEC_MS10_DDT_PM2_SIZE, mst_codec_ms10_ddt_pm2,
        MST_CODEC_MS10_DDT_PM3_ADDR, MST_CODEC_MS10_DDT_PM3_SIZE, mst_codec_ms10_ddt_pm3,
        MST_CODEC_MS10_DDT_PM4_ADDR, MST_CODEC_MS10_DDT_PM4_SIZE, mst_codec_ms10_ddt_pm4,
        "MS10_DDT",},
};
//==============================================
AUDIO_ALG_INFO    GAAC_LoadCodeTable[ ]=
{        {
        MST_CODEC_GAAC_PM1_ADDR, MST_CODEC_GAAC_PM1_SIZE, mst_codec_gaac_pm1,
        MST_CODEC_GAAC_PM2_ADDR, MST_CODEC_GAAC_PM2_SIZE, mst_codec_gaac_pm2,
        MST_CODEC_GAAC_PM3_ADDR, MST_CODEC_GAAC_PM3_SIZE, mst_codec_gaac_pm3,
        MST_CODEC_GAAC_PM4_ADDR, MST_CODEC_GAAC_PM4_SIZE, mst_codec_gaac_pm4,
        "GAAC",},
};
//==============================================
AUDIO_ALG_INFO    WMA_PRO_LoadCodeTable[ ]=
{        {
        MST_CODEC_WMA_PRO_PM1_ADDR, MST_CODEC_WMA_PRO_PM1_SIZE, mst_codec_wma_pro_pm1,
        MST_CODEC_WMA_PRO_PM2_ADDR, MST_CODEC_WMA_PRO_PM2_SIZE, mst_codec_wma_pro_pm2,
        MST_CODEC_WMA_PRO_PM3_ADDR, MST_CODEC_WMA_PRO_PM3_SIZE, mst_codec_wma_pro_pm3,
        MST_CODEC_WMA_PRO_PM4_ADDR, MST_CODEC_WMA_PRO_PM4_SIZE, mst_codec_wma_pro_pm4,
        "WMA_PRO",},
};
//==============================================
AUDIO_ALG_INFO    DTS_DMP_LoadCodeTable[ ]=
{        {
        MST_CODEC_DTS_DMP_PM1_ADDR, MST_CODEC_DTS_DMP_PM1_SIZE, mst_codec_dts_dmp_pm1,
        MST_CODEC_DTS_DMP_PM2_ADDR, MST_CODEC_DTS_DMP_PM2_SIZE, mst_codec_dts_dmp_pm2,
        MST_CODEC_DTS_DMP_PM3_ADDR, MST_CODEC_DTS_DMP_PM3_SIZE, mst_codec_dts_dmp_pm3,
        MST_CODEC_DTS_DMP_PM4_ADDR, MST_CODEC_DTS_DMP_PM4_SIZE, mst_codec_dts_dmp_pm4,
        "DTS_DMP",},
};
//==============================================
AUDIO_ALG_INFO    DTS_LBR_LoadCodeTable[ ]=
{        {
        MST_CODEC_DTS_LBR_PM1_ADDR, MST_CODEC_DTS_LBR_PM1_SIZE, mst_codec_dts_lbr_pm1,
        MST_CODEC_DTS_LBR_PM2_ADDR, MST_CODEC_DTS_LBR_PM2_SIZE, mst_codec_dts_lbr_pm2,
        MST_CODEC_DTS_LBR_PM3_ADDR, MST_CODEC_DTS_LBR_PM3_SIZE, mst_codec_dts_lbr_pm3,
        MST_CODEC_DTS_LBR_PM4_ADDR, MST_CODEC_DTS_LBR_PM4_SIZE, mst_codec_dts_lbr_pm4,
        "DTS_LBR",},
};
//==============================================
AUDIO_ALG_INFO    RA8LBR_LoadCodeTable[ ]=
{        {
        MST_CODEC_RA8LBR_PM1_ADDR, MST_CODEC_RA8LBR_PM1_SIZE, mst_codec_ra8lbr_pm1,
        MST_CODEC_RA8LBR_PM2_ADDR, MST_CODEC_RA8LBR_PM2_SIZE, mst_codec_ra8lbr_pm2,
        MST_CODEC_RA8LBR_PM3_ADDR, MST_CODEC_RA8LBR_PM3_SIZE, mst_codec_ra8lbr_pm3,
        MST_CODEC_RA8LBR_PM4_ADDR, MST_CODEC_RA8LBR_PM4_SIZE, mst_codec_ra8lbr_pm4,
        "RA8LBR",},
};
//==============================================
AUDIO_ALG_INFO    VORBIS_LoadCodeTable[ ]=
{        {
        MST_CODEC_VORBIS_PM1_ADDR, MST_CODEC_VORBIS_PM1_SIZE, mst_codec_vorbis_pm1,
        MST_CODEC_VORBIS_PM2_ADDR, MST_CODEC_VORBIS_PM2_SIZE, mst_codec_vorbis_pm2,
        MST_CODEC_VORBIS_PM3_ADDR, MST_CODEC_VORBIS_PM3_SIZE, mst_codec_vorbis_pm3,
        MST_CODEC_VORBIS_PM4_ADDR, MST_CODEC_VORBIS_PM4_SIZE, mst_codec_vorbis_pm4,
        "VORBIS",},
};
//==============================================
AUDIO_ALG_INFO    AMR_NB_LoadCodeTable[ ]=
{        {
        MST_CODEC_AMR_NB_PM1_ADDR, MST_CODEC_AMR_NB_PM1_SIZE, mst_codec_amr_nb_pm1,
        MST_CODEC_AMR_NB_PM2_ADDR, MST_CODEC_AMR_NB_PM2_SIZE, mst_codec_amr_nb_pm2,
        MST_CODEC_AMR_NB_PM3_ADDR, MST_CODEC_AMR_NB_PM3_SIZE, mst_codec_amr_nb_pm3,
        MST_CODEC_AMR_NB_PM4_ADDR, MST_CODEC_AMR_NB_PM4_SIZE, mst_codec_amr_nb_pm4,
        "AMR_NB",},
};
//==============================================
AUDIO_ALG_INFO    AMR_WB_LoadCodeTable[ ]=
{        {
        MST_CODEC_AMR_WB_PM1_ADDR, MST_CODEC_AMR_WB_PM1_SIZE, mst_codec_amr_wb_pm1,
        MST_CODEC_AMR_WB_PM2_ADDR, MST_CODEC_AMR_WB_PM2_SIZE, mst_codec_amr_wb_pm2,
        MST_CODEC_AMR_WB_PM3_ADDR, MST_CODEC_AMR_WB_PM3_SIZE, mst_codec_amr_wb_pm3,
        MST_CODEC_AMR_WB_PM4_ADDR, MST_CODEC_AMR_WB_PM4_SIZE, mst_codec_amr_wb_pm4,
        "AMR_WB",},
};
//==============================================
AUDIO_ALG_INFO    DRAD_LoadCodeTable[ ]=
{        {
        MST_CODEC_DRAD_PM1_ADDR, MST_CODEC_DRAD_PM1_SIZE, mst_codec_drad_pm1,
        MST_CODEC_DRAD_PM2_ADDR, MST_CODEC_DRAD_PM2_SIZE, mst_codec_drad_pm2,
        MST_CODEC_DRAD_PM3_ADDR, MST_CODEC_DRAD_PM3_SIZE, mst_codec_drad_pm3,
        MST_CODEC_DRAD_PM4_ADDR, MST_CODEC_DRAD_PM4_SIZE, mst_codec_drad_pm4,
        "DRAD",},
};
//==============================================
AUDIO_ALG_INFO    FLAC_LoadCodeTable[ ]=
{        {
        MST_CODEC_FLAC_PM1_ADDR, MST_CODEC_FLAC_PM1_SIZE, mst_codec_flac_pm1,
        MST_CODEC_FLAC_PM2_ADDR, MST_CODEC_FLAC_PM2_SIZE, mst_codec_flac_pm2,
        MST_CODEC_FLAC_PM3_ADDR, MST_CODEC_FLAC_PM3_SIZE, mst_codec_flac_pm3,
        MST_CODEC_FLAC_PM4_ADDR, MST_CODEC_FLAC_PM4_SIZE, mst_codec_flac_pm4,
        "FLAC",},
};
//==============================================
AUDIO_ALG_INFO    PALSUM_LoadCodeTable[ ]=
{        {
        MST_CODEC_PALSUM_PM1_ADDR, MST_CODEC_PALSUM_PM1_SIZE, mst_codec_palsum_pm1,
        MST_CODEC_PALSUM_PM2_ADDR, MST_CODEC_PALSUM_PM2_SIZE, mst_codec_palsum_pm2,
        MST_CODEC_PALSUM_PM3_ADDR, MST_CODEC_PALSUM_PM3_SIZE, mst_codec_palsum_pm3,
        MST_CODEC_PALSUM_PM4_ADDR, MST_CODEC_PALSUM_PM4_SIZE, mst_codec_palsum_pm4,
        "PALSUM",},
};
//==============================================
AUDIO_ALG_INFO    BTSC_LoadCodeTable[ ]=
{        {
        MST_CODEC_BTSC_PM1_ADDR, MST_CODEC_BTSC_PM1_SIZE, mst_codec_btsc_pm1,
        MST_CODEC_BTSC_PM2_ADDR, MST_CODEC_BTSC_PM2_SIZE, mst_codec_btsc_pm2,
        MST_CODEC_BTSC_PM3_ADDR, MST_CODEC_BTSC_PM3_SIZE, mst_codec_btsc_pm3,
        MST_CODEC_BTSC_PM4_ADDR, MST_CODEC_BTSC_PM4_SIZE, mst_codec_btsc_pm4,
        "BTSC",},
};
//==============================================
AUDIO_ALG_INFO    TSHD_LoadCodeTable[ ]=
{        {
        MST_CODEC_TSHD_PM1_ADDR, MST_CODEC_TSHD_PM1_SIZE, mst_codec_tshd_pm1,
        MST_CODEC_TSHD_PM2_ADDR, MST_CODEC_TSHD_PM2_SIZE, mst_codec_tshd_pm2,
        MST_CODEC_TSHD_PM3_ADDR, MST_CODEC_TSHD_PM3_SIZE, mst_codec_tshd_pm3,
        MST_CODEC_TSHD_PM4_ADDR, MST_CODEC_TSHD_PM4_SIZE, mst_codec_tshd_pm4,
        "TSHD",},
};
//==============================================
AUDIO_ALG_INFO    TSXT_LoadCodeTable[ ]=
{        {
        MST_CODEC_TSXT_PM1_ADDR, MST_CODEC_TSXT_PM1_SIZE, mst_codec_tsxt_pm1,
        MST_CODEC_TSXT_PM2_ADDR, MST_CODEC_TSXT_PM2_SIZE, mst_codec_tsxt_pm2,
        MST_CODEC_TSXT_PM3_ADDR, MST_CODEC_TSXT_PM3_SIZE, mst_codec_tsxt_pm3,
        MST_CODEC_TSXT_PM4_ADDR, MST_CODEC_TSXT_PM4_SIZE, mst_codec_tsxt_pm4,
        "TSXT",},
};
//==============================================
AUDIO_ALG_INFO    PURESND_LoadCodeTable[ ]=
{        {
        MST_CODEC_PURESND_PM1_ADDR, MST_CODEC_PURESND_PM1_SIZE, mst_codec_puresnd_pm1,
        MST_CODEC_PURESND_PM2_ADDR, MST_CODEC_PURESND_PM2_SIZE, mst_codec_puresnd_pm2,
        MST_CODEC_PURESND_PM3_ADDR, MST_CODEC_PURESND_PM3_SIZE, mst_codec_puresnd_pm3,
        MST_CODEC_PURESND_PM4_ADDR, MST_CODEC_PURESND_PM4_SIZE, mst_codec_puresnd_pm4,
        "PURESND",},
};
//==============================================
AUDIO_ALG_INFO    BONGIOVIDPS_LoadCodeTable[ ]=
{        {
        MST_CODEC_DPS_PM1_ADDR, MST_CODEC_DPS_PM1_SIZE, mst_codec_dps_pm1,
        MST_CODEC_DPS_PM2_ADDR, MST_CODEC_DPS_PM2_SIZE, mst_codec_dps_pm2,
        MST_CODEC_DPS_PM3_ADDR, MST_CODEC_DPS_PM3_SIZE, mst_codec_dps_pm3,
        MST_CODEC_DPS_PM4_ADDR, MST_CODEC_DPS_PM4_SIZE, mst_codec_dps_pm4,
        "BONGIOVI DPS",},
};
//==============================================
AUDIO_ALG_INFO    DEC_LoadCodeTable[ ]=
{        {
        MST_CODEC_DEC_PM1_ADDR, MST_CODEC_DEC_PM1_SIZE, mst_codec_dec_pm1,
        MST_CODEC_DEC_PM2_ADDR, MST_CODEC_DEC_PM2_SIZE, mst_codec_dec_pm2,
        MST_CODEC_DEC_PM3_ADDR, MST_CODEC_DEC_PM3_SIZE, mst_codec_dec_pm3,
        MST_CODEC_DEC_PM4_ADDR, MST_CODEC_DEC_PM4_SIZE, mst_codec_dec_pm4,
        "DEC",},
};
//==============================================
AUDIO_ALG_INFO    DDE_LoadCodeTable[ ]=
{        {
        MST_CODEC_DDE_PM1_ADDR, MST_CODEC_DDE_PM1_SIZE, mst_codec_dde_pm1,
        MST_CODEC_DDE_PM2_ADDR, MST_CODEC_DDE_PM2_SIZE, mst_codec_dde_pm2,
        MST_CODEC_DDE_PM3_ADDR, MST_CODEC_DDE_PM3_SIZE, mst_codec_dde_pm3,
        MST_CODEC_DDE_PM4_ADDR, MST_CODEC_DDE_PM4_SIZE, mst_codec_dde_pm4,
        "DDE",},
};
//==============================================
AUDIO_ALG_INFO    DBX_LoadCodeTable[ ]=
{        {
        MST_CODEC_DBX_PM1_ADDR, MST_CODEC_DBX_PM1_SIZE, mst_codec_dbx_pm1,
        MST_CODEC_DBX_PM2_ADDR, MST_CODEC_DBX_PM2_SIZE, mst_codec_dbx_pm2,
        MST_CODEC_DBX_PM3_ADDR, MST_CODEC_DBX_PM3_SIZE, mst_codec_dbx_pm3,
        MST_CODEC_DBX_PM4_ADDR, MST_CODEC_DBX_PM4_SIZE, mst_codec_dbx_pm4,
        "DBX",},
};


///////////////////////////////////////////////////////////////////////////////////////
#endif // _DECODER_INFO_H_