1 #ifndef __PLATFORM_PROJ_INCLUDE_FILE__ 2 #define __PLATFORM_PROJ_INCLUDE_FILE__ 3 4 #include "ddr_config.h" 5 #include "mbox_decR2.h" 6 7 #define DEC_R2_CLOCK 432000000 8 9 #define DEFAULT_ES_BLOCK_LEVEL 0x1800 10 #define DEFAULT_PCM_BLOCK_LEVEL 0x20000 11 #define DEFAULT_AVSYNC_OFFSET 0x3138 //AVSYNC delay in DTV: 140ms, Unit: 33bits 12 #define DEFAULT_SPDIF_OFFSET 0xC00 // 13 #define DEFAULT_STOP_PARSER_ES_LEVEL 0x10000 14 #define DEFAULT_FILE_HAND_SHAKE_SIZE 0x800 15 16 #define MPG_AV_DEFAULT_DELAY 0x3E1E 17 #define AC3_AV_DEFAULT_DELAY 0x4300 18 #define AAC_AV_DEFAULT_DELAY 0x327E 19 20 #define DELAY_UPPER_LIMIT 0x6978 21 #define DELAY_LOWER_LIMIT 0xA8C 22 23 #ifdef __BUILD_FOR_R2__ 24 /*********************************************************** 25 * Software Setting 26 ***********************************************************/ 27 #define R2_SIMULATION 0 28 #define R2_BUILD_IN_TEST_PATTERN 0 29 30 #define R2_DECODER_EN (1) 31 #define R2_DECODER1_FORCE_MCH_OUTPUT (1) 32 #define R2_DECODER1_FORCE_2CH_OUTPUT (0) 33 #define R2_DECODER2_FORCE_MCH_OUTPUT (1) 34 #define R2_DECODER2_FORCE_2CH_OUTPUT (0) 35 #ifdef __aeon__ 36 #define R2_DECODER1_OUTPUT_BY_DSP (0) 37 #define R2_DECODER2_OUTPUT_BY_DSP (0) 38 #else 39 #define R2_DECODER1_OUTPUT_BY_DSP (0) 40 #define R2_DECODER2_OUTPUT_BY_DSP (0) 41 #endif 42 43 #define PRE__SOUND_PROCESS_EN 0 44 #define POST_SOUND_PROCESS_EN 0 45 #define FD230_EN 0 46 47 #define R2_AD_ENABLE 1 48 #define R2_DISABLE_PARSERAB 0 49 #define PARSER_PUSI_SUPPORT 1 50 #define PASDMA_ENABLE 0 51 #define PASDROP_ENABLE 0 52 53 #define R2_INTERRUPT_PRINTF 54 55 #if (R2_SIMULATION == 1) 56 #define R2_SIM_DEC1_AUDIO_TYPE 1 // 1: AC3, 5: AAC, 3: mp3 (use ES1(md) and ES2(ad)) 57 #define R2_SIM_DEC2_AUDIO_TYPE 1 // 1: AC3, 5: AAC, 3: mp3 (use ES3(md) and ES4(ad)) 58 #define R2_SIM_DEC1_COMMAND_ENABLE 0x11 //0: disable, 0x01 : MD only, 0x11: MD+AD 59 #define R2_SIM_DEC2_COMMAND_ENABLE 0 //0: disable, 0x01 : MD only, 0x11: MD+AD 60 #undef R2_INTERRUPT_PRINTF 61 #endif 62 63 /*********************************************************** 64 * wrapper define for each IP 65 ***********************************************************/ 66 #define DEC_R2_DQMEM_SIZE 32 //unit is kbytes 67 #define DEC_R2_DQMEM_ADDR 0xFFFF0000 68 69 #define R2_DEC_HDMI_OUTPUT 1 // 1:HDMI_Nonpcm_Tx or HDMI_ARC 70 #define UNI_DECODE_DONE_NON_6_BLOCK 1 71 #define REMOVE_DTS_TRANSCODER 0 72 #define REMOVE_MS11_DDENCODE 0 73 #define HEAAC_SPDIF_BYPASS 1 74 #define SND_R2_SUPPORT_DDENC 1 75 #define SND_DSP_SUPPORT_DDENC 1 76 #define SND_R2_SUPPORT_DDPENC 1 77 #define SND_DSP_SUPPORT_DPDENC 1 78 #define SND_R2_SUPPORT_DTSENC 1 79 #define SND_DSP_SUPPORT_DTSENC 1 80 #define USE_SPDIF_REPLACE_HDMI 1 81 #define STREAMING_LOW_LATENCY_LIMITER 0 82 83 #define L2_CRC_ERR_MUTE_NUM 2 84 #define L2_SYNCWORD_ERR_MUTE_NUM 2 85 #define DDP_HDMI_FILL256_SAMPLE_BEFORE_FIRST_FRAME 0 86 #define SUPPORT_DRCLINE_MPEG_LEVEL_MODIFY 1 87 /*********************************************************** 88 * Hardware Setting 89 ***********************************************************/ 90 #define LOG2_BYTES_IN_LINE 4 91 #define BYTE_IN_LINE (1<<LOG2_BYTES_IN_LINE) 92 #define BYTE_IN_LINE_MASK (BYTE_IN_LINE - 1) 93 #define ALIGN_TO_MIU_LINE(x) (x&BYTE_IN_LINE_MASK)?((x+BYTE_IN_LINE)&(~BYTE_IN_LINE_MASK)):x 94 95 #define HAL_ICACHE_SIZE 8192 96 #define HAL_ICACHE_LINE_SIZE 64 97 #define HAL_ICACHE_WAY 4 98 99 #define HAL_DCACHE_SIZE 8192 100 #define HAL_DCACHE_LINE_SIZE 64 101 #define HAL_DCACHE_WAY 4 102 103 /* D_PREFETCH */ 104 #define DC_WR_ALLOCATE_EN 1 // R2 D-Cache write-allocate 105 #define D_PREFETCH_NUM 0 //Macan has no this feature 106 #define R2_SPRA_DCU_PREFETCH (118) //118 for DCU prefetch 107 108 /* I_PREFETCH */ 109 #define I_PREFETCH_NUM 0 //Macan has no this feature 110 #define R2_SPRA_ICU_PREFETCH (119) //119 for ICU prefetch 111 112 /* interrupt */ 113 #define NR_IRQS 20 114 #define IRQ13_UART 0x13//19 115 116 /*********************************************************** 117 * 118 ***********************************************************/ 119 #define MAX_PRINTF_BUF 0x8000 120 #define decSysFunc_start //dbg_func_entries++ 121 #define decSysFunc_end //dbg_func_entries-- 122 #define decSysPrint(x) //{int xxx=0; for( xxx=0; xxx<dbg_func_entries; xxx++) printf("\t");} x 123 #ifdef WIN32 124 #define decSysPrint_R2(x) 125 #else 126 #define decSysPrint_R2(x) x 127 #endif 128 129 #define CHK_BUFF_SUM(addr, size) { \ 130 int xxx=0; \ 131 unsigned char *p = (unsigned char *) addr; \ 132 unsigned char sum = 0; \ 133 for (xxx=0; xxx<size; xxx++) \ 134 sum += p[xxx]; \ 135 printf("sum = %x ", sum); \ 136 } 137 138 #define CHK_BUFF_XOR(addr, size) { \ 139 int xxx=0; \ 140 unsigned char *p = (unsigned char *) addr; \ 141 unsigned char sum = 0; \ 142 for (xxx=0; xxx<size; xxx++) \ 143 sum ^= p[xxx]; \ 144 printf("xor = %x ", sum); \ 145 } 146 147 /*********************************************************** 148 * DDR Setting 149 ***********************************************************/ 150 #ifdef __aeon__ 151 #define OFFSET_R2 0 152 #else 153 #define OFFSET_R2 ((unsigned int)&chip_audio_memory_buf) 154 #endif 155 156 #define OFFSET_R2_TO_ASNDR2 (OFFSET_R2 + ADEC__R2_DDR_SIZE) 157 #define OFFSET_R2_TO_ASNDDSP (OFFSET_R2 + ADEC__R2_DDR_SIZE + ASND__R2_DDR_SIZE) 158 #define OFFSET_R2_TO_COMM_DDR (OFFSET_R2 + ADEC__R2_DDR_SIZE +ASND__R2_DDR_SIZE + ASND_DSP_DDR_SIZE) 159 160 /* DECODER DDR */ 161 #define DEC1_METADATA1_BUF (OFFSET_R2_TO_ASNDDSP + OFFSET_DEC1_METADATA1_DRAM_ADDR) 162 #define DEC1_METADATA2_BUF (OFFSET_R2_TO_ASNDDSP + OFFSET_DEC1_METADATA2_DRAM_ADDR) 163 #define DEC1_METADATA3_BUF (OFFSET_R2_TO_ASNDDSP + OFFSET_DEC1_METADATA3_DRAM_ADDR) 164 165 #define DEC2_METADATA1_BUF (OFFSET_R2_TO_ASNDDSP + OFFSET_DEC2_METADATA1_DRAM_ADDR) 166 #define DEC2_METADATA2_BUF (OFFSET_R2_TO_ASNDDSP + OFFSET_DEC2_METADATA2_DRAM_ADDR) 167 #define DEC2_METADATA3_BUF (OFFSET_R2_TO_ASNDDSP + OFFSET_DEC2_METADATA3_DRAM_ADDR) 168 //// ES & PCM //// 169 #if 1 170 #define ES1_DRAM_ADDR (OFFSET_R2_TO_ASNDDSP + OFFSET_ES1_DRAM_ADDR) 171 #define ES2_DRAM_ADDR (OFFSET_R2_TO_ASNDDSP + OFFSET_ES2_DRAM_ADDR) 172 #define ES3_DRAM_ADDR (OFFSET_R2_TO_ASNDDSP + OFFSET_ES3_DRAM_ADDR) 173 #define ES4_DRAM_ADDR (OFFSET_R2_TO_ASNDDSP + OFFSET_ES4_DRAM_ADDR) 174 #define PCM1_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM1_DRAM_ADDR) 175 #define PCM2_DRAM_ADDR (OFFSET_R2_TO_COMM_DDR + OFFSET_PCM2_DRAM_ADDR) 176 #endif 177 178 //// HDMI non-PCM //// 179 #if (R2_DEC_HDMI_OUTPUT == 1) 180 #define BUF_HDMI_OFFSET OFFSET_HDMI_NONPCM_DRAM_BASE 181 #define BUF_HDMI_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_HDMI_OFFSET) 182 #define BUF_HDMI_SIZE HDMI_NONPCM_DRAM_SIZE 183 #endif 184 185 #if 0 186 #define DSP1_ENC_RAW_OFFSET 0x334000 187 #define DSP1_ENC_RAW_BUFADDR (OFFSET_R2_TO_COMM_DDR + DSP1_ENC_RAW_OFFSET) 188 #define DSP1_ENC_RAW_BUFSIZE 0x38E00 189 #endif 190 191 /* sound effect related DDR */ 192 193 /* pre sound DDR */ 194 //#define BUF_PCMIN_ADDR (OFFSET_R2_TO_ASNDDSP + OFFSET_SE_MAIN_IN_DRAM_ADDR) 195 //#define BUF_PCMIN_SIZE SE_MAIN_IN_DRAM_SIZE 196 197 /* post sound DDR */ 198 //#define BUF_PCMIN2_ADDR (OFFSET_R2_TO_ASNDDSP + OFFSET_SE_MAIN_OUT_DRAM_ADDR) 199 //#define BUF_PCMIN2_SIZE SE_MAIN_OUT_DRAM_SIZE 200 201 #define BUF_SPDIF_OFFSET OFFSET_SPDIF_NONPCM_DRAM_BASE 202 #define BUF_SPDIF_ADDR (OFFSET_R2_TO_COMM_DDR+ BUF_SPDIF_OFFSET) 203 #define BUF_SPDIF_SIZE SPDIF_NONPCM_DRAM_SIZE 204 205 /* ENCODER DDR */ 206 #define DDENC_METADATA_OFFSET OFFSET_DDENC_METADATA_DRAM_ADDR 207 #define DDENC_METADATA_ADDR (OFFSET_R2_TO_ASNDDSP+ DDENC_METADATA_OFFSET) 208 #define DDENC_METADATA_SIZE DDENC_METADATA_DRAM_SIZE 209 210 /* MISC */ 211 212 /*********************************************************** 213 * Decoder threshold settings 214 ***********************************************************/ 215 #define R2_OUTPUT_ENC_RAW_DATA 0 216 217 #define DEC_OUTPUT_BYTES_PER_SAMPLE 2 218 #define DEC_OUTPUT_DMX_CHANNELS 2 219 #define DEC_OUTPUT_BYTES_PER_DMX_SAMPLE 4 220 #define DEC_OUTPUT_MCH_CHANNELS 6 //order : L / C / R / Ls / Rs / LFE 221 #define DEC_OUTPUT_OMX_MCH_CHANNELS 10 222 223 #define AVSYNC_TD_TIMEOUT_THRESHOLD 0x36EE8/2 // 2500ms !?? Threshold?? STC ? APTS ????, ??? FreeRun 224 #define AVSYNC_WAIT_STC_TD 90*100/2 // 100 ms !?? Threshold?? STC ?? APTS ???, ??????STC 225 #define AVSYNC_SKIP_FRM_TD 90*45/2 // 45 ms !?? Threshold?? STC ?? APTS ???, ??skip frame??STC 226 #define SYS_DEC_HDMIPLAY_PCM_LEVEL 45*48 //(1536-64)*48 //0 // 45 ms 227 #define AVSYNC_11172_OVERFLOW_THRESHOLD 0x6D3A06 // 0x7FFFFFFF/300 228 // 229 #define SYS_DEC1_WAIT_1ST_PTS_TIMEOUT_PCM_LEVEL 700*48 // 700ms (should small than "SYS_DEC_STOP_DECODE_PCM_LEVEL") 230 #define SYS_DEC1_WAIT_STC_TIMEOUT_PCM_LEVEL 700*48 // 700ms (should small than "SYS_DEC_STOP_DECODE_PCM_LEVEL") 231 #define SYS_DEC1_FREEPLAY_PCM_LEVEL 45*48 // 45ms (should small than "SYS_DEC_STOP_DECODE_PCM_LEVEL") 232 #define SYS_DEC1_STOP_DECODE_PCM_LEVEL (1024-64)*48 //(1536-64)*DEC_OUTPUT_1MS_48K_SIZE //(1024-64)*DEC_OUTPUT_1MS_48K_SIZE // 1024ms (should small than "SYS_DEC_STOP_DECODE_PCM_LEVEL") 233 #define SYS_DEC1_STOP_DECODE_PCM_LEVEL_OMX 1728*48 234 #define SYS_DEC1_STOP_DECODE_PCM_LEVEL_MM_TS 120*48 235 #define SYS_DEC1_STOP_DECODE_PCM_LEVEL_DTV ((PCM1_DRAM_SIZE/48000/2/10) * 1000 -64)*48 236 #define SYS_DEC1_WAIT_STC_TIMEOUT_ES_LEVEL 0x8000 237 #define SYS_DEC1_WAIT_1ST_PTS_TIMEOUT_ES_LEVEL 0x2000 238 239 #define SYS_DEC_SLEEP_PCM_LEVEL 60*48 // 60ms 240 #define SYS_DEC_WAIT_1st_PTS_FRMCNT 32 241 #define SYS_AD_NOSIGNAL_THRESHOLD 128 242 #define SYS_DEC_DTV_FREEPLAY_PCM_LEVEL 64*48 243 244 #define SYS_DEC_MM_TD_TIMEOUT_THRESHOLD_UP_LIMIT (200*90000/2) 245 #define SYS_DEC_MM_TD_TIMEOUT_THRESHOLD_DOWN_LIMIT (-30*90000/2) 246 247 /*********************************************************** 248 * OMX nonPCM threshold settings 249 ***********************************************************/ 250 #define OMX_PCM_COMPARE_LEVEL 0x4800 //SmpPerCH = 0x1200*10/2/2 251 #define OMX_DEFAULT_ADECID R2_ADEC_ID2 252 #define OMX_THRESHOLD 4 253 #define OMX_NONPCM_START_EN_LEVEL 0x4000 254 #define OMX_NONPCM_STOPSKIP_LEVEL 0x1600 255 #define OMX_PCM_CONSTANT_DELAY 0x0 256 257 /*********************************************************** 258 * Sound effect Setting 259 ***********************************************************/ 260 #define ASND_PROCESS_MODE 2 // 2(adec_acmod_stereo) or 7(adec_acmod_mod32) 261 #define ASND_PROCESS_ITF_UNIT 32 262 #define BYTES_IN_PCM 3 263 264 /* pre sound process */ 265 #define ASND_PRE_PROCESS_BUF_UNIT 256 266 #define ASND_PRE_INPUT_PCM_CH 8 //(RAW DMX + 5.1) 267 268 #define DOWNMIX_2_CH_ORDER 0 269 #define MULTI_5P1_CH_ORDER 2 270 #define ENC_2_CH_ORDER 8 271 #define ECHO_CH_ORDER 10 272 273 /* post sound process */ 274 #define ASND_POST_INPUT_PCM_CH 8 275 #define ASND_POST_PROCESS_BUF_UNIT 256 276 277 #endif //__BUILD_FOR_R2__ 278 279 /*********************************************************** 280 * Mbox Setting 281 ***********************************************************/ 282 //--------------------------------------- 283 /******************* MCU <--> DEC-R2 *******************/ 284 /* MCU -> DEC-R2 */ 285 //// MCU -> DEC-R2 : Common //// 286 #define MBOX_WORD_MCUCMD_PARAMTYPE MBOX_M2D_0380 //generate interrut 287 #define MBOX_BYTE_MCUCMD_ID_SEL MBOX_M2D_0382 288 #define MBOX_BYTE_MCUCMD_Get_OR_Set MBOX_M2D_0382+1 289 #define MBOX_WORD_MCUCMD_PARAM1 MBOX_M2D_0384 290 #define MBOX_WORD_MCUCMD_PARAM2 MBOX_M2D_0386 291 #define MBOX_WORD_R2_CTRL MBOX_M2D_0388 292 #define STREAMING_LOW_LATENCY_LIMITER_EN _BIT_15_ 293 #define MBOX_WORD_R2_SYSTEM_DBG MBOX_M2D_038A 294 /* 295 [ 0] decoder decode frame statue 296 [ 1] decoder output pcm status 297 [ 3] reset measured max AD no signal counter 298 [ 4] omx decode done print 299 [ 8] decoder print info 300 [ 9] measure decoder mips 301 [10] measure miu latency 302 [11] enable wfi mode 303 [12] disable skip frm when doing AV sync 304 [13] disable wait STC when doing AV sync 305 [14] disable calculate increase cPTS in timer 306 */ 307 308 #define MBOX_WORD_DBG_DUMP_DDR_ADDR_HI MBOX_M2D_038C 309 #define MBOX_WORD_DBG_MBOX_VALUE_HI MBOX_M2D_038C 310 #define MBOX_WORD_DBG_MBOX_PRINT_SIZE MBOX_M2D_038C 311 #define MBOX_WORD_DBG_DUMP_DDR_ADDR_LO MBOX_M2D_038E 312 #define MBOX_WORD_DBG_MBOX_VALUE_LO MBOX_M2D_038E 313 #define MBOX_WORD_DBG_DUMP_DDR_SIZE MBOX_M2D_039C 314 #define MBOX_WORD_DBG_MBOX_ADDR MBOX_M2D_039C 315 #define MBOX_BYTE_OMX_NPCM_SYNC_DBG MBOX_M2D_039C+1 316 #define MBOX_BYTE_STATUS_SELECT MBOX_M2D_039E 317 #define MBOX_BYTE_STATUS_SPEED MBOX_M2D_039E+1 318 319 //// MCU -> DEC-R2 : R2 decoder //// 320 #define MBOX_BYTE_DEC_SPDIF_SEL MBOX_M2D_0396 321 #define MBOX_BYTE_DEC1_SEL MBOX_M2D_0398 322 #define MBOX_BYTE_DEC2_SEL MBOX_M2D_039A 323 #define MBOX_BYTE_DEC1_CMD MBOX_M2D_0398+1 324 #define MBOX_BYTE_DEC2_CMD MBOX_M2D_039A+1 325 326 327 /* DEC-R2 -> MCU */ 328 //// DEC-R2 -> MCU : Common //// 329 #define MBOX_WORD_MCU_INTERRUPT MBOX_D2M_03A0 330 #define MBOX_BYTE_PARAM_TOKEN MBOX_D2M_03A2+1 331 #define MBOX_WORD_INFO_VALUE1 MBOX_D2M_03A4 332 #define MBOX_WORD_INFO_VALUE2 MBOX_D2M_03A6 333 #define MBOX_WORD_R2_STATUS MBOX_D2M_03A8 334 #define MBOX_WORD_R2_VERSION MBOX_D2M_03AA 335 #define MBOX_BYTE_R2_DBG_ACK_HI MBOX_D2M_03AC 336 #define MBOX_BYTE_R2_DBG_ACK MBOX_D2M_03AE 337 #define MBOX_BYTE_WHILE_1_CNTR MBOX_D2M_03B2 338 #define MBOX_BYTE_TIMER_CNT MBOX_D2M_03B2+1 339 #define MBOX_BYTE_R2_SPDIF MBOX_D2M_03B4 340 #define MBOX_BYTE_LOADCODE_ACK MBOX_D2M_03B6 341 #define MBOX_BYTE_R2_WFI_CNTR MBOX_D2M_03B8 342 343 /* dec R2 -> MCU */ 344 //// dec R2 -> MCU : Common //// 345 #define MBOX_R2_START_ADDRESS_LO MBOX_R2Reg_82 346 #define MBOX_R2_START_ADDRESS_HI MBOX_R2Reg_84 347 348 #if 0 349 #define MBOX_WORD_R2_HDMI_STATUS MBOX_D2M_03B0 350 #endif 351 352 #ifdef __BUILD_FOR_R2__ 353 /* dec R2 <--> snd R2 */ 354 #define MBPX_D2A_DDENC (MBOX_D2A_IO_1) 355 #define MBPX_D2A_DTSENC (MBOX_D2A_IO_1+1) 356 #define MBPX_D2A_MS12 (MBOX_D2A_IO_2) 357 #define DEC1_MS12_PCMR_ENABLE_BIT 0 358 #define DEC2_MS12_PCMR_ENABLE_BIT 1 359 #define DEC1_MS12_DAP_MCH_BIT 2 360 #define DEC2_MS12_DAP_MCH_BIT 3 361 #define MBPX_D2A_PCM_BUF_RPTR (MBOX_D2A_IO_3) 362 363 /* SND-DSP -> snd R2 */ 364 //// R2 decoder //// 365 #define MBOX_S2D_DSP_TO_R2_COMMAND MBOX_S2D_IO_0 366 #define S2D_CMD_RESET_PCM1_AVSYNC 0x0001 367 #define S2D_CMD_RESET_PCM2_AVSYNC 0x0002 368 369 #define MBOX_S2D_DSP_TO_R2_PARAM MBOX_S2D_IO_1 370 #define MBOX_S2D_R2CMD_RECEIVE_CNT MBOX_S2D_IO_2 371 372 #define MBOX_S2D_PCM1_PLAYCNT MBOX_S2D_IO_3 373 #define MBOX_S2D_PCM1_FIFOCNT MBOX_S2D_IO_4 374 #define MBOX_S2D_PCM1_DRAM_RDPTR MBOX_S2D_IO_5 375 376 #define MBOX_SNDDSP_2_DECR2_ENC_ON_CHIP MBOX_S2D_IO_9 377 378 #define MBOX_SNDR2_2_DECR2_ENC_ON_CHIP MBOX_A2D_IO_0 379 380 #define MBOX_S2D_PCM2_PLAYCNT MBOX_S2D_IO_A 381 #define MBOX_S2D_PCM2_FIFOCNT MBOX_S2D_IO_B 382 #define MBOX_S2D_PCM2_DRAM_RDPTR MBOX_S2D_IO_C 383 384 //#define MBOX_S2D_REG_DECODER_SEL MBOX_S2D_IO_A 385 //#define MBOX_S2D_REG_HDMI_IN_FREQ MBOX_S2D_IO_B 386 387 #define MBOX_S2D_DSPWORD_SPDIF_RDPTR MBOX_S2D_IO_D 388 #define MBOX_S2D_DSPWORD_HDMI_RDPTR MBOX_S2D_IO_6 389 390 #define MBOX_S2D_DSPWORD_IP_AUTH MBOX_S2D_IO_E 391 #define MBOX_S2D_DSPWORD_BOUND_OPTION MBOX_S2D_IO_F 392 393 /* R2 -> SND DSP */ 394 #define MBOX_D2S_PCMISR_CTRL MBOX_D2S_IO_1 395 #define MBOX_R2_PCM1ISR_PLAY_START_BIT _BIT_0_ //--> �o�U�� playSmpFlag / stop / pause �M�w 396 #define MBOX_R2_PCM1ISR_PLAY_MUTE_BIT _BIT_1_ //--> Mute 397 #define MBOX_R2_PCM1ISR_USING_ASINK_ISR_BIT _BIT_2_ 398 #define MBOX_R2_PCM2ISR_PLAY_START_BIT _BIT_8_ 399 #define MBOX_R2_PCM2ISR_PLAY_MUTE_BIT _BIT_9_ 400 #define MBOX_R2_PCM2ISR_USING_ASINK_ISR_BIT _BIT_10_ 401 402 #define MBOX_D2S_PCM1_DRAM_WRPTR MBOX_D2S_IO_2 403 #define MBOX_D2S_PCM1_SYNTH_H MBOX_D2S_IO_3 404 #define MBOX_D2S_PCM1_SYNTH_L MBOX_D2S_IO_4 405 406 #define MBOX_D2S_PCM2_DRAM_WRPTR MBOX_D2S_IO_5 407 #define MBOX_D2S_PCM2_SYNTH_H MBOX_D2S_IO_6 408 #define MBOX_D2S_PCM2_SYNTH_L MBOX_D2S_IO_7 409 410 #define MBOX_D2S_R2_TO_DSP_COMMAND MBOX_D2S_IO_8 411 #define D2S_CMD_UPD_PCM1_MUTECNT _BIT_0_ 412 #define D2S_CMD_CLR_PCM1_PLAYCNT _BIT_1_ 413 #define D2S_CMD_UPD_PCM1_PLAYCNT _BIT_2_ 414 #define D2S_CMD_FLUSH_PCM1_SMPS _BIT_3_ 415 #define D2S_CMD_RESET_PCM1 _BIT_4_ 416 #define D2S_CMD_UPD_PCM2_MUTECNT _BIT_5_ 417 #define D2S_CMD_CLR_PCM2_PLAYCNT _BIT_6_ 418 #define D2S_CMD_UPD_PCM2_PLAYCNT _BIT_7_ 419 #define D2S_CMD_FLUSH_PCM2_SMPS _BIT_8_ 420 #define D2S_CMD_RESET_PCM2 _BIT_9_ 421 422 #define MBOX_D2S_R2_TO_DSP_PARAM MBOX_D2S_IO_9 423 #define MBOX_D2S_DSPWORD_SPDIF_WRPTR MBOX_D2S_IO_A 424 #define MBOX_D2S_DSPWORD_HDMI_WRPTR MBOX_D2S_IO_B 425 426 #define MBOX_D2S_DSPWORD_SPDIF_CTRL MBOX_D2S_IO_C 427 #define MBOX_D2S_DSPWORD_HDMI_CTRL MBOX_D2S_IO_C 428 #define MBOX_HDMI_CTRL_START_BIT _BIT_23_ 429 #define MBOX_HDMI_HBR_MODE_BIT _BIT_20_ 430 #define MBOX_HDMI_CTRL_EN_BIT _BIT_21_ 431 #define MBOX_SPDIF_CTRL_EN_BIT _BIT_17_ 432 #define MBOX_SPDIF_CTRL_START_BIT _BIT_19_ 433 #define MBOX_HDMI_PCM_NONPCM _BIT_7_ 434 #define MBOX_SPDIF_PCM_NONPCM _BIT_6_ 435 #define MBOX_HDMI_NONPCM_OWNER _BIT_4_ 436 #define MBOX_SPDIF_NONPCM_OWNER _BIT_2_ 437 /* 438 [23] HDMI nonPcm Start 439 [22] 440 [21] HDMI nonPcm PlayEnable 441 [20] HDMI HBR mode 442 [19] SPDIF nonPcm Start 443 [18] inform DDEncode to attenuate 4.75dB 444 [17] SPDIF nonPcm PlayEnable 445 [16] 446 [15:12] SPDIF nonPcm sampleRate index 447 // 0: 96K, 1: 88K, 2: 64K 448 // 3: 48K, 4: 44K, 5: 32K 449 // 6: 24K, 7: 22K, 8: 16K 450 // 9: 12K, a: 11K, b: 8K 451 452 [11:8] HDMI nonPcm sampleRate index 453 // 0: 96K, 1: 88K, 2: 64K 454 // 3: 48K, 4: 44K, 5: 32K 455 // 6: 24K, 7: 22K, 8: 16K 456 // 9: 12K, a: 11K, b: 8K 457 // c:192K, d: 176K e: 128K 458 459 [7] HDMI is Pcm or nonPcm 460 [6] SPDIF is Pcm or nonPcm 461 [5:4] hdmi nonPcm owner 462 [3:2] spdif nonPcm owner 463 [0:1] spdif/hdmi PCM attenuator index 464 */ 465 466 467 #define MBOX_D2S_R2_DOLBY_META_DATA MBOX_D2S_IO_D 468 469 #define MBOX_D2S_R2_TO_DSP_ENCODE MBOX_D2S_IO_E 470 #define D2S_CMD_DDENC_ENABLE _BIT_6_ 471 #define D2S_CMD_DTSENC_ENABLE _BIT_5_ 472 #define D2S_LFE_MODE _BIT_4_ 473 #define D2S_AC_MODE _BIT_0_ 474 475 //#define MBOX_D2S_R2_TO_DSP_MISC MBOX_D2S_IO_F 476 // #define D2S_CMD_SOUND_MIXER_DISABLE _BIT_0_ 477 478 /*********************************************************** 479 * SE R2 mailbox 480 ***********************************************************/ 481 #define SNDR2_MBOX_BYTE_R2_DBG_ACK MBOX_A2M_2EAE 482 #define SNDR2_MBOX_BYTE_STATUS_SELECT MBOX_M2A_2E9E 483 #define MBOX_S2A_DSPWORD_PCMIN_WRPTR MBOX_S2A_IO_1 484 #define MBOX_A2S_DSPWORD_PCMOUT_WRPTR MBOX_A2S_IO_1 485 486 #define MBOX_A2S_DSPWORD_HDMI_WRPTR MBOX_A2S_IO_4 487 #define MBOX_A2S_DSPWORD_SPDIF_WRPTR MBOX_A2S_IO_3 488 489 #define MBOX_S2A_DSPWORD_SPDIF_RDPTR MBOX_S2A_IO_3 490 #define MBOX_S2A_DSPWORD_HDMI_RDPTR MBOX_S2A_IO_4 491 #define MBOX_S2A_DSPWORD_IP_AUTH MBOX_S2A_IO_E 492 #define MBOX_S2A_DSPWORD_BOUND_OPTION MBOX_S2A_IO_F 493 /*********************************************************** 494 * DEBUG 495 ***********************************************************/ 496 #define dbg_print(x) x 497 // #define MMTS_REPORT_SCR_INSTEAD 498 499 /*********************************************************** 500 * Hardware patch 501 ***********************************************************/ 502 #define PATCH_0001 0 //Pacth for R2 MAU problem (T8 U01) 503 504 #endif //__BUILD_FOR_R2__ 505 #endif //__PLATFORM_PROJ_INCLUDE_FILE__