1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2 /*
3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4 */
5
6 #define MODULE_TAG "vdpp2"
7
8 #include <sys/ioctl.h>
9 #include <errno.h>
10 #include <math.h>
11
12 #include "mpp_buffer.h"
13 #include "mpp_env.h"
14 #include "mpp_service.h"
15 #include "mpp_platform.h"
16
17 #include "vdpp2.h"
18
19 #define VDPP2_VEP_MAX_WIDTH (1920)
20 #define VDPP2_VEP_MAX_HEIGHT (2048)
21 #define VDPP2_HIST_MAX_WIDTH (4096)
22 #define VDPP2_HIST_MAX_HEIGHT (4096)
23 #define VDPP2_MODE_MIN_WIDTH (128)
24 #define VDPP2_MODE_MIN_HEIGH (128)
25
26 #define VDPP2_HIST_HSD_DISABLE_LIMIT (1920)
27 #define VDPP2_HIST_VSD_DISABLE_LIMIT (1080)
28 #define VDPP2_HIST_VSD_MODE_1_LIMIT (2160)
29
30 RK_U32 vdpp2_debug = 0;
31 /* default es parameters */
32 static RK_S32 diff2conf_lut_x_tmp[9] = {
33 0, 1024, 2048, 3072, 4096, 6144, 8192, 12288, 65535,
34 };
35 static RK_S32 diff2conf_lut_y_tmp[9] = {
36 0, 84, 141, 179, 204, 233, 246, 253, 255,
37 };
38 /* default sharp parameters */
39 static RK_S32 coring_zero_tmp[7] = {
40 5, 5, 8, 5, 8, 5, 5,
41 };
42 static RK_S32 coring_thr_tmp[7] = {
43 40, 40, 40, 24, 26, 30, 26,
44 };
45 static RK_S32 coring_ratio_tmp[7] = {
46 1479, 1188, 1024, 1422, 1024, 1024, 1024,
47 };
48 static RK_S32 gain_pos_tmp[7] = {
49 128, 256, 512, 256, 512, 256, 256,
50 };
51 static RK_S32 gain_neg_tmp[7] = {
52 128, 256, 512, 256, 512, 256, 256,
53 };
54 static RK_S32 limit_ctrl_pos0_tmp[7] = {
55 64, 64, 64, 64, 64, 64, 64,
56 };
57 static RK_S32 limit_ctrl_pos1_tmp[7] = {
58 120, 120, 120, 120, 120, 120, 120,
59 };
60 static RK_S32 limit_ctrl_neg0_tmp[7] = {
61 64, 64, 64, 64, 64, 64, 64,
62 };
63 static RK_S32 limit_ctrl_neg1_tmp[7] = {
64 120, 120, 120, 120, 120, 120, 120,
65 };
66 static RK_S32 limit_ctrl_ratio_tmp[7] = {
67 128, 128, 128, 128, 128, 128, 128,
68 };
69 static RK_S32 limit_ctrl_bnd_pos_tmp[7] = {
70 81, 131, 63, 81, 63, 63, 63,
71 };
72 static RK_S32 limit_ctrl_bnd_neg_tmp[7] = {
73 81, 131, 63, 81, 63, 63, 63,
74 };
75 static RK_S32 lum_grd_tmp[6] = {
76 0, 200, 300, 860, 960, 1023
77 };
78 static RK_S32 lum_val_tmp[6] = {
79 64, 64, 64, 64, 64, 64,
80 };
81 static RK_S32 adp_grd_tmp[6] = {
82 0, 4, 60, 180, 300, 1023,
83 };
84 static RK_S32 adp_val_tmp[6] = {
85 64, 64, 64, 64, 64, 64,
86 };
87 static RK_S32 var_grd_tmp[6] = {
88 0, 39, 102, 209, 500, 1023,
89 };
90 static RK_S32 var_val_tmp[6] = {
91 64, 64, 64, 64, 64, 64,
92 };
93 static RK_S32 diag_adj_gain_tab_tmp[8] = {
94 6, 7, 8, 9, 10, 11, 12, 13,
95 };
96 static RK_S32 roll_tab_pattern0[16] = {
97 0, 0, 0, 1, 2, 3, 4, 6, 8, 10, 11, 12, 13, 14, 15, 15,
98 };
99 static RK_S32 roll_tab_pattern1[16] = {
100 31, 31, 30, 29, 28, 27, 25, 23, 21, 19, 18, 17, 16, 16, 15, 15,
101 };
102 static RK_S32 roll_tab_pattern2[16] = {
103 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
104 };
105 static RK_S32 tex_grd_tmp[6] = {
106 0, 128, 256, 400, 600, 1023,
107 };
108 static RK_S32 tex_val_tmp[6] = {
109 40, 60, 80, 100, 127, 127,
110 };
111
112 typedef enum VdppDciFmt_e {
113 VDPP_DCI_FMT_RGB888, // 0
114 VDPP_DCI_FMT_ARGB8888, // 1
115 VDPP_DCI_FMT_Y_8bit_SP = 4, // 4
116 VDPP_DCI_FMT_Y_10bit_SP, // 5
117 VDPP_DCI_FMT_BUTT,
118 } VdppDciFmt;
119
120 typedef struct VdppSrcFmtCfg_t {
121 VdppDciFmt format;
122 RK_S32 alpha_swap;
123 RK_S32 rbuv_swap;
124 } VdppSrcFmtCfg;
125
126 static VdppSrcFmtCfg vdpp_src_yuv_cfg[MPP_FMT_YUV_BUTT] = {
127 { /* MPP_FMT_YUV420SP */
128 .format = VDPP_DCI_FMT_Y_8bit_SP,
129 .alpha_swap = 0,
130 .rbuv_swap = 0,
131 },
132 { /* MPP_FMT_YUV420SP_10BIT */
133 .format = VDPP_DCI_FMT_Y_10bit_SP,
134 .alpha_swap = 0,
135 .rbuv_swap = 0,
136 },
137 { /* MPP_FMT_YUV422SP */
138 .format = VDPP_DCI_FMT_Y_8bit_SP,
139 .alpha_swap = 0,
140 .rbuv_swap = 0,
141 },
142 { /* MPP_FMT_YUV422SP_10BIT */
143 .format = VDPP_DCI_FMT_Y_10bit_SP,
144 .alpha_swap = 0,
145 .rbuv_swap = 0,
146 },
147 { /* MPP_FMT_YUV420P */
148 .format = VDPP_DCI_FMT_Y_8bit_SP,
149 .alpha_swap = 0,
150 .rbuv_swap = 0,
151 },
152 { /* MPP_FMT_YUV420SP_VU */
153 .format = VDPP_DCI_FMT_Y_8bit_SP,
154 .alpha_swap = 0,
155 .rbuv_swap = 1,
156 },
157 { /* MPP_FMT_YUV422P */
158 .format = VDPP_DCI_FMT_Y_8bit_SP,
159 .alpha_swap = 0,
160 .rbuv_swap = 0,
161 },
162 { /* MPP_FMT_YUV422SP_VU */
163 .format = VDPP_DCI_FMT_Y_8bit_SP,
164 .alpha_swap = 0,
165 .rbuv_swap = 1,
166 },
167 { /* MPP_FMT_YUV422_YUYV */
168 .format = VDPP_DCI_FMT_BUTT,
169 .alpha_swap = 0,
170 .rbuv_swap = 0,
171 },
172 { /* MPP_FMT_YUV422_YVYU */
173 .format = VDPP_DCI_FMT_BUTT,
174 .alpha_swap = 0,
175 .rbuv_swap = 1,
176 },
177 { /* MPP_FMT_YUV422_UYVY */
178 .format = VDPP_DCI_FMT_BUTT,
179 .alpha_swap = 0,
180 .rbuv_swap = 0,
181 },
182 { /* MPP_FMT_YUV422_VYUY */
183 .format = VDPP_DCI_FMT_BUTT,
184 .alpha_swap = 0,
185 .rbuv_swap = 1,
186 },
187 { /* MPP_FMT_YUV400 */
188 .format = VDPP_DCI_FMT_Y_8bit_SP,
189 .alpha_swap = 0,
190 .rbuv_swap = 0,
191 },
192 { /* MPP_FMT_YUV440SP */
193 .format = VDPP_DCI_FMT_Y_8bit_SP,
194 .alpha_swap = 0,
195 .rbuv_swap = 0,
196 },
197 { /* MPP_FMT_YUV411SP */
198 .format = VDPP_DCI_FMT_Y_8bit_SP,
199 .alpha_swap = 0,
200 .rbuv_swap = 0,
201 },
202 { /* MPP_FMT_YUV444SP */
203 .format = VDPP_DCI_FMT_Y_8bit_SP,
204 .alpha_swap = 0,
205 .rbuv_swap = 0,
206 },
207 { /* MPP_FMT_YUV444P */
208 .format = VDPP_DCI_FMT_Y_8bit_SP,
209 .alpha_swap = 0,
210 .rbuv_swap = 1,
211 },
212 };
213
214 static VdppSrcFmtCfg vdpp_src_rgb_cfg[MPP_FMT_RGB_BUTT - MPP_FRAME_FMT_RGB] = {
215 { /* MPP_FMT_RGB565 */
216 .format = VDPP_DCI_FMT_BUTT,
217 .alpha_swap = 0,
218 .rbuv_swap = 1,
219 },
220 { /* MPP_FMT_BGR565 */
221 .format = VDPP_DCI_FMT_BUTT,
222 .alpha_swap = 0,
223 .rbuv_swap = 0,
224 },
225 { /* MPP_FMT_RGB555 */
226 .format = VDPP_DCI_FMT_BUTT,
227 .alpha_swap = 0,
228 .rbuv_swap = 0,
229 },
230 { /* MPP_FMT_BGR555 */
231 .format = VDPP_DCI_FMT_BUTT,
232 .alpha_swap = 0,
233 .rbuv_swap = 0,
234 },
235 { /* MPP_FMT_RGB444 */
236 .format = VDPP_DCI_FMT_BUTT,
237 .alpha_swap = 0,
238 .rbuv_swap = 0,
239 },
240 { /* MPP_FMT_BGR444 */
241 .format = VDPP_DCI_FMT_BUTT,
242 .alpha_swap = 0,
243 .rbuv_swap = 0,
244 },
245 { /* MPP_FMT_RGB888 */
246 .format = VDPP_DCI_FMT_RGB888,
247 .alpha_swap = 0,
248 .rbuv_swap = 0,
249 },
250 { /* MPP_FMT_BGR888 */
251 .format = VDPP_DCI_FMT_RGB888,
252 .alpha_swap = 0,
253 .rbuv_swap = 1,
254 },
255 { /* MPP_FMT_RGB101010 */
256 .format = VDPP_DCI_FMT_BUTT,
257 .alpha_swap = 0,
258 .rbuv_swap = 0,
259 },
260 { /* MPP_FMT_BGR101010 */
261 .format = VDPP_DCI_FMT_BUTT,
262 .alpha_swap = 0,
263 .rbuv_swap = 0,
264 },
265 { /* MPP_FMT_ARGB8888 */
266 .format = VDPP_DCI_FMT_ARGB8888,
267 .alpha_swap = 1,
268 .rbuv_swap = 1,
269 },
270 { /* MPP_FMT_ABGR8888 */
271 .format = VDPP_DCI_FMT_ARGB8888,
272 .alpha_swap = 1,
273 .rbuv_swap = 0,
274 },
275 { /* MPP_FMT_BGRA8888 */
276 .format = VDPP_DCI_FMT_ARGB8888,
277 .alpha_swap = 0,
278 .rbuv_swap = 0,
279 },
280 { /* MPP_FMT_RGBA8888 */
281 .format = VDPP_DCI_FMT_ARGB8888,
282 .alpha_swap = 0,
283 .rbuv_swap = 1,
284 },
285 };
286
update_dci_ctl(struct vdpp2_params * src_params)287 static void update_dci_ctl(struct vdpp2_params* src_params)
288 {
289 RK_S32 dci_format, dci_alpha_swap, dci_rbuv_swap;
290
291 if (MPP_FRAME_FMT_IS_YUV(src_params->src_fmt)) {
292 dci_format = vdpp_src_yuv_cfg[src_params->src_fmt - MPP_FRAME_FMT_YUV].format;
293 dci_alpha_swap = vdpp_src_yuv_cfg[src_params->src_fmt - MPP_FRAME_FMT_YUV].alpha_swap;
294 dci_rbuv_swap = vdpp_src_yuv_cfg[src_params->src_fmt - MPP_FRAME_FMT_YUV].rbuv_swap;
295 } else if (MPP_FRAME_FMT_IS_RGB(src_params->src_fmt)) {
296 dci_format = vdpp_src_rgb_cfg[src_params->src_fmt - MPP_FRAME_FMT_RGB].format;
297 dci_alpha_swap = vdpp_src_rgb_cfg[src_params->src_fmt - MPP_FRAME_FMT_RGB].alpha_swap;
298 dci_rbuv_swap = vdpp_src_rgb_cfg[src_params->src_fmt - MPP_FRAME_FMT_RGB].rbuv_swap;
299 } else {
300 mpp_err("warning: invalid input format %d", src_params->src_fmt);
301 return;
302 }
303
304 src_params->dci_format = dci_format;
305 src_params->dci_alpha_swap = dci_alpha_swap;
306 src_params->dci_rbuv_swap = dci_rbuv_swap;
307
308 VDPP2_DBG(VDPP2_DBG_TRACE, "input format %d dci_format %d", src_params->src_fmt, dci_format);
309 }
310
set_hist_to_vdpp2_reg(struct vdpp2_params * src_params,struct vdpp2_reg * dst_reg)311 static void set_hist_to_vdpp2_reg(struct vdpp2_params* src_params, struct vdpp2_reg* dst_reg)
312 {
313 RK_S32 pic_vir_src_ystride;
314 RK_S32 hsd_sample_num, vsd_sample_num, sw_dci_blk_hsize, sw_dci_blk_vsize;
315 RK_U32 dci_hsd_mode, dci_vsd_mode;
316
317 update_dci_ctl(src_params);
318
319 pic_vir_src_ystride = (src_params->src_width + 3) / 4;
320
321 if (src_params->dci_format == VDPP_DCI_FMT_RGB888) {
322 pic_vir_src_ystride = src_params->src_width_vir * 3 / 4;
323 } else if (src_params->dci_format == VDPP_DCI_FMT_ARGB8888) {
324 pic_vir_src_ystride = src_params->src_width_vir * 4 / 4;
325 } else if (src_params->dci_format == VDPP_DCI_FMT_Y_10bit_SP) { // Y 10bit SP
326 pic_vir_src_ystride = src_params->src_width_vir * 10 / 8 / 4;
327 } else if (src_params->dci_format == VDPP_DCI_FMT_Y_8bit_SP) { // Y 8bit SP
328 pic_vir_src_ystride = src_params->src_width_vir / 4;
329 } else {
330 mpp_err("warning: unsupported dci format %d", src_params->dci_format);
331 return;
332 }
333
334 dci_hsd_mode = (src_params->dci_hsd_mode & 1);
335 dci_vsd_mode = (src_params->dci_vsd_mode & 3);
336
337 /* check vdpp scale down mode for performance optimization */
338 if (!(dci_hsd_mode & VDPP_DCI_HSD_MODE_1) &&
339 (src_params->src_width_vir > VDPP2_HIST_HSD_DISABLE_LIMIT)) {
340 VDPP2_DBG(VDPP2_DBG_INT, "w_vir %d hsd mode %d is optimized as mode 1\n",
341 src_params->src_width_vir, dci_hsd_mode);
342 dci_hsd_mode = VDPP_DCI_HSD_MODE_1;
343 }
344
345 if (!(dci_vsd_mode & VDPP_DCI_VSD_MODE_1) &&
346 (src_params->src_height_vir > VDPP2_HIST_VSD_DISABLE_LIMIT)) {
347 VDPP2_DBG(VDPP2_DBG_INT, "h_vir %d vsd mode %d is optimized as mode 1\n",
348 src_params->src_height_vir, dci_vsd_mode);
349 dci_vsd_mode = VDPP_DCI_VSD_MODE_1;
350 }
351
352 if (!(dci_vsd_mode & VDPP_DCI_VSD_MODE_2) &&
353 (src_params->src_height_vir > VDPP2_HIST_VSD_MODE_1_LIMIT)) {
354 VDPP2_DBG(VDPP2_DBG_INT, "h_vir %d vsd mode %d is optimized as mode 2\n",
355 src_params->src_height_vir, dci_vsd_mode);
356 dci_vsd_mode = VDPP_DCI_VSD_MODE_2;
357 }
358
359 dci_vsd_mode = (src_params->working_mode == VDPP_WORK_MODE_VEP) ? 0 : dci_vsd_mode;
360 dci_hsd_mode = (src_params->working_mode == VDPP_WORK_MODE_VEP) ? 0 : dci_hsd_mode;
361
362 switch (dci_hsd_mode) {
363 case VDPP_DCI_HSD_DISABLE:
364 hsd_sample_num = 2;
365 break;
366 case VDPP_DCI_HSD_MODE_1:
367 hsd_sample_num = 4;
368 break;
369 default:
370 hsd_sample_num = 2;
371 break;
372 }
373
374 switch (dci_vsd_mode) {
375 case VDPP_DCI_VSD_DISABLE:
376 vsd_sample_num = 1;
377 break;
378 case VDPP_DCI_VSD_MODE_1:
379 vsd_sample_num = 2;
380 break;
381 case VDPP_DCI_VSD_MODE_2:
382 vsd_sample_num = 4;
383 break;
384 default:
385 vsd_sample_num = 1;
386 break;
387 }
388
389 if (src_params->src_height < 1080)
390 sw_dci_blk_vsize = src_params->src_height / (16 * vsd_sample_num);
391 else
392 sw_dci_blk_vsize = (src_params->src_height + (16 * vsd_sample_num - 1)) / (16 * vsd_sample_num);
393
394 if (src_params->src_width < 1080)
395 sw_dci_blk_hsize = src_params->src_width / (16 * hsd_sample_num);
396 else
397 sw_dci_blk_hsize = (src_params->src_width + (16 * hsd_sample_num - 1)) / (16 * hsd_sample_num);
398
399 dst_reg->common.reg1.sw_dci_en = src_params->hist_cnt_en;
400
401 dst_reg->dci.reg0.sw_dci_yrgb_addr = src_params->src.y;
402 dst_reg->dci.reg1.sw_dci_yrgb_vir_stride = pic_vir_src_ystride;
403 dst_reg->dci.reg1.sw_dci_yrgb_gather_num = src_params->dci_yrgb_gather_num;
404 dst_reg->dci.reg1.sw_dci_yrgb_gather_en = src_params->dci_yrgb_gather_en;
405 dst_reg->dci.reg2.sw_vdpp_src_pic_width = MPP_ALIGN_DOWN(src_params->src_width, hsd_sample_num) - 1;
406 dst_reg->dci.reg2.sw_vdpp_src_pic_height = MPP_ALIGN_DOWN(src_params->src_height, vsd_sample_num) - 1;
407 dst_reg->dci.reg3.sw_dci_data_format = src_params->dci_format;
408 dst_reg->dci.reg3.sw_dci_csc_range = src_params->dci_csc_range;
409 dst_reg->dci.reg3.sw_dci_vsd_mode = dci_vsd_mode;
410 dst_reg->dci.reg3.sw_dci_hsd_mode = dci_hsd_mode;
411 dst_reg->dci.reg3.sw_dci_alpha_swap = src_params->dci_alpha_swap;
412 dst_reg->dci.reg3.sw_dci_rb_swap = src_params->dci_rbuv_swap;
413 dst_reg->dci.reg3.sw_dci_blk_hsize = sw_dci_blk_hsize;
414 dst_reg->dci.reg3.sw_dci_blk_vsize = sw_dci_blk_vsize;
415 dst_reg->dci.reg4.sw_dci_hist_addr = src_params->hist;
416 }
417
update_es_tan(EsParams * p_es_param)418 static void update_es_tan(EsParams* p_es_param)
419 {
420 RK_U32 angle_lo_th, angle_hi_th;
421
422 angle_lo_th = 23 - p_es_param->es_iAngleDelta - p_es_param->es_iAngleDeltaExtra;
423 angle_hi_th = 23 + p_es_param->es_iAngleDelta;
424
425 p_es_param->es_tan_lo_th = mpp_clip(tan(angle_lo_th * acos(-1) / 180.0) * 512, 0, 511);
426 p_es_param->es_tan_hi_th = mpp_clip(tan(angle_hi_th * acos(-1) / 180.0) * 512, 0, 511);
427 }
428
429
set_es_to_vdpp2_reg(struct vdpp2_params * src_params,struct vdpp2_reg * dst_reg)430 static void set_es_to_vdpp2_reg(struct vdpp2_params* src_params, struct vdpp2_reg* dst_reg)
431 {
432 EsParams *p_es_param = &src_params->es_params;
433 RK_U8 diff2conf_lut_k[8] = { 0 };
434 RK_U8 conf_local_mean_th = mpp_clip((256 * (float)p_es_param->es_iWgtLocalTh)
435 / p_es_param->es_iWgtGain, 0, 255);
436 RK_S32 i;
437
438 update_es_tan(p_es_param);
439
440 dst_reg->es.reg0.es_enable = p_es_param->es_bEnabledES;
441 dst_reg->es.reg1.dir_th = p_es_param->es_iGradNoDirTh;
442 dst_reg->es.reg1.flat_th = p_es_param->es_iGradFlatTh;
443
444 dst_reg->es.reg2.tan_lo_th = p_es_param->es_tan_lo_th;
445 dst_reg->es.reg2.tan_hi_th = p_es_param->es_tan_hi_th;
446
447 dst_reg->es.reg3.ep_chk_en = p_es_param->es_bEndpointCheckEnable;
448 //dst_reg->es.sw_dir_chk.MEM_GAT_EN
449
450 dst_reg->es.reg4.diff_gain0 = p_es_param->es_iK1;
451 dst_reg->es.reg4.diff_limit = p_es_param->es_iDeltaLimit;
452
453 dst_reg->es.reg5.diff_gain1 = p_es_param->es_iK2;
454 dst_reg->es.reg5.lut_x0 = p_es_param->es_iDiff2conf_lut_x[0];
455
456 dst_reg->es.reg6.lut_x1 = p_es_param->es_iDiff2conf_lut_x[1];
457 dst_reg->es.reg6.lut_x2 = p_es_param->es_iDiff2conf_lut_x[2];
458 dst_reg->es.reg7.lut_x3 = p_es_param->es_iDiff2conf_lut_x[3];
459 dst_reg->es.reg7.lut_x4 = p_es_param->es_iDiff2conf_lut_x[4];
460 dst_reg->es.reg8.lut_x5 = p_es_param->es_iDiff2conf_lut_x[5];
461 dst_reg->es.reg8.lut_x6 = p_es_param->es_iDiff2conf_lut_x[6];
462 dst_reg->es.reg9.lut_x7 = p_es_param->es_iDiff2conf_lut_x[7];
463 dst_reg->es.reg9.lut_x8 = p_es_param->es_iDiff2conf_lut_x[8];
464
465 dst_reg->es.reg10.lut_y0 = p_es_param->es_iDiff2conf_lut_y[0];
466 dst_reg->es.reg10.lut_y1 = p_es_param->es_iDiff2conf_lut_y[1];
467 dst_reg->es.reg10.lut_y2 = p_es_param->es_iDiff2conf_lut_y[2];
468 dst_reg->es.reg10.lut_y3 = p_es_param->es_iDiff2conf_lut_y[3];
469 dst_reg->es.reg11.lut_y4 = p_es_param->es_iDiff2conf_lut_y[4];
470 dst_reg->es.reg11.lut_y5 = p_es_param->es_iDiff2conf_lut_y[5];
471 dst_reg->es.reg11.lut_y6 = p_es_param->es_iDiff2conf_lut_y[6];
472 dst_reg->es.reg11.lut_y7 = p_es_param->es_iDiff2conf_lut_y[7];
473 dst_reg->es.reg12.lut_y8 = p_es_param->es_iDiff2conf_lut_y[8];
474
475 for (i = 0; i < 8; i++) {
476 double x0 = p_es_param->es_iDiff2conf_lut_x[i];
477 double x1 = p_es_param->es_iDiff2conf_lut_x[i + 1];
478 double y0 = p_es_param->es_iDiff2conf_lut_y[i];
479 double y1 = p_es_param->es_iDiff2conf_lut_y[i + 1];
480 diff2conf_lut_k[i] = mpp_clip(FLOOR(256 * (y1 - y0) / (x1 - x0)), 0, 255);
481 }
482 dst_reg->es.reg13.lut_k0 = diff2conf_lut_k[0];
483 dst_reg->es.reg13.lut_k1 = diff2conf_lut_k[1];
484 dst_reg->es.reg13.lut_k2 = diff2conf_lut_k[2];
485 dst_reg->es.reg13.lut_k3 = diff2conf_lut_k[3];
486 dst_reg->es.reg14.lut_k4 = diff2conf_lut_k[4];
487 dst_reg->es.reg14.lut_k5 = diff2conf_lut_k[5];
488 dst_reg->es.reg14.lut_k6 = diff2conf_lut_k[6];
489 dst_reg->es.reg14.lut_k7 = diff2conf_lut_k[7];
490
491 dst_reg->es.reg15.wgt_decay = p_es_param->es_iWgtDecay;
492 dst_reg->es.reg15.wgt_gain = p_es_param->es_iWgtGain;
493
494 dst_reg->es.reg16.conf_mean_th = conf_local_mean_th;
495 dst_reg->es.reg16.conf_cnt_th = p_es_param->es_iConfCntTh;
496 dst_reg->es.reg16.low_conf_th = p_es_param->es_iLowConfTh;
497 dst_reg->es.reg16.low_conf_ratio = p_es_param->es_iLowConfRatio;
498 }
499
set_shp_to_vdpp2_reg(struct vdpp2_params * src_params,struct vdpp2_reg * dst_reg)500 static void set_shp_to_vdpp2_reg(struct vdpp2_params* src_params, struct vdpp2_reg* dst_reg)
501 {
502 ShpParams *p_shp_param = &src_params->shp_params;
503 /* Peaking Ctrl sw-process */
504 RK_S32 peaking_ctrl_idx_P0[7] = { 0 };
505 RK_S32 peaking_ctrl_idx_N0[7] = { 0 };
506 RK_S32 peaking_ctrl_idx_P1[7] = { 0 };
507 RK_S32 peaking_ctrl_idx_N1[7] = { 0 };
508 RK_S32 peaking_ctrl_idx_P2[7] = { 0 };
509 RK_S32 peaking_ctrl_idx_N2[7] = { 0 };
510 RK_S32 peaking_ctrl_idx_P3[7] = { 0 };
511 RK_S32 peaking_ctrl_idx_N3[7] = { 0 };
512
513 RK_S32 peaking_ctrl_value_N1[7] = { 0 };
514 RK_S32 peaking_ctrl_value_N2[7] = { 0 };
515 RK_S32 peaking_ctrl_value_N3[7] = { 0 };
516 RK_S32 peaking_ctrl_value_P1[7] = { 0 };
517 RK_S32 peaking_ctrl_value_P2[7] = { 0 };
518 RK_S32 peaking_ctrl_value_P3[7] = { 0 };
519
520 RK_S32 peaking_ctrl_ratio_P01[7] = { 0 };
521 RK_S32 peaking_ctrl_ratio_P12[7] = { 0 };
522 RK_S32 peaking_ctrl_ratio_P23[7] = { 0 };
523 RK_S32 peaking_ctrl_ratio_N01[7] = { 0 };
524 RK_S32 peaking_ctrl_ratio_N12[7] = { 0 };
525 RK_S32 peaking_ctrl_ratio_N23[7] = { 0 };
526
527 RK_S32 global_gain_slp_temp[5] = { 0 };
528 RK_S32 ii;
529 dst_reg->sharp.reg0.sw_sharp_enable = p_shp_param->sharp_enable;
530 dst_reg->sharp.reg0.sw_lti_enable = p_shp_param->lti_h_enable || p_shp_param->lti_v_enable;
531 dst_reg->sharp.reg0.sw_cti_enable = p_shp_param->cti_h_enable;
532 dst_reg->sharp.reg0.sw_peaking_enable = p_shp_param->peaking_enable;
533 dst_reg->sharp.reg0.sw_peaking_ctrl_enable = p_shp_param->peaking_coring_enable || p_shp_param->peaking_gain_enable || p_shp_param->peaking_limit_ctrl_enable;
534 dst_reg->sharp.reg0.sw_edge_proc_enable = p_shp_param->peaking_edge_ctrl_enable;
535 dst_reg->sharp.reg0.sw_shoot_ctrl_enable = p_shp_param->shootctrl_enable;
536 dst_reg->sharp.reg0.sw_gain_ctrl_enable = p_shp_param->global_gain_enable;
537 dst_reg->sharp.reg0.sw_color_adj_enable = p_shp_param->color_ctrl_enable;
538 dst_reg->sharp.reg0.sw_texture_adj_enable = p_shp_param->tex_adj_enable;
539 dst_reg->sharp.reg0.sw_coloradj_bypass_en = p_shp_param->sharp_coloradj_bypass_en;
540 dst_reg->sharp.reg0.sw_ink_enable = 0;
541 dst_reg->sharp.reg0.sw_sharp_redundent_bypass = 0;
542
543 if ((dst_reg->sharp.reg0.sw_lti_enable == 1) && (p_shp_param->lti_h_enable == 0))
544 p_shp_param->lti_h_gain = 0;
545
546 if ((dst_reg->sharp.reg0.sw_lti_enable == 1) && (p_shp_param->lti_v_enable == 0))
547 p_shp_param->lti_v_gain = 0;
548
549 dst_reg->sharp.reg162.sw_ltih_radius = p_shp_param->lti_h_radius;
550 dst_reg->sharp.reg162.sw_ltih_slp1 = p_shp_param->lti_h_slope;
551 dst_reg->sharp.reg162.sw_ltih_thr1 = p_shp_param->lti_h_thresold;
552 dst_reg->sharp.reg163.sw_ltih_noisethrneg = p_shp_param->lti_h_noise_thr_neg;
553 dst_reg->sharp.reg163.sw_ltih_noisethrpos = p_shp_param->lti_h_noise_thr_pos;
554 dst_reg->sharp.reg163.sw_ltih_tigain = p_shp_param->lti_h_gain;
555
556 dst_reg->sharp.reg164.sw_ltiv_radius = p_shp_param->lti_v_radius;
557 dst_reg->sharp.reg164.sw_ltiv_slp1 = p_shp_param->lti_v_slope;
558 dst_reg->sharp.reg164.sw_ltiv_thr1 = p_shp_param->lti_v_thresold;
559 dst_reg->sharp.reg165.sw_ltiv_noisethrneg = p_shp_param->lti_v_noise_thr_neg;
560 dst_reg->sharp.reg165.sw_ltiv_noisethrpos = p_shp_param->lti_v_noise_thr_pos;
561 dst_reg->sharp.reg165.sw_ltiv_tigain = p_shp_param->lti_v_gain;
562
563 dst_reg->sharp.reg166.sw_ctih_radius = p_shp_param->cti_h_radius;
564 dst_reg->sharp.reg166.sw_ctih_slp1 = p_shp_param->cti_h_slope;
565 dst_reg->sharp.reg166.sw_ctih_thr1 = p_shp_param->cti_h_thresold;
566 dst_reg->sharp.reg167.sw_ctih_noisethrneg = p_shp_param->cti_h_noise_thr_neg;
567 dst_reg->sharp.reg167.sw_ctih_noisethrpos = p_shp_param->cti_h_noise_thr_pos;
568 dst_reg->sharp.reg167.sw_ctih_tigain = p_shp_param->cti_h_gain;
569
570 for (ii = 0; ii < 7; ii++) {
571 RK_S32 coring_ratio, coring_zero, coring_thr, gain_ctrl_pos,
572 gain_ctrl_neg, limit_ctrl_p0, limit_ctrl_p1, limit_ctrl_n0,
573 limit_ctrl_n1, limit_ctrl_ratio;
574 RK_S32 ratio_pos_tmp, ratio_neg_tmp, peaking_ctrl_add_tmp;
575
576 if (p_shp_param->peaking_coring_enable == 1) {
577 coring_ratio = p_shp_param->peaking_coring_ratio[ii];
578 coring_zero = p_shp_param->peaking_coring_zero[ii] >> 2;
579 coring_thr = p_shp_param->peaking_coring_thr[ii] >> 2;
580 } else {
581 coring_ratio = 1024;
582 coring_zero = 0;
583 coring_thr = 0;
584 }
585 if (p_shp_param->peaking_gain_enable == 1) {
586 gain_ctrl_pos = p_shp_param->peaking_gain_pos[ii];
587 gain_ctrl_neg = p_shp_param->peaking_gain_neg[ii];
588 } else {
589 gain_ctrl_pos = 1024;
590 gain_ctrl_neg = 1024;
591 }
592 if (p_shp_param->peaking_limit_ctrl_enable == 1) {
593 limit_ctrl_p0 = p_shp_param->peaking_limit_ctrl_pos0[ii] >> 2;
594 limit_ctrl_p1 = p_shp_param->peaking_limit_ctrl_pos1[ii] >> 2;
595 limit_ctrl_n0 = p_shp_param->peaking_limit_ctrl_neg0[ii] >> 2;
596 limit_ctrl_n1 = p_shp_param->peaking_limit_ctrl_neg1[ii] >> 2;
597 limit_ctrl_ratio = p_shp_param->peaking_limit_ctrl_ratio[ii];
598 } else {
599 limit_ctrl_p0 = 255 >> 2;
600 limit_ctrl_p1 = 255 >> 2;
601 limit_ctrl_n0 = 255 >> 2;
602 limit_ctrl_n1 = 255 >> 2;
603 limit_ctrl_ratio = 1024;
604 }
605
606 peaking_ctrl_idx_P0[ii] = coring_zero;
607 peaking_ctrl_idx_N0[ii] = -coring_zero;
608 peaking_ctrl_idx_P1[ii] = coring_thr;
609 peaking_ctrl_idx_N1[ii] = -coring_thr;
610 peaking_ctrl_idx_P2[ii] = limit_ctrl_p0;
611 peaking_ctrl_idx_N2[ii] = -limit_ctrl_n0;
612 peaking_ctrl_idx_P3[ii] = limit_ctrl_p1;
613 peaking_ctrl_idx_N3[ii] = -limit_ctrl_n1;
614
615 ratio_pos_tmp = (coring_ratio * gain_ctrl_pos + 512) >> 10;
616 ratio_neg_tmp = (coring_ratio * gain_ctrl_neg + 512) >> 10;
617 peaking_ctrl_value_P1[ii] = ((ratio_pos_tmp * (coring_thr - coring_zero) + 512) >> 10);
618 peaking_ctrl_value_N1[ii] = -((ratio_neg_tmp * (coring_thr - coring_zero) + 512) >> 10);
619 peaking_ctrl_ratio_P01[ii] = ratio_pos_tmp;
620 peaking_ctrl_ratio_N01[ii] = ratio_neg_tmp;
621
622 peaking_ctrl_ratio_P12[ii] = gain_ctrl_pos;
623 peaking_ctrl_ratio_N12[ii] = gain_ctrl_neg;
624
625 peaking_ctrl_add_tmp = (gain_ctrl_pos * (limit_ctrl_p0 - coring_thr) + 512) >> 10;
626 peaking_ctrl_value_P2[ii] = peaking_ctrl_value_P1[ii] + peaking_ctrl_add_tmp;
627 peaking_ctrl_add_tmp = (gain_ctrl_neg * (limit_ctrl_n0 - coring_thr) + 512) >> 10;
628 peaking_ctrl_value_N2[ii] = peaking_ctrl_value_N1[ii] - peaking_ctrl_add_tmp;
629
630 ratio_pos_tmp = (limit_ctrl_ratio * gain_ctrl_pos + 512) >> 10;
631 ratio_neg_tmp = (limit_ctrl_ratio * gain_ctrl_neg + 512) >> 10;
632
633 peaking_ctrl_add_tmp = (ratio_pos_tmp * (limit_ctrl_p1 - limit_ctrl_p0) + 512) >> 10;
634 peaking_ctrl_value_P3[ii] = peaking_ctrl_value_P2[ii] + peaking_ctrl_add_tmp;
635 peaking_ctrl_add_tmp = (ratio_neg_tmp * (limit_ctrl_n1 - limit_ctrl_n0) + 512) >> 10;
636 peaking_ctrl_value_N3[ii] = peaking_ctrl_value_N2[ii] - peaking_ctrl_add_tmp;
637 peaking_ctrl_ratio_P23[ii] = ratio_pos_tmp;
638 peaking_ctrl_ratio_N23[ii] = ratio_neg_tmp;
639
640 peaking_ctrl_idx_N0[ii] = mpp_clip(peaking_ctrl_idx_N0[ii], -256, 255);
641 peaking_ctrl_idx_N1[ii] = mpp_clip(peaking_ctrl_idx_N1[ii], -256, 255);
642 peaking_ctrl_idx_N2[ii] = mpp_clip(peaking_ctrl_idx_N2[ii], -256, 255);
643 peaking_ctrl_idx_N3[ii] = mpp_clip(peaking_ctrl_idx_N3[ii], -256, 255);
644 peaking_ctrl_idx_P0[ii] = mpp_clip(peaking_ctrl_idx_P0[ii], -256, 255);
645 peaking_ctrl_idx_P1[ii] = mpp_clip(peaking_ctrl_idx_P1[ii], -256, 255);
646 peaking_ctrl_idx_P2[ii] = mpp_clip(peaking_ctrl_idx_P2[ii], -256, 255);
647 peaking_ctrl_idx_P3[ii] = mpp_clip(peaking_ctrl_idx_P3[ii], -256, 255);
648
649 peaking_ctrl_value_N1[ii] = mpp_clip(peaking_ctrl_value_N1[ii], -256, 255);
650 peaking_ctrl_value_N2[ii] = mpp_clip(peaking_ctrl_value_N2[ii], -256, 255);
651 peaking_ctrl_value_N3[ii] = mpp_clip(peaking_ctrl_value_N3[ii], -256, 255);
652 peaking_ctrl_value_P1[ii] = mpp_clip(peaking_ctrl_value_P1[ii], -256, 255);
653 peaking_ctrl_value_P2[ii] = mpp_clip(peaking_ctrl_value_P2[ii], -256, 255);
654 peaking_ctrl_value_P3[ii] = mpp_clip(peaking_ctrl_value_P3[ii], -256, 255);
655
656 peaking_ctrl_ratio_P01[ii] = mpp_clip(peaking_ctrl_ratio_P01[ii], 0, 4095);
657 peaking_ctrl_ratio_P12[ii] = mpp_clip(peaking_ctrl_ratio_P12[ii], 0, 4095);
658 peaking_ctrl_ratio_P23[ii] = mpp_clip(peaking_ctrl_ratio_P23[ii], 0, 4095);
659 peaking_ctrl_ratio_N01[ii] = mpp_clip(peaking_ctrl_ratio_N01[ii], 0, 4095);
660 peaking_ctrl_ratio_N12[ii] = mpp_clip(peaking_ctrl_ratio_N12[ii], 0, 4095);
661 peaking_ctrl_ratio_N23[ii] = mpp_clip(peaking_ctrl_ratio_N23[ii], 0, 4095);
662 }
663
664 dst_reg->sharp.reg12.sw_peaking0_idx_n0 = peaking_ctrl_idx_N0[0];
665 dst_reg->sharp.reg12.sw_peaking0_idx_n1 = peaking_ctrl_idx_N1[0];
666 dst_reg->sharp.reg13.sw_peaking0_idx_n2 = peaking_ctrl_idx_N2[0];
667 dst_reg->sharp.reg13.sw_peaking0_idx_n3 = peaking_ctrl_idx_N3[0];
668 dst_reg->sharp.reg14.sw_peaking0_idx_p0 = peaking_ctrl_idx_P0[0];
669 dst_reg->sharp.reg14.sw_peaking0_idx_p1 = peaking_ctrl_idx_P1[0];
670 dst_reg->sharp.reg15.sw_peaking0_idx_p2 = peaking_ctrl_idx_P2[0];
671 dst_reg->sharp.reg15.sw_peaking0_idx_p3 = peaking_ctrl_idx_P3[0];
672 dst_reg->sharp.reg16.sw_peaking0_value_n1 = peaking_ctrl_value_N1[0];
673 dst_reg->sharp.reg16.sw_peaking0_value_n2 = peaking_ctrl_value_N2[0];
674 dst_reg->sharp.reg17.sw_peaking0_value_n3 = peaking_ctrl_value_N3[0];
675 dst_reg->sharp.reg17.sw_peaking0_value_p1 = peaking_ctrl_value_P1[0];
676 dst_reg->sharp.reg18.sw_peaking0_value_p2 = peaking_ctrl_value_P2[0];
677 dst_reg->sharp.reg18.sw_peaking0_value_p3 = peaking_ctrl_value_P3[0];
678 dst_reg->sharp.reg19.sw_peaking0_ratio_n01 = peaking_ctrl_ratio_N01[0];
679 dst_reg->sharp.reg19.sw_peaking0_ratio_n12 = peaking_ctrl_ratio_N12[0];
680 dst_reg->sharp.reg20.sw_peaking0_ratio_n23 = peaking_ctrl_ratio_N23[0];
681 dst_reg->sharp.reg20.sw_peaking0_ratio_p01 = peaking_ctrl_ratio_P01[0];
682 dst_reg->sharp.reg21.sw_peaking0_ratio_p12 = peaking_ctrl_ratio_P12[0];
683 dst_reg->sharp.reg21.sw_peaking0_ratio_p23 = peaking_ctrl_ratio_P23[0];
684
685 dst_reg->sharp.reg23.sw_peaking1_idx_n0 = peaking_ctrl_idx_N0[1];
686 dst_reg->sharp.reg23.sw_peaking1_idx_n1 = peaking_ctrl_idx_N1[1];
687 dst_reg->sharp.reg24.sw_peaking1_idx_n2 = peaking_ctrl_idx_N2[1];
688 dst_reg->sharp.reg24.sw_peaking1_idx_n3 = peaking_ctrl_idx_N3[1];
689 dst_reg->sharp.reg25.sw_peaking1_idx_p0 = peaking_ctrl_idx_P0[1];
690 dst_reg->sharp.reg25.sw_peaking1_idx_p1 = peaking_ctrl_idx_P1[1];
691 dst_reg->sharp.reg26.sw_peaking1_idx_p2 = peaking_ctrl_idx_P2[1];
692 dst_reg->sharp.reg26.sw_peaking1_idx_p3 = peaking_ctrl_idx_P3[1];
693 dst_reg->sharp.reg27.sw_peaking1_value_n1 = peaking_ctrl_value_N1[1];
694 dst_reg->sharp.reg27.sw_peaking1_value_n2 = peaking_ctrl_value_N2[1];
695 dst_reg->sharp.reg28.sw_peaking1_value_n3 = peaking_ctrl_value_N3[1];
696 dst_reg->sharp.reg28.sw_peaking1_value_p1 = peaking_ctrl_value_P1[1];
697 dst_reg->sharp.reg29.sw_peaking1_value_p2 = peaking_ctrl_value_P2[1];
698 dst_reg->sharp.reg29.sw_peaking1_value_p3 = peaking_ctrl_value_P3[1];
699 dst_reg->sharp.reg30.sw_peaking1_ratio_n01 = peaking_ctrl_ratio_N01[1];
700 dst_reg->sharp.reg30.sw_peaking1_ratio_n12 = peaking_ctrl_ratio_N12[1];
701 dst_reg->sharp.reg31.sw_peaking1_ratio_n23 = peaking_ctrl_ratio_N23[1];
702 dst_reg->sharp.reg31.sw_peaking1_ratio_p01 = peaking_ctrl_ratio_P01[1];
703 dst_reg->sharp.reg32.sw_peaking1_ratio_p12 = peaking_ctrl_ratio_P12[1];
704 dst_reg->sharp.reg32.sw_peaking1_ratio_p23 = peaking_ctrl_ratio_P23[1];
705
706 dst_reg->sharp.reg34.sw_peaking2_idx_n0 = peaking_ctrl_idx_N0[2];
707 dst_reg->sharp.reg34.sw_peaking2_idx_n1 = peaking_ctrl_idx_N1[2];
708 dst_reg->sharp.reg35.sw_peaking2_idx_n2 = peaking_ctrl_idx_N2[2];
709 dst_reg->sharp.reg35.sw_peaking2_idx_n3 = peaking_ctrl_idx_N3[2];
710 dst_reg->sharp.reg36.sw_peaking2_idx_p0 = peaking_ctrl_idx_P0[2];
711 dst_reg->sharp.reg36.sw_peaking2_idx_p1 = peaking_ctrl_idx_P1[2];
712 dst_reg->sharp.reg37.sw_peaking2_idx_p2 = peaking_ctrl_idx_P2[2];
713 dst_reg->sharp.reg37.sw_peaking2_idx_p3 = peaking_ctrl_idx_P3[2];
714 dst_reg->sharp.reg38.sw_peaking2_value_n1 = peaking_ctrl_value_N1[2];
715 dst_reg->sharp.reg38.sw_peaking2_value_n2 = peaking_ctrl_value_N2[2];
716 dst_reg->sharp.reg39.sw_peaking2_value_n3 = peaking_ctrl_value_N3[2];
717 dst_reg->sharp.reg39.sw_peaking2_value_p1 = peaking_ctrl_value_P1[2];
718 dst_reg->sharp.reg40.sw_peaking2_value_p2 = peaking_ctrl_value_P2[2];
719 dst_reg->sharp.reg40.sw_peaking2_value_p3 = peaking_ctrl_value_P3[2];
720 dst_reg->sharp.reg41.sw_peaking2_ratio_n01 = peaking_ctrl_ratio_N01[2];
721 dst_reg->sharp.reg41.sw_peaking2_ratio_n12 = peaking_ctrl_ratio_N12[2];
722 dst_reg->sharp.reg42.sw_peaking2_ratio_n23 = peaking_ctrl_ratio_N23[2];
723 dst_reg->sharp.reg42.sw_peaking2_ratio_p01 = peaking_ctrl_ratio_P01[2];
724 dst_reg->sharp.reg43.sw_peaking2_ratio_p12 = peaking_ctrl_ratio_P12[2];
725 dst_reg->sharp.reg43.sw_peaking2_ratio_p23 = peaking_ctrl_ratio_P23[2];
726
727 dst_reg->sharp.reg45.sw_peaking3_idx_n0 = peaking_ctrl_idx_N0[3];
728 dst_reg->sharp.reg45.sw_peaking3_idx_n1 = peaking_ctrl_idx_N1[3];
729 dst_reg->sharp.reg46.sw_peaking3_idx_n2 = peaking_ctrl_idx_N2[3];
730 dst_reg->sharp.reg46.sw_peaking3_idx_n3 = peaking_ctrl_idx_N3[3];
731 dst_reg->sharp.reg47.sw_peaking3_idx_p0 = peaking_ctrl_idx_P0[3];
732 dst_reg->sharp.reg47.sw_peaking3_idx_p1 = peaking_ctrl_idx_P1[3];
733 dst_reg->sharp.reg48.sw_peaking3_idx_p2 = peaking_ctrl_idx_P2[3];
734 dst_reg->sharp.reg48.sw_peaking3_idx_p3 = peaking_ctrl_idx_P3[3];
735 dst_reg->sharp.reg49.sw_peaking3_value_n1 = peaking_ctrl_value_N1[3];
736 dst_reg->sharp.reg49.sw_peaking3_value_n2 = peaking_ctrl_value_N2[3];
737 dst_reg->sharp.reg50.sw_peaking3_value_n3 = peaking_ctrl_value_N3[3];
738 dst_reg->sharp.reg50.sw_peaking3_value_p1 = peaking_ctrl_value_P1[3];
739 dst_reg->sharp.reg51.sw_peaking3_value_p2 = peaking_ctrl_value_P2[3];
740 dst_reg->sharp.reg51.sw_peaking3_value_p3 = peaking_ctrl_value_P3[3];
741 dst_reg->sharp.reg52.sw_peaking3_ratio_n01 = peaking_ctrl_ratio_N01[3];
742 dst_reg->sharp.reg52.sw_peaking3_ratio_n12 = peaking_ctrl_ratio_N12[3];
743 dst_reg->sharp.reg53.sw_peaking3_ratio_n23 = peaking_ctrl_ratio_N23[3];
744 dst_reg->sharp.reg53.sw_peaking3_ratio_p01 = peaking_ctrl_ratio_P01[3];
745 dst_reg->sharp.reg54.sw_peaking3_ratio_p12 = peaking_ctrl_ratio_P12[3];
746 dst_reg->sharp.reg54.sw_peaking3_ratio_p23 = peaking_ctrl_ratio_P23[3];
747
748 dst_reg->sharp.reg56.sw_peaking4_idx_n0 = peaking_ctrl_idx_N0[4];
749 dst_reg->sharp.reg56.sw_peaking4_idx_n1 = peaking_ctrl_idx_N1[4];
750 dst_reg->sharp.reg57.sw_peaking4_idx_n2 = peaking_ctrl_idx_N2[4];
751 dst_reg->sharp.reg57.sw_peaking4_idx_n3 = peaking_ctrl_idx_N3[4];
752 dst_reg->sharp.reg58.sw_peaking4_idx_p0 = peaking_ctrl_idx_P0[4];
753 dst_reg->sharp.reg58.sw_peaking4_idx_p1 = peaking_ctrl_idx_P1[4];
754 dst_reg->sharp.reg59.sw_peaking4_idx_p2 = peaking_ctrl_idx_P2[4];
755 dst_reg->sharp.reg59.sw_peaking4_idx_p3 = peaking_ctrl_idx_P3[4];
756 dst_reg->sharp.reg60.sw_peaking4_value_n1 = peaking_ctrl_value_N1[4];
757 dst_reg->sharp.reg60.sw_peaking4_value_n2 = peaking_ctrl_value_N2[4];
758 dst_reg->sharp.reg61.sw_peaking4_value_n3 = peaking_ctrl_value_N3[4];
759 dst_reg->sharp.reg61.sw_peaking4_value_p1 = peaking_ctrl_value_P1[4];
760 dst_reg->sharp.reg62.sw_peaking4_value_p2 = peaking_ctrl_value_P2[4];
761 dst_reg->sharp.reg62.sw_peaking4_value_p3 = peaking_ctrl_value_P3[4];
762 dst_reg->sharp.reg63.sw_peaking4_ratio_n01 = peaking_ctrl_ratio_N01[4];
763 dst_reg->sharp.reg63.sw_peaking4_ratio_n12 = peaking_ctrl_ratio_N12[4];
764 dst_reg->sharp.reg64.sw_peaking4_ratio_n23 = peaking_ctrl_ratio_N23[4];
765 dst_reg->sharp.reg64.sw_peaking4_ratio_p01 = peaking_ctrl_ratio_P01[4];
766 dst_reg->sharp.reg65.sw_peaking4_ratio_p12 = peaking_ctrl_ratio_P12[4];
767 dst_reg->sharp.reg65.sw_peaking4_ratio_p23 = peaking_ctrl_ratio_P23[4];
768
769 dst_reg->sharp.reg67.sw_peaking5_idx_n0 = peaking_ctrl_idx_N0[5];
770 dst_reg->sharp.reg67.sw_peaking5_idx_n1 = peaking_ctrl_idx_N1[5];
771 dst_reg->sharp.reg68.sw_peaking5_idx_n2 = peaking_ctrl_idx_N2[5];
772 dst_reg->sharp.reg68.sw_peaking5_idx_n3 = peaking_ctrl_idx_N3[5];
773 dst_reg->sharp.reg69.sw_peaking5_idx_p0 = peaking_ctrl_idx_P0[5];
774 dst_reg->sharp.reg69.sw_peaking5_idx_p1 = peaking_ctrl_idx_P1[5];
775 dst_reg->sharp.reg70.sw_peaking5_idx_p2 = peaking_ctrl_idx_P2[5];
776 dst_reg->sharp.reg70.sw_peaking5_idx_p3 = peaking_ctrl_idx_P3[5];
777 dst_reg->sharp.reg71.sw_peaking5_value_n1 = peaking_ctrl_value_N1[5];
778 dst_reg->sharp.reg71.sw_peaking5_value_n2 = peaking_ctrl_value_N2[5];
779 dst_reg->sharp.reg72.sw_peaking5_value_n3 = peaking_ctrl_value_N3[5];
780 dst_reg->sharp.reg72.sw_peaking5_value_p1 = peaking_ctrl_value_P1[5];
781 dst_reg->sharp.reg73.sw_peaking5_value_p2 = peaking_ctrl_value_P2[5];
782 dst_reg->sharp.reg73.sw_peaking5_value_p3 = peaking_ctrl_value_P3[5];
783 dst_reg->sharp.reg74.sw_peaking5_ratio_n01 = peaking_ctrl_ratio_N01[5];
784 dst_reg->sharp.reg74.sw_peaking5_ratio_n12 = peaking_ctrl_ratio_N12[5];
785 dst_reg->sharp.reg75.sw_peaking5_ratio_n23 = peaking_ctrl_ratio_N23[5];
786 dst_reg->sharp.reg75.sw_peaking5_ratio_p01 = peaking_ctrl_ratio_P01[5];
787 dst_reg->sharp.reg76.sw_peaking5_ratio_p12 = peaking_ctrl_ratio_P12[5];
788 dst_reg->sharp.reg76.sw_peaking5_ratio_p23 = peaking_ctrl_ratio_P23[5];
789
790 dst_reg->sharp.reg78.sw_peaking6_idx_n0 = peaking_ctrl_idx_N0[6];
791 dst_reg->sharp.reg78.sw_peaking6_idx_n1 = peaking_ctrl_idx_N1[6];
792 dst_reg->sharp.reg79.sw_peaking6_idx_n2 = peaking_ctrl_idx_N2[6];
793 dst_reg->sharp.reg79.sw_peaking6_idx_n3 = peaking_ctrl_idx_N3[6];
794 dst_reg->sharp.reg80.sw_peaking6_idx_p0 = peaking_ctrl_idx_P0[6];
795 dst_reg->sharp.reg80.sw_peaking6_idx_p1 = peaking_ctrl_idx_P1[6];
796 dst_reg->sharp.reg81.sw_peaking6_idx_p2 = peaking_ctrl_idx_P2[6];
797 dst_reg->sharp.reg81.sw_peaking6_idx_p3 = peaking_ctrl_idx_P3[6];
798 dst_reg->sharp.reg82.sw_peaking6_value_n1 = peaking_ctrl_value_N1[6];
799 dst_reg->sharp.reg82.sw_peaking6_value_n2 = peaking_ctrl_value_N2[6];
800 dst_reg->sharp.reg83.sw_peaking6_value_n3 = peaking_ctrl_value_N3[6];
801 dst_reg->sharp.reg83.sw_peaking6_value_p1 = peaking_ctrl_value_P1[6];
802 dst_reg->sharp.reg84.sw_peaking6_value_p2 = peaking_ctrl_value_P2[6];
803 dst_reg->sharp.reg84.sw_peaking6_value_p3 = peaking_ctrl_value_P3[6];
804 dst_reg->sharp.reg85.sw_peaking6_ratio_n01 = peaking_ctrl_ratio_N01[6];
805 dst_reg->sharp.reg85.sw_peaking6_ratio_n12 = peaking_ctrl_ratio_N12[6];
806 dst_reg->sharp.reg86.sw_peaking6_ratio_n23 = peaking_ctrl_ratio_N23[6];
807 dst_reg->sharp.reg86.sw_peaking6_ratio_p01 = peaking_ctrl_ratio_P01[6];
808 dst_reg->sharp.reg87.sw_peaking6_ratio_p12 = peaking_ctrl_ratio_P12[6];
809 dst_reg->sharp.reg87.sw_peaking6_ratio_p23 = peaking_ctrl_ratio_P23[6];
810
811 dst_reg->sharp.reg2.sw_peaking_v00 = p_shp_param->peaking_filt_core_V0[0];
812 dst_reg->sharp.reg2.sw_peaking_v01 = p_shp_param->peaking_filt_core_V0[1];
813 dst_reg->sharp.reg2.sw_peaking_v02 = p_shp_param->peaking_filt_core_V0[2];
814 dst_reg->sharp.reg2.sw_peaking_v10 = p_shp_param->peaking_filt_core_V1[0];
815 dst_reg->sharp.reg2.sw_peaking_v11 = p_shp_param->peaking_filt_core_V1[1];
816 dst_reg->sharp.reg2.sw_peaking_v12 = p_shp_param->peaking_filt_core_V1[2];
817 dst_reg->sharp.reg3.sw_peaking_v20 = p_shp_param->peaking_filt_core_V2[0];
818 dst_reg->sharp.reg3.sw_peaking_v21 = p_shp_param->peaking_filt_core_V2[1];
819 dst_reg->sharp.reg3.sw_peaking_v22 = p_shp_param->peaking_filt_core_V2[2];
820 dst_reg->sharp.reg3.sw_peaking_usm0 = p_shp_param->peaking_filt_core_USM[0];
821 dst_reg->sharp.reg3.sw_peaking_usm1 = p_shp_param->peaking_filt_core_USM[1];
822 dst_reg->sharp.reg3.sw_peaking_usm2 = p_shp_param->peaking_filt_core_USM[2];
823 dst_reg->sharp.reg3.sw_diag_coef = p_shp_param->peaking_filter_cfg_diag_enh_coef;
824 dst_reg->sharp.reg4.sw_peaking_h00 = p_shp_param->peaking_filt_core_H0[0];
825 dst_reg->sharp.reg4.sw_peaking_h01 = p_shp_param->peaking_filt_core_H0[1];
826 dst_reg->sharp.reg4.sw_peaking_h02 = p_shp_param->peaking_filt_core_H0[2];
827 dst_reg->sharp.reg6.sw_peaking_h10 = p_shp_param->peaking_filt_core_H1[0];
828 dst_reg->sharp.reg6.sw_peaking_h11 = p_shp_param->peaking_filt_core_H1[1];
829 dst_reg->sharp.reg6.sw_peaking_h12 = p_shp_param->peaking_filt_core_H1[2];
830 dst_reg->sharp.reg8.sw_peaking_h20 = p_shp_param->peaking_filt_core_H2[0];
831 dst_reg->sharp.reg8.sw_peaking_h21 = p_shp_param->peaking_filt_core_H2[1];
832 dst_reg->sharp.reg8.sw_peaking_h22 = p_shp_param->peaking_filt_core_H2[2];
833
834 dst_reg->sharp.reg100.sw_peaking_gain = p_shp_param->peaking_gain;
835 dst_reg->sharp.reg100.sw_nondir_thr = p_shp_param->peaking_edge_ctrl_non_dir_thr;
836 dst_reg->sharp.reg100.sw_dir_cmp_ratio = p_shp_param->peaking_edge_ctrl_dir_cmp_ratio;
837 dst_reg->sharp.reg100.sw_nondir_wgt_ratio = p_shp_param->peaking_edge_ctrl_non_dir_wgt_ratio;
838 dst_reg->sharp.reg101.sw_nondir_wgt_offset = p_shp_param->peaking_edge_ctrl_non_dir_wgt_offset;
839 dst_reg->sharp.reg101.sw_dir_cnt_thr = p_shp_param->peaking_edge_ctrl_dir_cnt_thr;
840 dst_reg->sharp.reg101.sw_dir_cnt_avg = p_shp_param->peaking_edge_ctrl_dir_cnt_avg;
841 dst_reg->sharp.reg101.sw_dir_cnt_offset = p_shp_param->peaking_edge_ctrl_dir_cnt_offset;
842 dst_reg->sharp.reg101.sw_diag_dir_thr = p_shp_param->peaking_edge_ctrl_diag_dir_thr;
843 dst_reg->sharp.reg102.sw_diag_adjgain_tab0 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[0];
844 dst_reg->sharp.reg102.sw_diag_adjgain_tab1 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[1];
845 dst_reg->sharp.reg102.sw_diag_adjgain_tab2 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[2];
846 dst_reg->sharp.reg102.sw_diag_adjgain_tab3 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[3];
847 dst_reg->sharp.reg102.sw_diag_adjgain_tab4 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[4];
848 dst_reg->sharp.reg102.sw_diag_adjgain_tab5 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[5];
849 dst_reg->sharp.reg102.sw_diag_adjgain_tab6 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[6];
850 dst_reg->sharp.reg102.sw_diag_adjgain_tab7 = p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab[7];
851
852 dst_reg->sharp.reg103.sw_edge_alpha_over_non = p_shp_param->peaking_estc_alpha_over_non;
853 dst_reg->sharp.reg103.sw_edge_alpha_under_non = p_shp_param->peaking_estc_alpha_under_non;
854 dst_reg->sharp.reg103.sw_edge_alpha_over_unlimit_non = p_shp_param->peaking_estc_alpha_over_unlimit_non;
855 dst_reg->sharp.reg103.sw_edge_alpha_under_unlimit_non = p_shp_param->peaking_estc_alpha_under_unlimit_non;
856
857 dst_reg->sharp.reg104.sw_edge_alpha_over_v = p_shp_param->peaking_estc_alpha_over_v;
858 dst_reg->sharp.reg104.sw_edge_alpha_under_v = p_shp_param->peaking_estc_alpha_under_v;
859 dst_reg->sharp.reg104.sw_edge_alpha_over_unlimit_v = p_shp_param->peaking_estc_alpha_over_unlimit_v;
860 dst_reg->sharp.reg104.sw_edge_alpha_under_unlimit_v = p_shp_param->peaking_estc_alpha_under_unlimit_v;
861
862 dst_reg->sharp.reg105.sw_edge_alpha_over_h = p_shp_param->peaking_estc_alpha_over_h;
863 dst_reg->sharp.reg105.sw_edge_alpha_under_h = p_shp_param->peaking_estc_alpha_under_h;
864 dst_reg->sharp.reg105.sw_edge_alpha_over_unlimit_h = p_shp_param->peaking_estc_alpha_over_unlimit_h;
865 dst_reg->sharp.reg105.sw_edge_alpha_under_unlimit_h = p_shp_param->peaking_estc_alpha_under_unlimit_h;
866
867 dst_reg->sharp.reg106.sw_edge_alpha_over_d0 = p_shp_param->peaking_estc_alpha_over_d0;
868 dst_reg->sharp.reg106.sw_edge_alpha_under_d0 = p_shp_param->peaking_estc_alpha_under_d0;
869 dst_reg->sharp.reg106.sw_edge_alpha_over_unlimit_d0 = p_shp_param->peaking_estc_alpha_over_unlimit_d0;
870 dst_reg->sharp.reg106.sw_edge_alpha_under_unlimit_d0 = p_shp_param->peaking_estc_alpha_under_unlimit_d0;
871
872 dst_reg->sharp.reg107.sw_edge_alpha_over_d1 = p_shp_param->peaking_estc_alpha_over_d1;
873 dst_reg->sharp.reg107.sw_edge_alpha_under_d1 = p_shp_param->peaking_estc_alpha_under_d1;
874 dst_reg->sharp.reg107.sw_edge_alpha_over_unlimit_d1 = p_shp_param->peaking_estc_alpha_over_unlimit_d1;
875 dst_reg->sharp.reg107.sw_edge_alpha_under_unlimit_d1 = p_shp_param->peaking_estc_alpha_under_unlimit_d1;
876
877 dst_reg->sharp.reg108.sw_edge_delta_offset_non = p_shp_param->peaking_estc_delta_offset_non;
878 dst_reg->sharp.reg108.sw_edge_delta_offset_v = p_shp_param->peaking_estc_delta_offset_v;
879 dst_reg->sharp.reg108.sw_edge_delta_offset_h = p_shp_param->peaking_estc_delta_offset_h;
880 dst_reg->sharp.reg109.sw_edge_delta_offset_d0 = p_shp_param->peaking_estc_delta_offset_d0;
881 dst_reg->sharp.reg109.sw_edge_delta_offset_d1 = p_shp_param->peaking_estc_delta_offset_d1;
882
883 dst_reg->sharp.reg110.sw_shoot_filt_radius = p_shp_param->shootctrl_filter_radius;
884 dst_reg->sharp.reg110.sw_shoot_delta_offset = p_shp_param->shootctrl_delta_offset;
885 dst_reg->sharp.reg110.sw_shoot_alpha_over = p_shp_param->shootctrl_alpha_over;
886 dst_reg->sharp.reg110.sw_shoot_alpha_under = p_shp_param->shootctrl_alpha_under;
887 dst_reg->sharp.reg111.sw_shoot_alpha_over_unlimit = p_shp_param->shootctrl_alpha_over_unlimit;
888 dst_reg->sharp.reg111.sw_shoot_alpha_under_unlimit = p_shp_param->shootctrl_alpha_under_unlimit;
889
890
891 //dst_reg->sharp.reg112.sw_adp_idx0 = p_shp_param->global_gain_adp_grd
892 dst_reg->sharp.reg112.sw_adp_idx0 = p_shp_param->global_gain_adp_grd[1] >> 2;
893 dst_reg->sharp.reg112.sw_adp_idx1 = p_shp_param->global_gain_adp_grd[2] >> 2;
894 dst_reg->sharp.reg112.sw_adp_idx2 = p_shp_param->global_gain_adp_grd[3] >> 2;
895 dst_reg->sharp.reg113.sw_adp_idx3 = p_shp_param->global_gain_adp_grd[4] >> 2;
896 dst_reg->sharp.reg113.sw_adp_gain0 = p_shp_param->global_gain_adp_val[0];
897 dst_reg->sharp.reg113.sw_adp_gain1 = p_shp_param->global_gain_adp_val[1];
898 dst_reg->sharp.reg114.sw_adp_gain2 = p_shp_param->global_gain_adp_val[2];
899 dst_reg->sharp.reg114.sw_adp_gain3 = p_shp_param->global_gain_adp_val[3];
900 dst_reg->sharp.reg114.sw_adp_gain4 = p_shp_param->global_gain_adp_val[4];
901 global_gain_slp_temp[0] = ROUND(128 * (float)(dst_reg->sharp.reg113.sw_adp_gain1 - dst_reg->sharp.reg113.sw_adp_gain0)
902 / MPP_MAX((float)(dst_reg->sharp.reg112.sw_adp_idx0 - 0), 1));
903 global_gain_slp_temp[1] = ROUND(128 * (float)(dst_reg->sharp.reg114.sw_adp_gain2 - dst_reg->sharp.reg113.sw_adp_gain1)
904 / MPP_MAX((float)(dst_reg->sharp.reg112.sw_adp_idx1 - dst_reg->sharp.reg112.sw_adp_idx0), 1));
905 global_gain_slp_temp[2] = ROUND(128 * (float)(dst_reg->sharp.reg114.sw_adp_gain3 - dst_reg->sharp.reg114.sw_adp_gain2)
906 / MPP_MAX((float)(dst_reg->sharp.reg112.sw_adp_idx2 - dst_reg->sharp.reg112.sw_adp_idx1), 1));
907 global_gain_slp_temp[3] = ROUND(128 * (float)(dst_reg->sharp.reg114.sw_adp_gain4 - dst_reg->sharp.reg114.sw_adp_gain3)
908 / MPP_MAX((float)(dst_reg->sharp.reg113.sw_adp_idx3 - dst_reg->sharp.reg112.sw_adp_idx2), 1));
909 global_gain_slp_temp[4] = ROUND(128 * (float)(p_shp_param->global_gain_adp_val[5] - dst_reg->sharp.reg114.sw_adp_gain4)
910 / MPP_MAX((float)(255 - dst_reg->sharp.reg113.sw_adp_idx3), 1));
911 dst_reg->sharp.reg115.sw_adp_slp01 = mpp_clip(global_gain_slp_temp[0], -1024, 1023);
912 dst_reg->sharp.reg115.sw_adp_slp12 = mpp_clip(global_gain_slp_temp[1], -1024, 1023);
913 dst_reg->sharp.reg128.sw_adp_slp23 = mpp_clip(global_gain_slp_temp[2], -1024, 1023);
914 dst_reg->sharp.reg128.sw_adp_slp34 = mpp_clip(global_gain_slp_temp[3], -1024, 1023);
915 dst_reg->sharp.reg129.sw_adp_slp45 = mpp_clip(global_gain_slp_temp[4], -1024, 1023);
916
917 dst_reg->sharp.reg129.sw_var_idx0 = p_shp_param->global_gain_var_grd[1] >> 2;
918 dst_reg->sharp.reg129.sw_var_idx1 = p_shp_param->global_gain_var_grd[2] >> 2;
919 dst_reg->sharp.reg130.sw_var_idx2 = p_shp_param->global_gain_var_grd[3] >> 2;
920 dst_reg->sharp.reg130.sw_var_idx3 = p_shp_param->global_gain_var_grd[4] >> 2;
921 dst_reg->sharp.reg130.sw_var_gain0 = p_shp_param->global_gain_var_val[0];
922 dst_reg->sharp.reg131.sw_var_gain1 = p_shp_param->global_gain_var_val[1];
923 dst_reg->sharp.reg131.sw_var_gain2 = p_shp_param->global_gain_var_val[2];
924 dst_reg->sharp.reg131.sw_var_gain3 = p_shp_param->global_gain_var_val[3];
925 dst_reg->sharp.reg131.sw_var_gain4 = p_shp_param->global_gain_var_val[4];
926 global_gain_slp_temp[0] = ROUND(128 * (float)(dst_reg->sharp.reg131.sw_var_gain1 - dst_reg->sharp.reg130.sw_var_gain0)
927 / MPP_MAX((float)(dst_reg->sharp.reg129.sw_var_idx0 - 0), 1));
928 global_gain_slp_temp[1] = ROUND(128 * (float)(dst_reg->sharp.reg131.sw_var_gain2 - dst_reg->sharp.reg131.sw_var_gain1)
929 / MPP_MAX((float)(dst_reg->sharp.reg129.sw_var_idx1 - dst_reg->sharp.reg129.sw_var_idx0), 1));
930 global_gain_slp_temp[2] = ROUND(128 * (float)(dst_reg->sharp.reg131.sw_var_gain3 - dst_reg->sharp.reg131.sw_var_gain2)
931 / MPP_MAX((float)(dst_reg->sharp.reg130.sw_var_idx2 - dst_reg->sharp.reg129.sw_var_idx1), 1));
932 global_gain_slp_temp[3] = ROUND(128 * (float)(dst_reg->sharp.reg131.sw_var_gain4 - dst_reg->sharp.reg131.sw_var_gain3)
933 / MPP_MAX((float)(dst_reg->sharp.reg130.sw_var_idx3 - dst_reg->sharp.reg130.sw_var_idx2), 1));
934 global_gain_slp_temp[4] = ROUND(128 * (float)(p_shp_param->global_gain_var_val[5] - dst_reg->sharp.reg131.sw_var_gain4)
935 / MPP_MAX((float)(255 - dst_reg->sharp.reg130.sw_var_idx3), 1));
936 dst_reg->sharp.reg132.sw_var_slp01 = mpp_clip(global_gain_slp_temp[0], -1024, 1023);
937 dst_reg->sharp.reg132.sw_var_slp12 = mpp_clip(global_gain_slp_temp[1], -1024, 1023);
938 dst_reg->sharp.reg133.sw_var_slp23 = mpp_clip(global_gain_slp_temp[2], -1024, 1023);
939 dst_reg->sharp.reg133.sw_var_slp34 = mpp_clip(global_gain_slp_temp[3], -1024, 1023);
940 dst_reg->sharp.reg134.sw_var_slp45 = mpp_clip(global_gain_slp_temp[4], -1024, 1023);
941
942 dst_reg->sharp.reg134.sw_lum_select = p_shp_param->global_gain_lum_mode;
943 dst_reg->sharp.reg134.sw_lum_idx0 = p_shp_param->global_gain_lum_grd[1] >> 2;
944 dst_reg->sharp.reg135.sw_lum_idx1 = p_shp_param->global_gain_lum_grd[2] >> 2;
945 dst_reg->sharp.reg135.sw_lum_idx2 = p_shp_param->global_gain_lum_grd[3] >> 2;
946 dst_reg->sharp.reg135.sw_lum_idx3 = p_shp_param->global_gain_lum_grd[4] >> 2;
947 dst_reg->sharp.reg136.sw_lum_gain0 = p_shp_param->global_gain_lum_val[0];
948 dst_reg->sharp.reg136.sw_lum_gain1 = p_shp_param->global_gain_lum_val[1];
949 dst_reg->sharp.reg136.sw_lum_gain2 = p_shp_param->global_gain_lum_val[2];
950 dst_reg->sharp.reg136.sw_lum_gain3 = p_shp_param->global_gain_lum_val[3];
951 dst_reg->sharp.reg137.sw_lum_gain4 = p_shp_param->global_gain_lum_val[4];
952 global_gain_slp_temp[0] = ROUND(128 * (float)(dst_reg->sharp.reg136.sw_lum_gain1 - dst_reg->sharp.reg136.sw_lum_gain0)
953 / MPP_MAX((float)(dst_reg->sharp.reg134.sw_lum_idx0 - 0), 1));
954 global_gain_slp_temp[1] = ROUND(128 * (float)(dst_reg->sharp.reg136.sw_lum_gain2 - dst_reg->sharp.reg136.sw_lum_gain1)
955 / MPP_MAX((float)(dst_reg->sharp.reg135.sw_lum_idx1 - dst_reg->sharp.reg134.sw_lum_idx0), 1));
956 global_gain_slp_temp[2] = ROUND(128 * (float)(dst_reg->sharp.reg136.sw_lum_gain3 - dst_reg->sharp.reg136.sw_lum_gain2)
957 / MPP_MAX((float)(dst_reg->sharp.reg135.sw_lum_idx2 - dst_reg->sharp.reg135.sw_lum_idx1), 1));
958 global_gain_slp_temp[3] = ROUND(128 * (float)(dst_reg->sharp.reg137.sw_lum_gain4 - dst_reg->sharp.reg136.sw_lum_gain3)
959 / MPP_MAX((float)(dst_reg->sharp.reg135.sw_lum_idx3 - dst_reg->sharp.reg135.sw_lum_idx2), 1));
960 global_gain_slp_temp[4] = ROUND(128 * (float)(p_shp_param->global_gain_lum_val[5] - dst_reg->sharp.reg137.sw_lum_gain4)
961 / MPP_MAX((float)(255 - dst_reg->sharp.reg135.sw_lum_idx3), 1));
962 dst_reg->sharp.reg137.sw_lum_slp01 = mpp_clip(global_gain_slp_temp[0], -1024, 1023);
963 dst_reg->sharp.reg137.sw_lum_slp12 = mpp_clip(global_gain_slp_temp[1], -1024, 1023);
964 dst_reg->sharp.reg138.sw_lum_slp23 = mpp_clip(global_gain_slp_temp[2], -1024, 1023);
965 dst_reg->sharp.reg138.sw_lum_slp34 = mpp_clip(global_gain_slp_temp[3], -1024, 1023);
966 dst_reg->sharp.reg139.sw_lum_slp45 = mpp_clip(global_gain_slp_temp[4], -1024, 1023);
967
968
969 dst_reg->sharp.reg140.sw_adj_point_x0 = p_shp_param->color_ctrl_p0_point_u;
970 dst_reg->sharp.reg140.sw_adj_point_y0 = p_shp_param->color_ctrl_p0_point_v;
971 dst_reg->sharp.reg140.sw_adj_scaling_coef0 = p_shp_param->color_ctrl_p0_scaling_coef;
972 dst_reg->sharp.reg141.sw_coloradj_tab0_0 = p_shp_param->color_ctrl_p0_roll_tab[0];
973 dst_reg->sharp.reg141.sw_coloradj_tab0_1 = p_shp_param->color_ctrl_p0_roll_tab[1];
974 dst_reg->sharp.reg141.sw_coloradj_tab0_2 = p_shp_param->color_ctrl_p0_roll_tab[2];
975 dst_reg->sharp.reg141.sw_coloradj_tab0_3 = p_shp_param->color_ctrl_p0_roll_tab[3];
976 dst_reg->sharp.reg141.sw_coloradj_tab0_4 = p_shp_param->color_ctrl_p0_roll_tab[4];
977 dst_reg->sharp.reg141.sw_coloradj_tab0_5 = p_shp_param->color_ctrl_p0_roll_tab[5];
978 dst_reg->sharp.reg142.sw_coloradj_tab0_6 = p_shp_param->color_ctrl_p0_roll_tab[6];
979 dst_reg->sharp.reg142.sw_coloradj_tab0_7 = p_shp_param->color_ctrl_p0_roll_tab[7];
980 dst_reg->sharp.reg142.sw_coloradj_tab0_8 = p_shp_param->color_ctrl_p0_roll_tab[8];
981 dst_reg->sharp.reg142.sw_coloradj_tab0_9 = p_shp_param->color_ctrl_p0_roll_tab[9];
982 dst_reg->sharp.reg142.sw_coloradj_tab0_10 = p_shp_param->color_ctrl_p0_roll_tab[10];
983 dst_reg->sharp.reg142.sw_coloradj_tab0_11 = p_shp_param->color_ctrl_p0_roll_tab[11];
984 dst_reg->sharp.reg143.sw_coloradj_tab0_12 = p_shp_param->color_ctrl_p0_roll_tab[12];
985 dst_reg->sharp.reg143.sw_coloradj_tab0_13 = p_shp_param->color_ctrl_p0_roll_tab[13];
986 dst_reg->sharp.reg143.sw_coloradj_tab0_14 = p_shp_param->color_ctrl_p0_roll_tab[14];
987 dst_reg->sharp.reg143.sw_coloradj_tab0_15 = p_shp_param->color_ctrl_p0_roll_tab[15];
988
989 dst_reg->sharp.reg144.sw_adj_point_x1 = p_shp_param->color_ctrl_p1_point_u;
990 dst_reg->sharp.reg144.sw_adj_point_y1 = p_shp_param->color_ctrl_p1_point_v;
991 dst_reg->sharp.reg144.sw_adj_scaling_coef1 = p_shp_param->color_ctrl_p1_scaling_coef;
992 dst_reg->sharp.reg145.sw_coloradj_tab1_0 = p_shp_param->color_ctrl_p1_roll_tab[0];
993 dst_reg->sharp.reg145.sw_coloradj_tab1_1 = p_shp_param->color_ctrl_p1_roll_tab[1];
994 dst_reg->sharp.reg145.sw_coloradj_tab1_2 = p_shp_param->color_ctrl_p1_roll_tab[2];
995 dst_reg->sharp.reg145.sw_coloradj_tab1_3 = p_shp_param->color_ctrl_p1_roll_tab[3];
996 dst_reg->sharp.reg145.sw_coloradj_tab1_4 = p_shp_param->color_ctrl_p1_roll_tab[4];
997 dst_reg->sharp.reg145.sw_coloradj_tab1_5 = p_shp_param->color_ctrl_p1_roll_tab[5];
998 dst_reg->sharp.reg146.sw_coloradj_tab1_6 = p_shp_param->color_ctrl_p1_roll_tab[6];
999 dst_reg->sharp.reg146.sw_coloradj_tab1_7 = p_shp_param->color_ctrl_p1_roll_tab[7];
1000 dst_reg->sharp.reg146.sw_coloradj_tab1_8 = p_shp_param->color_ctrl_p1_roll_tab[8];
1001 dst_reg->sharp.reg146.sw_coloradj_tab1_9 = p_shp_param->color_ctrl_p1_roll_tab[9];
1002 dst_reg->sharp.reg146.sw_coloradj_tab1_10 = p_shp_param->color_ctrl_p1_roll_tab[10];
1003 dst_reg->sharp.reg146.sw_coloradj_tab1_11 = p_shp_param->color_ctrl_p1_roll_tab[11];
1004 dst_reg->sharp.reg147.sw_coloradj_tab1_12 = p_shp_param->color_ctrl_p1_roll_tab[12];
1005 dst_reg->sharp.reg147.sw_coloradj_tab1_13 = p_shp_param->color_ctrl_p1_roll_tab[13];
1006 dst_reg->sharp.reg147.sw_coloradj_tab1_14 = p_shp_param->color_ctrl_p1_roll_tab[14];
1007 dst_reg->sharp.reg147.sw_coloradj_tab1_15 = p_shp_param->color_ctrl_p1_roll_tab[15];
1008
1009 dst_reg->sharp.reg148.sw_adj_point_x2 = p_shp_param->color_ctrl_p2_point_u;
1010 dst_reg->sharp.reg148.sw_adj_point_y2 = p_shp_param->color_ctrl_p2_point_v;
1011 dst_reg->sharp.reg148.sw_adj_scaling_coef2 = p_shp_param->color_ctrl_p2_scaling_coef;
1012 dst_reg->sharp.reg149.sw_coloradj_tab2_0 = p_shp_param->color_ctrl_p2_roll_tab[0];
1013 dst_reg->sharp.reg149.sw_coloradj_tab2_1 = p_shp_param->color_ctrl_p2_roll_tab[1];
1014 dst_reg->sharp.reg149.sw_coloradj_tab2_2 = p_shp_param->color_ctrl_p2_roll_tab[2];
1015 dst_reg->sharp.reg149.sw_coloradj_tab2_3 = p_shp_param->color_ctrl_p2_roll_tab[3];
1016 dst_reg->sharp.reg149.sw_coloradj_tab2_4 = p_shp_param->color_ctrl_p2_roll_tab[4];
1017 dst_reg->sharp.reg149.sw_coloradj_tab2_5 = p_shp_param->color_ctrl_p2_roll_tab[5];
1018 dst_reg->sharp.reg150.sw_coloradj_tab2_6 = p_shp_param->color_ctrl_p2_roll_tab[6];
1019 dst_reg->sharp.reg150.sw_coloradj_tab2_7 = p_shp_param->color_ctrl_p2_roll_tab[7];
1020 dst_reg->sharp.reg150.sw_coloradj_tab2_8 = p_shp_param->color_ctrl_p2_roll_tab[8];
1021 dst_reg->sharp.reg150.sw_coloradj_tab2_9 = p_shp_param->color_ctrl_p2_roll_tab[9];
1022 dst_reg->sharp.reg150.sw_coloradj_tab2_10 = p_shp_param->color_ctrl_p2_roll_tab[10];
1023 dst_reg->sharp.reg150.sw_coloradj_tab2_11 = p_shp_param->color_ctrl_p2_roll_tab[11];
1024 dst_reg->sharp.reg151.sw_coloradj_tab2_12 = p_shp_param->color_ctrl_p2_roll_tab[12];
1025 dst_reg->sharp.reg151.sw_coloradj_tab2_13 = p_shp_param->color_ctrl_p2_roll_tab[13];
1026 dst_reg->sharp.reg151.sw_coloradj_tab2_14 = p_shp_param->color_ctrl_p2_roll_tab[14];
1027 dst_reg->sharp.reg151.sw_coloradj_tab2_15 = p_shp_param->color_ctrl_p2_roll_tab[15];
1028
1029 dst_reg->sharp.reg152.sw_adj_point_x3 = p_shp_param->color_ctrl_p3_point_u;
1030 dst_reg->sharp.reg152.sw_adj_point_y3 = p_shp_param->color_ctrl_p3_point_v;
1031 dst_reg->sharp.reg152.sw_adj_scaling_coef3 = p_shp_param->color_ctrl_p3_scaling_coef;
1032 dst_reg->sharp.reg153.sw_coloradj_tab3_0 = p_shp_param->color_ctrl_p3_roll_tab[0];
1033 dst_reg->sharp.reg153.sw_coloradj_tab3_1 = p_shp_param->color_ctrl_p3_roll_tab[1];
1034 dst_reg->sharp.reg153.sw_coloradj_tab3_2 = p_shp_param->color_ctrl_p3_roll_tab[2];
1035 dst_reg->sharp.reg153.sw_coloradj_tab3_3 = p_shp_param->color_ctrl_p3_roll_tab[3];
1036 dst_reg->sharp.reg153.sw_coloradj_tab3_4 = p_shp_param->color_ctrl_p3_roll_tab[4];
1037 dst_reg->sharp.reg153.sw_coloradj_tab3_5 = p_shp_param->color_ctrl_p3_roll_tab[5];
1038 dst_reg->sharp.reg154.sw_coloradj_tab3_6 = p_shp_param->color_ctrl_p3_roll_tab[6];
1039 dst_reg->sharp.reg154.sw_coloradj_tab3_7 = p_shp_param->color_ctrl_p3_roll_tab[7];
1040 dst_reg->sharp.reg154.sw_coloradj_tab3_8 = p_shp_param->color_ctrl_p3_roll_tab[8];
1041 dst_reg->sharp.reg154.sw_coloradj_tab3_9 = p_shp_param->color_ctrl_p3_roll_tab[9];
1042 dst_reg->sharp.reg154.sw_coloradj_tab3_10 = p_shp_param->color_ctrl_p3_roll_tab[10];
1043 dst_reg->sharp.reg154.sw_coloradj_tab3_11 = p_shp_param->color_ctrl_p3_roll_tab[11];
1044 dst_reg->sharp.reg155.sw_coloradj_tab3_12 = p_shp_param->color_ctrl_p3_roll_tab[12];
1045 dst_reg->sharp.reg155.sw_coloradj_tab3_13 = p_shp_param->color_ctrl_p3_roll_tab[13];
1046 dst_reg->sharp.reg155.sw_coloradj_tab3_14 = p_shp_param->color_ctrl_p3_roll_tab[14];
1047 dst_reg->sharp.reg155.sw_coloradj_tab3_15 = p_shp_param->color_ctrl_p3_roll_tab[15];
1048
1049
1050 dst_reg->sharp.reg156.sw_idxmode_select = p_shp_param->tex_adj_mode_select;
1051 dst_reg->sharp.reg156.sw_ymode_select = p_shp_param->tex_adj_y_mode_select;
1052 dst_reg->sharp.reg156.sw_tex_idx0 = p_shp_param->tex_adj_grd[1] >> 2;
1053 dst_reg->sharp.reg156.sw_tex_idx1 = p_shp_param->tex_adj_grd[2] >> 2;
1054 dst_reg->sharp.reg157.sw_tex_idx2 = p_shp_param->tex_adj_grd[3] >> 2;
1055 dst_reg->sharp.reg157.sw_tex_idx3 = p_shp_param->tex_adj_grd[4] >> 2;
1056 dst_reg->sharp.reg157.sw_tex_gain0 = p_shp_param->tex_adj_val[0];
1057 dst_reg->sharp.reg158.sw_tex_gain1 = p_shp_param->tex_adj_val[1];
1058 dst_reg->sharp.reg158.sw_tex_gain2 = p_shp_param->tex_adj_val[2];
1059 dst_reg->sharp.reg158.sw_tex_gain3 = p_shp_param->tex_adj_val[3];
1060 dst_reg->sharp.reg158.sw_tex_gain4 = p_shp_param->tex_adj_val[4];
1061 global_gain_slp_temp[0] = ROUND(128 * (float)(dst_reg->sharp.reg158.sw_tex_gain1 - dst_reg->sharp.reg157.sw_tex_gain0)
1062 / MPP_MAX((float)(dst_reg->sharp.reg156.sw_tex_idx0 - 0), 1));
1063 global_gain_slp_temp[1] = ROUND(128 * (float)(dst_reg->sharp.reg158.sw_tex_gain2 - dst_reg->sharp.reg158.sw_tex_gain1)
1064 / MPP_MAX((float)(dst_reg->sharp.reg156.sw_tex_idx1 - dst_reg->sharp.reg156.sw_tex_idx0), 1));
1065 global_gain_slp_temp[2] = ROUND(128 * (float)(dst_reg->sharp.reg158.sw_tex_gain3 - dst_reg->sharp.reg158.sw_tex_gain2)
1066 / MPP_MAX((float)(dst_reg->sharp.reg157.sw_tex_idx2 - dst_reg->sharp.reg156.sw_tex_idx1), 1));
1067 global_gain_slp_temp[3] = ROUND(128 * (float)(dst_reg->sharp.reg158.sw_tex_gain4 - dst_reg->sharp.reg158.sw_tex_gain3)
1068 / MPP_MAX((float)(dst_reg->sharp.reg157.sw_tex_idx3 - dst_reg->sharp.reg157.sw_tex_idx2), 1));
1069 global_gain_slp_temp[4] = ROUND(128 * (float)(p_shp_param->tex_adj_val[5] - dst_reg->sharp.reg158.sw_tex_gain4)
1070 / MPP_MAX((float)(255 - dst_reg->sharp.reg157.sw_tex_idx3), 1));
1071 dst_reg->sharp.reg159.sw_tex_slp01 = mpp_clip(global_gain_slp_temp[0], -1024, 1023);
1072 dst_reg->sharp.reg159.sw_tex_slp12 = mpp_clip(global_gain_slp_temp[1], -1024, 1023);
1073 dst_reg->sharp.reg160.sw_tex_slp23 = mpp_clip(global_gain_slp_temp[2], -1024, 1023);
1074 dst_reg->sharp.reg160.sw_tex_slp34 = mpp_clip(global_gain_slp_temp[3], -1024, 1023);
1075 dst_reg->sharp.reg161.sw_tex_slp45 = mpp_clip(global_gain_slp_temp[4], -1024, 1023);
1076
1077 }
1078
vdpp2_params_to_reg(struct vdpp2_params * src_params,struct vdpp2_api_ctx * ctx)1079 static MPP_RET vdpp2_params_to_reg(struct vdpp2_params* src_params, struct vdpp2_api_ctx *ctx)
1080 {
1081 struct vdpp2_reg *dst_reg = &ctx->reg;
1082 struct zme_params *zme_params = &src_params->zme_params;
1083
1084 memset(dst_reg, 0, sizeof(*dst_reg));
1085
1086 dst_reg->common.reg0.sw_vdpp_frm_en = 1;
1087
1088 /* 0x0004(reg1), TODO: add debug function */
1089 dst_reg->common.reg1.sw_vdpp_src_fmt = VDPP_FMT_YUV420;
1090 dst_reg->common.reg1.sw_vdpp_src_yuv_swap = src_params->src_yuv_swap;
1091
1092 if (MPP_FMT_YUV420SP_VU == src_params->src_fmt)
1093 dst_reg->common.reg1.sw_vdpp_src_yuv_swap = 1;
1094
1095 dst_reg->common.reg1.sw_vdpp_dst_fmt = src_params->dst_fmt;
1096 dst_reg->common.reg1.sw_vdpp_dst_yuv_swap = src_params->dst_yuv_swap;
1097 dst_reg->common.reg1.sw_vdpp_dbmsr_en = (src_params->working_mode == VDPP_WORK_MODE_DCI)
1098 ? 0
1099 : src_params->dmsr_params.dmsr_enable;
1100
1101 /* 0x0008(reg2) */
1102 dst_reg->common.reg2.sw_vdpp_working_mode = src_params->working_mode;
1103 VDPP2_DBG(VDPP2_DBG_TRACE, "working_mode %d", src_params->working_mode);
1104
1105 /* 0x000C ~ 0x001C(reg3 ~ reg7), skip */
1106 dst_reg->common.reg4.sw_vdpp_clk_on = 1;
1107 dst_reg->common.reg4.sw_md_clk_on = 1;
1108 dst_reg->common.reg4.sw_dect_clk_on = 1;
1109 dst_reg->common.reg4.sw_me_clk_on = 1;
1110 dst_reg->common.reg4.sw_mc_clk_on = 1;
1111 dst_reg->common.reg4.sw_eedi_clk_on = 1;
1112 dst_reg->common.reg4.sw_ble_clk_on = 1;
1113 dst_reg->common.reg4.sw_out_clk_on = 1;
1114 dst_reg->common.reg4.sw_ctrl_clk_on = 1;
1115 dst_reg->common.reg4.sw_ram_clk_on = 1;
1116 dst_reg->common.reg4.sw_dma_clk_on = 1;
1117 dst_reg->common.reg4.sw_reg_clk_on = 1;
1118
1119 /* 0x0020(reg8) */
1120 dst_reg->common.reg8.sw_vdpp_frm_done_en = 1;
1121 dst_reg->common.reg8.sw_vdpp_osd_max_en = 1;
1122 dst_reg->common.reg8.sw_vdpp_bus_error_en = 1;
1123 dst_reg->common.reg8.sw_vdpp_timeout_int_en = 1;
1124 dst_reg->common.reg8.sw_vdpp_config_error_en = 1;
1125 /* 0x0024 ~ 0x002C(reg9 ~ reg11), skip */
1126 {
1127 RK_U32 src_right_redundant = src_params->src_width % 16 == 0 ? 0 : 16 - src_params->src_width % 16;
1128 RK_U32 src_down_redundant = src_params->src_height % 8 == 0 ? 0 : 8 - src_params->src_height % 8;
1129 RK_U32 dst_right_redundant = src_params->dst_width % 16 == 0 ? 0 : 16 - src_params->dst_width % 16;
1130 /* 0x0030(reg12) */
1131 dst_reg->common.reg12.sw_vdpp_src_vir_y_stride = src_params->src_width_vir / 4;
1132
1133 /* 0x0034(reg13) */
1134 dst_reg->common.reg13.sw_vdpp_dst_vir_y_stride = src_params->dst_width_vir / 4;
1135
1136 /* 0x0038(reg14) */
1137 dst_reg->common.reg14.sw_vdpp_src_pic_width = src_params->src_width + src_right_redundant - 1;
1138 dst_reg->common.reg14.sw_vdpp_src_right_redundant = src_right_redundant;
1139 dst_reg->common.reg14.sw_vdpp_src_pic_height = src_params->src_height + src_down_redundant - 1;
1140 dst_reg->common.reg14.sw_vdpp_src_down_redundant = src_down_redundant;
1141
1142 /* 0x003C(reg15) */
1143 dst_reg->common.reg15.sw_vdpp_dst_pic_width = src_params->dst_width + dst_right_redundant - 1;
1144 dst_reg->common.reg15.sw_vdpp_dst_right_redundant = dst_right_redundant;
1145 dst_reg->common.reg15.sw_vdpp_dst_pic_height = src_params->dst_height - 1;
1146 }
1147 /* 0x0040 ~ 0x005C(reg16 ~ reg23), skip */
1148 dst_reg->common.reg20.sw_vdpp_timeout_en = 1;
1149 dst_reg->common.reg20.sw_vdpp_timeout_cnt = 0x8FFFFFF;
1150
1151 /* 0x0060(reg24) */
1152 dst_reg->common.reg24.sw_vdpp_src_addr_y = src_params->src.y;
1153
1154 /* 0x0064(reg25) */
1155 dst_reg->common.reg25.sw_vdpp_src_addr_uv = src_params->src.cbcr;
1156
1157 /* 0x0068(reg26) */
1158 dst_reg->common.reg26.sw_vdpp_dst_addr_y = src_params->dst.y;
1159
1160 /* 0x006C(reg27) */
1161 dst_reg->common.reg27.sw_vdpp_dst_addr_uv = src_params->dst.cbcr;
1162
1163 if (src_params->yuv_out_diff) {
1164 RK_U32 dst_right_redundant_c = src_params->dst_c_width % 16 == 0 ? 0 : 16 - src_params->dst_c_width % 16;
1165
1166 dst_reg->common.reg1.sw_vdpp_yuvout_diff_en = src_params->yuv_out_diff;
1167 dst_reg->common.reg13.sw_vdpp_dst_vir_c_stride = src_params->dst_c_width_vir / 4;
1168 /* 0x0040(reg16) */
1169 dst_reg->common.reg16.sw_vdpp_dst_pic_width_c = src_params->dst_c_width + dst_right_redundant_c - 1;
1170 dst_reg->common.reg16.sw_vdpp_dst_right_redundant_c = dst_right_redundant_c;
1171 dst_reg->common.reg16.sw_vdpp_dst_pic_height_c = src_params->dst_c_height - 1;
1172
1173 dst_reg->common.reg27.sw_vdpp_dst_addr_uv = src_params->dst_c.cbcr;
1174 }
1175
1176 set_dmsr_to_vdpp_reg(&src_params->dmsr_params, &ctx->dmsr);
1177 set_hist_to_vdpp2_reg(src_params, dst_reg);
1178 set_es_to_vdpp2_reg(src_params, dst_reg);
1179 set_shp_to_vdpp2_reg(src_params, dst_reg);
1180
1181 zme_params->src_width = src_params->src_width;
1182 zme_params->src_height = src_params->src_height;
1183 zme_params->dst_width = src_params->dst_width;
1184 zme_params->dst_height = src_params->dst_height;
1185 zme_params->dst_fmt = src_params->dst_fmt;
1186 zme_params->yuv_out_diff = src_params->yuv_out_diff;
1187 zme_params->dst_c_width = src_params->dst_c_width;
1188 zme_params->dst_c_height = src_params->dst_c_height;
1189 set_zme_to_vdpp_reg(zme_params, &ctx->zme);
1190
1191 return MPP_OK;
1192 }
1193
vdpp2_set_default_dmsr_param(struct dmsr_params * p_dmsr_param)1194 static void vdpp2_set_default_dmsr_param(struct dmsr_params* p_dmsr_param)
1195 {
1196 p_dmsr_param->dmsr_enable = 1;
1197 p_dmsr_param->dmsr_str_pri_y = 10;
1198 p_dmsr_param->dmsr_str_sec_y = 4;
1199 p_dmsr_param->dmsr_dumping_y = 6;
1200 p_dmsr_param->dmsr_wgt_pri_gain_even_1 = 12;
1201 p_dmsr_param->dmsr_wgt_pri_gain_even_2 = 12;
1202 p_dmsr_param->dmsr_wgt_pri_gain_odd_1 = 8;
1203 p_dmsr_param->dmsr_wgt_pri_gain_odd_2 = 16;
1204 p_dmsr_param->dmsr_wgt_sec_gain = 5;
1205 p_dmsr_param->dmsr_blk_flat_th = 20;
1206 p_dmsr_param->dmsr_contrast_to_conf_map_x0 = 1680;
1207 p_dmsr_param->dmsr_contrast_to_conf_map_x1 = 6720;
1208 p_dmsr_param->dmsr_contrast_to_conf_map_y0 = 0;
1209 p_dmsr_param->dmsr_contrast_to_conf_map_y1 = 65535;
1210 p_dmsr_param->dmsr_diff_core_th0 = 1;
1211 p_dmsr_param->dmsr_diff_core_th1 = 5;
1212 p_dmsr_param->dmsr_diff_core_wgt0 = 16;
1213 p_dmsr_param->dmsr_diff_core_wgt1 = 16;
1214 p_dmsr_param->dmsr_diff_core_wgt2 = 16;
1215 p_dmsr_param->dmsr_edge_th_low_arr[0] = 30;
1216 p_dmsr_param->dmsr_edge_th_low_arr[1] = 10;
1217 p_dmsr_param->dmsr_edge_th_low_arr[2] = 0;
1218 p_dmsr_param->dmsr_edge_th_low_arr[3] = 0;
1219 p_dmsr_param->dmsr_edge_th_low_arr[4] = 0;
1220 p_dmsr_param->dmsr_edge_th_low_arr[5] = 0;
1221 p_dmsr_param->dmsr_edge_th_low_arr[6] = 0;
1222 p_dmsr_param->dmsr_edge_th_high_arr[0] = 60;
1223 p_dmsr_param->dmsr_edge_th_high_arr[1] = 40;
1224 p_dmsr_param->dmsr_edge_th_high_arr[2] = 20;
1225 p_dmsr_param->dmsr_edge_th_high_arr[3] = 10;
1226 p_dmsr_param->dmsr_edge_th_high_arr[4] = 10;
1227 p_dmsr_param->dmsr_edge_th_high_arr[5] = 10;
1228 p_dmsr_param->dmsr_edge_th_high_arr[6] = 10;
1229 }
1230
vdpp_set_default_es_param(EsParams * p_es_param)1231 static void vdpp_set_default_es_param(EsParams* p_es_param)
1232 {
1233 p_es_param->es_bEnabledES = 0;
1234 p_es_param->es_iAngleDelta = 17;
1235 p_es_param->es_iAngleDeltaExtra = 5;
1236 p_es_param->es_iGradNoDirTh = 37;
1237 p_es_param->es_iGradFlatTh = 75;
1238 p_es_param->es_iWgtGain = 128;
1239 p_es_param->es_iWgtDecay = 128;
1240 p_es_param->es_iLowConfTh = 96;
1241 p_es_param->es_iLowConfRatio = 32;
1242 p_es_param->es_iConfCntTh = 4;
1243 p_es_param->es_iWgtLocalTh = 64;
1244 p_es_param->es_iK1 = 4096;
1245 p_es_param->es_iK2 = 7168;
1246 p_es_param->es_iDeltaLimit = 65280;
1247 memcpy(&p_es_param->es_iDiff2conf_lut_x[0], &diff2conf_lut_x_tmp[0], sizeof(diff2conf_lut_x_tmp));
1248 memcpy(&p_es_param->es_iDiff2conf_lut_y[0], &diff2conf_lut_y_tmp[0], sizeof(diff2conf_lut_y_tmp));
1249 p_es_param->es_bEndpointCheckEnable = 1;
1250 }
1251
vdpp_set_default_shp_param(ShpParams * p_shp_param)1252 static void vdpp_set_default_shp_param(ShpParams* p_shp_param)
1253 {
1254
1255 p_shp_param->sharp_enable = 1;
1256 p_shp_param->sharp_coloradj_bypass_en = 1;
1257
1258 p_shp_param->lti_h_enable = 0;
1259 p_shp_param->lti_h_radius = 1;
1260 p_shp_param->lti_h_slope = 100;
1261 p_shp_param->lti_h_thresold = 21;
1262 p_shp_param->lti_h_gain = 8;
1263 p_shp_param->lti_h_noise_thr_pos = 1023;
1264 p_shp_param->lti_h_noise_thr_neg = 1023;
1265
1266 p_shp_param->lti_v_enable = 0;
1267 p_shp_param->lti_v_radius = 1;
1268 p_shp_param->lti_v_slope = 100;
1269 p_shp_param->lti_v_thresold = 21;
1270 p_shp_param->lti_v_gain = 8;
1271 p_shp_param->lti_v_noise_thr_pos = 1023;
1272 p_shp_param->lti_v_noise_thr_neg = 1023;
1273
1274 p_shp_param->cti_h_enable = 0;
1275 p_shp_param->cti_h_radius = 1;
1276 p_shp_param->cti_h_slope = 100;
1277 p_shp_param->cti_h_thresold = 21;
1278 p_shp_param->cti_h_gain = 8;
1279 p_shp_param->cti_h_noise_thr_pos = 1023;
1280 p_shp_param->cti_h_noise_thr_neg = 1023;
1281
1282 p_shp_param->peaking_enable = 1;
1283 p_shp_param->peaking_gain = 196;
1284
1285 p_shp_param->peaking_coring_enable = 1;
1286 p_shp_param->peaking_limit_ctrl_enable = 1;
1287 p_shp_param->peaking_gain_enable = 1;
1288
1289 memcpy(p_shp_param->peaking_coring_zero, coring_zero_tmp, sizeof(coring_zero_tmp));
1290 memcpy(p_shp_param->peaking_coring_thr, coring_thr_tmp, sizeof(coring_thr_tmp));
1291 memcpy(p_shp_param->peaking_coring_ratio, coring_ratio_tmp, sizeof(coring_ratio_tmp));
1292 memcpy(p_shp_param->peaking_gain_pos, gain_pos_tmp, sizeof(gain_pos_tmp));
1293 memcpy(p_shp_param->peaking_gain_neg, gain_neg_tmp, sizeof(gain_neg_tmp));
1294 memcpy(p_shp_param->peaking_limit_ctrl_pos0, limit_ctrl_pos0_tmp, sizeof(limit_ctrl_pos0_tmp));
1295 memcpy(p_shp_param->peaking_limit_ctrl_pos1, limit_ctrl_pos1_tmp, sizeof(limit_ctrl_pos1_tmp));
1296 memcpy(p_shp_param->peaking_limit_ctrl_neg0, limit_ctrl_neg0_tmp, sizeof(limit_ctrl_neg0_tmp));
1297 memcpy(p_shp_param->peaking_limit_ctrl_neg1, limit_ctrl_neg1_tmp, sizeof(limit_ctrl_neg1_tmp));
1298 memcpy(p_shp_param->peaking_limit_ctrl_ratio, limit_ctrl_ratio_tmp, sizeof(limit_ctrl_ratio_tmp));
1299 memcpy(p_shp_param->peaking_limit_ctrl_bnd_pos, limit_ctrl_bnd_pos_tmp, sizeof(limit_ctrl_bnd_pos_tmp));
1300 memcpy(p_shp_param->peaking_limit_ctrl_bnd_neg, limit_ctrl_bnd_neg_tmp, sizeof(limit_ctrl_bnd_neg_tmp));
1301
1302 p_shp_param->peaking_edge_ctrl_enable = 1;
1303 p_shp_param->peaking_edge_ctrl_non_dir_thr = 16;
1304 p_shp_param->peaking_edge_ctrl_dir_cmp_ratio = 4;
1305 p_shp_param->peaking_edge_ctrl_non_dir_wgt_offset = 64;
1306 p_shp_param->peaking_edge_ctrl_non_dir_wgt_ratio = 16;
1307 p_shp_param->peaking_edge_ctrl_dir_cnt_thr = 2;
1308 p_shp_param->peaking_edge_ctrl_dir_cnt_avg = 3;
1309 p_shp_param->peaking_edge_ctrl_dir_cnt_offset = 2;
1310 p_shp_param->peaking_edge_ctrl_diag_dir_thr = 16;
1311
1312 memcpy(p_shp_param->peaking_edge_ctrl_diag_adj_gain_tab, diag_adj_gain_tab_tmp, sizeof(diag_adj_gain_tab_tmp));
1313
1314 p_shp_param->peaking_estc_enable = 1;
1315 p_shp_param->peaking_estc_delta_offset_h = 4;
1316 p_shp_param->peaking_estc_alpha_over_h = 8;
1317 p_shp_param->peaking_estc_alpha_under_h = 16;
1318 p_shp_param->peaking_estc_alpha_over_unlimit_h = 64;
1319 p_shp_param->peaking_estc_alpha_under_unlimit_h = 112;
1320 p_shp_param->peaking_estc_delta_offset_v = 4;
1321 p_shp_param->peaking_estc_alpha_over_v = 8;
1322 p_shp_param->peaking_estc_alpha_under_v = 16;
1323 p_shp_param->peaking_estc_alpha_over_unlimit_v = 64;
1324 p_shp_param->peaking_estc_alpha_under_unlimit_v = 112;
1325 p_shp_param->peaking_estc_delta_offset_d0 = 4;
1326 p_shp_param->peaking_estc_alpha_over_d0 = 16;
1327 p_shp_param->peaking_estc_alpha_under_d0 = 16;
1328 p_shp_param->peaking_estc_alpha_over_unlimit_d0 = 96;
1329 p_shp_param->peaking_estc_alpha_under_unlimit_d0 = 96;
1330 p_shp_param->peaking_estc_delta_offset_d1 = 4;
1331 p_shp_param->peaking_estc_alpha_over_d1 = 16;
1332 p_shp_param->peaking_estc_alpha_under_d1 = 16;
1333 p_shp_param->peaking_estc_alpha_over_unlimit_d1 = 96;
1334 p_shp_param->peaking_estc_alpha_under_unlimit_d1 = 96;
1335 p_shp_param->peaking_estc_delta_offset_non = 4;
1336 p_shp_param->peaking_estc_alpha_over_non = 8;
1337 p_shp_param->peaking_estc_alpha_under_non = 8;
1338 p_shp_param->peaking_estc_alpha_over_unlimit_non = 112;
1339 p_shp_param->peaking_estc_alpha_under_unlimit_non = 112;
1340 p_shp_param->peaking_filter_cfg_diag_enh_coef = 6;
1341
1342 p_shp_param->peaking_filt_core_H0[0] = 4;
1343 p_shp_param->peaking_filt_core_H0[1] = 16;
1344 p_shp_param->peaking_filt_core_H0[2] = 24;
1345 p_shp_param->peaking_filt_core_H1[0] = -16;
1346 p_shp_param->peaking_filt_core_H1[1] = 0;
1347 p_shp_param->peaking_filt_core_H1[2] = 32;
1348 p_shp_param->peaking_filt_core_H2[0] = 0;
1349 p_shp_param->peaking_filt_core_H2[1] = -16;
1350 p_shp_param->peaking_filt_core_H2[2] = 32;
1351 p_shp_param->peaking_filt_core_V0[0] = 1;
1352 p_shp_param->peaking_filt_core_V0[1] = 4;
1353 p_shp_param->peaking_filt_core_V0[2] = 6;
1354 p_shp_param->peaking_filt_core_V1[0] = -4;
1355 p_shp_param->peaking_filt_core_V1[1] = 0;
1356 p_shp_param->peaking_filt_core_V1[2] = 8;
1357 p_shp_param->peaking_filt_core_V2[0] = 0;
1358 p_shp_param->peaking_filt_core_V2[1] = -4;
1359 p_shp_param->peaking_filt_core_V2[2] = 8;
1360 p_shp_param->peaking_filt_core_USM[0] = 1;
1361 p_shp_param->peaking_filt_core_USM[1] = 4;
1362 p_shp_param->peaking_filt_core_USM[2] = 6;
1363
1364 p_shp_param->shootctrl_enable = 1;
1365 p_shp_param->shootctrl_filter_radius = 1;
1366 p_shp_param->shootctrl_delta_offset = 16;
1367 p_shp_param->shootctrl_alpha_over = 8;
1368 p_shp_param->shootctrl_alpha_under = 8;
1369 p_shp_param->shootctrl_alpha_over_unlimit = 112;
1370 p_shp_param->shootctrl_alpha_under_unlimit = 112;
1371
1372 p_shp_param->global_gain_enable = 0;
1373 p_shp_param->global_gain_lum_mode = 0;
1374
1375 memcpy(p_shp_param->global_gain_lum_grd, lum_grd_tmp, sizeof(lum_grd_tmp));
1376 memcpy(p_shp_param->global_gain_lum_val, lum_val_tmp, sizeof(lum_val_tmp));
1377 memcpy(p_shp_param->global_gain_adp_grd, adp_grd_tmp, sizeof(adp_grd_tmp));
1378 memcpy(p_shp_param->global_gain_adp_val, adp_val_tmp, sizeof(adp_val_tmp));
1379 memcpy(p_shp_param->global_gain_var_grd, var_grd_tmp, sizeof(var_grd_tmp));
1380 memcpy(p_shp_param->global_gain_var_val, var_val_tmp, sizeof(var_val_tmp));
1381
1382 p_shp_param->color_ctrl_enable = 0;
1383
1384 p_shp_param->color_ctrl_p0_scaling_coef = 1;
1385 p_shp_param->color_ctrl_p0_point_u = 115;
1386 p_shp_param->color_ctrl_p0_point_v = 155;
1387 memcpy(p_shp_param->color_ctrl_p0_roll_tab, roll_tab_pattern0, sizeof(roll_tab_pattern0));
1388 p_shp_param->color_ctrl_p1_scaling_coef = 1;
1389 p_shp_param->color_ctrl_p1_point_u = 90;
1390 p_shp_param->color_ctrl_p1_point_v = 120;
1391 memcpy(p_shp_param->color_ctrl_p1_roll_tab, roll_tab_pattern1, sizeof(roll_tab_pattern1));
1392 p_shp_param->color_ctrl_p2_scaling_coef = 1;
1393 p_shp_param->color_ctrl_p2_point_u = 128;
1394 p_shp_param->color_ctrl_p2_point_v = 128;
1395 memcpy(p_shp_param->color_ctrl_p2_roll_tab, roll_tab_pattern2, sizeof(roll_tab_pattern2));
1396 p_shp_param->color_ctrl_p3_scaling_coef = 1;
1397 p_shp_param->color_ctrl_p3_point_u = 128;
1398 p_shp_param->color_ctrl_p3_point_v = 128;
1399 memcpy(p_shp_param->color_ctrl_p3_roll_tab, roll_tab_pattern2, sizeof(roll_tab_pattern2));
1400
1401 p_shp_param->tex_adj_enable = 0;
1402 p_shp_param->tex_adj_y_mode_select = 3;
1403 p_shp_param->tex_adj_mode_select = 0;
1404
1405 memcpy(p_shp_param->tex_adj_grd, tex_grd_tmp, sizeof(tex_grd_tmp));
1406 memcpy(p_shp_param->tex_adj_val, tex_val_tmp, sizeof(tex_val_tmp));
1407 }
1408
vdpp2_set_default_param(struct vdpp2_params * param)1409 static MPP_RET vdpp2_set_default_param(struct vdpp2_params *param)
1410 {
1411 param->src_fmt = VDPP_FMT_YUV420;
1412 param->src_yuv_swap = VDPP_YUV_SWAP_SP_UV;
1413 param->dst_fmt = VDPP_FMT_YUV444;
1414 param->dst_yuv_swap = VDPP_YUV_SWAP_SP_UV;
1415 param->src_width = 1920;
1416 param->src_height = 1080;
1417 param->dst_width = 1920;
1418 param->dst_height = 1080;
1419 param->yuv_out_diff = 0;
1420 param->working_mode = VDPP_WORK_MODE_VEP;
1421
1422 vdpp2_set_default_dmsr_param(¶m->dmsr_params);
1423 vdpp_set_default_es_param(¶m->es_params);
1424 vdpp_set_default_shp_param(¶m->shp_params);
1425
1426 param->hist_cnt_en = 1;
1427 param->dci_hsd_mode = VDPP_DCI_HSD_DISABLE;
1428 param->dci_vsd_mode = VDPP_DCI_VSD_DISABLE;
1429 param->dci_yrgb_gather_num = 0;
1430 param->dci_yrgb_gather_en = 0;
1431 param->dci_csc_range = VDPP_COLOR_SPACE_LIMIT_RANGE;
1432 update_dci_ctl(param);
1433
1434 vdpp_set_default_zme_param(¶m->zme_params);
1435
1436 return MPP_OK;
1437 }
1438
vdpp2_init(VdppCtx * ictx)1439 MPP_RET vdpp2_init(VdppCtx *ictx)
1440 {
1441 MPP_RET ret;
1442 MppReqV1 mpp_req;
1443 RK_U32 client_data = VDPP_CLIENT_TYPE;
1444 struct vdpp2_api_ctx *ctx = NULL;
1445
1446 if (NULL == *ictx) {
1447 mpp_err_f("found NULL input vdpp2 ctx %p\n", *ictx);
1448 return MPP_ERR_NULL_PTR;
1449 }
1450
1451 ctx = *ictx;
1452
1453 mpp_env_get_u32("vdpp2_debug", &vdpp2_debug, 0);
1454
1455 ctx->fd = open("/dev/mpp_service", O_RDWR | O_CLOEXEC);
1456 if (ctx->fd < 0) {
1457 mpp_err("can NOT find device /dev/vdpp\n");
1458 return MPP_NOK;
1459 }
1460
1461 mpp_req.cmd = MPP_CMD_INIT_CLIENT_TYPE;
1462 mpp_req.flag = 0;
1463 mpp_req.size = sizeof(client_data);
1464 mpp_req.data_ptr = REQ_DATA_PTR(&client_data);
1465
1466 memset(&ctx->params, 0, sizeof(struct vdpp2_params));
1467 /* set default parameters */
1468 vdpp2_set_default_param(&ctx->params);
1469
1470 ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req);
1471 if (ret) {
1472 mpp_err("ioctl set_client failed\n");
1473 return MPP_NOK;
1474 }
1475
1476 return MPP_OK;
1477 }
1478
vdpp2_deinit(VdppCtx ictx)1479 MPP_RET vdpp2_deinit(VdppCtx ictx)
1480 {
1481 struct vdpp2_api_ctx *ctx = NULL;
1482
1483 if (NULL == ictx) {
1484 mpp_err_f("found NULL input vdpp ctx %p\n", ictx);
1485 return MPP_ERR_NULL_PTR;
1486 }
1487
1488 ctx = ictx;
1489
1490 if (ctx->fd >= 0) {
1491 close(ctx->fd);
1492 ctx->fd = -1;
1493 }
1494
1495 return MPP_OK;
1496 }
1497
vdpp2_set_param(struct vdpp2_api_ctx * ctx,union vdpp_api_content * param,enum VDPP_PARAM_TYPE type)1498 static MPP_RET vdpp2_set_param(struct vdpp2_api_ctx *ctx,
1499 union vdpp_api_content *param,
1500 enum VDPP_PARAM_TYPE type)
1501 {
1502 RK_U16 mask;
1503 RK_U16 cfg_set;
1504
1505 switch (type) {
1506 case VDPP_PARAM_TYPE_COM: // deprecated config
1507 ctx->params.hist_cnt_en = 0; // default disable
1508
1509 ctx->params.src_fmt = VDPP_FMT_YUV420; // default 420
1510 ctx->params.src_yuv_swap = param->com.sswap;
1511 ctx->params.dst_fmt = param->com.dfmt;
1512 ctx->params.dst_yuv_swap = param->com.dswap;
1513 ctx->params.src_width = param->com.src_width;
1514 ctx->params.src_height = param->com.src_height;
1515 ctx->params.dst_width = param->com.dst_width;
1516 ctx->params.dst_height = param->com.dst_height;
1517
1518 ctx->params.dmsr_params.dmsr_enable = 1;
1519 ctx->params.es_params.es_bEnabledES = 1;
1520 ctx->params.shp_params.sharp_enable = 1;
1521 /* set default vir stride */
1522 if (!ctx->params.src_width_vir)
1523 ctx->params.src_width_vir = MPP_ALIGN(ctx->params.src_width, 16);
1524 if (!ctx->params.src_height_vir)
1525 ctx->params.src_height_vir = MPP_ALIGN(ctx->params.src_height, 8);
1526 if (!ctx->params.dst_width)
1527 ctx->params.dst_width = ctx->params.src_width;
1528 if (!ctx->params.dst_height)
1529 ctx->params.dst_height = ctx->params.src_height;
1530 if (!ctx->params.dst_width_vir)
1531 ctx->params.dst_width_vir = MPP_ALIGN(ctx->params.dst_width, 16);
1532 if (!ctx->params.dst_height_vir)
1533 ctx->params.dst_height_vir = MPP_ALIGN(ctx->params.dst_height, 2);
1534 /* set default chrome stride */
1535 if (!ctx->params.dst_c_width)
1536 ctx->params.dst_c_width = ctx->params.dst_width;
1537 if (!ctx->params.dst_c_width_vir)
1538 ctx->params.dst_c_width_vir = MPP_ALIGN(ctx->params.dst_c_width, 16);
1539 if (!ctx->params.dst_c_height)
1540 ctx->params.dst_c_height = ctx->params.dst_height;
1541 if (!ctx->params.dst_c_height_vir)
1542 ctx->params.dst_c_height_vir = MPP_ALIGN(ctx->params.dst_c_height, 2);
1543 update_dci_ctl(&ctx->params);
1544 break;
1545 case VDPP_PARAM_TYPE_DMSR:
1546 memcpy(&ctx->params.dmsr_params, ¶m->dmsr, sizeof(struct dmsr_params));
1547 break;
1548 case VDPP_PARAM_TYPE_ZME_COM:
1549 ctx->params.zme_params.zme_bypass_en = param->zme.bypass_enable;
1550 ctx->params.zme_params.zme_dering_enable = param->zme.dering_enable;
1551 ctx->params.zme_params.zme_dering_sen_0 = param->zme.dering_sen_0;
1552 ctx->params.zme_params.zme_dering_sen_1 = param->zme.dering_sen_1;
1553 ctx->params.zme_params.zme_dering_blend_alpha = param->zme.dering_blend_alpha;
1554 ctx->params.zme_params.zme_dering_blend_beta = param->zme.dering_blend_beta;
1555 break;
1556 case VDPP_PARAM_TYPE_ZME_COEFF:
1557 if (param->zme.tap8_coeff != NULL)
1558 ctx->params.zme_params.zme_tap8_coeff = param->zme.tap8_coeff;
1559 if (param->zme.tap6_coeff != NULL)
1560 ctx->params.zme_params.zme_tap6_coeff = param->zme.tap6_coeff;
1561 break;
1562 case VDPP_PARAM_TYPE_COM2:
1563 mask = (param->com2.cfg_set >> 16) & 0x7;
1564 cfg_set = (param->com2.cfg_set >> 0) & mask;
1565
1566 ctx->params.src_yuv_swap = param->com2.sswap;
1567 ctx->params.src_fmt = param->com2.sfmt;
1568 ctx->params.dst_fmt = param->com2.dfmt;
1569 ctx->params.dst_yuv_swap = param->com2.dswap;
1570 ctx->params.src_width = param->com2.src_width;
1571 ctx->params.src_height = param->com2.src_height;
1572 ctx->params.src_width_vir = param->com2.src_width_vir;
1573 ctx->params.src_height_vir = param->com2.src_height_vir;
1574 ctx->params.dst_width = param->com2.dst_width;
1575 ctx->params.dst_height = param->com2.dst_height;
1576 ctx->params.dst_width_vir = param->com2.dst_width_vir;
1577 ctx->params.dst_height_vir = param->com2.dst_height_vir;
1578 ctx->params.yuv_out_diff = param->com2.yuv_out_diff;
1579 ctx->params.dst_c_width = param->com2.dst_c_width;
1580 ctx->params.dst_c_height = param->com2.dst_c_height;
1581 ctx->params.dst_c_width_vir = param->com2.dst_c_width_vir;
1582 ctx->params.dst_c_height_vir = param->com2.dst_c_height_vir;
1583 ctx->params.working_mode = param->com2.hist_mode_en ?
1584 VDPP_WORK_MODE_DCI : VDPP_WORK_MODE_VEP;
1585 if (mask & VDPP_DMSR_EN)
1586 ctx->params.dmsr_params.dmsr_enable = (cfg_set & VDPP_DMSR_EN) ? 1 : 0;
1587 if (mask & VDPP_ES_EN)
1588 ctx->params.es_params.es_bEnabledES = (cfg_set & VDPP_ES_EN) ? 1 : 0;
1589 if (mask & VDPP_SHARP_EN)
1590 ctx->params.shp_params.sharp_enable = (cfg_set & VDPP_SHARP_EN) ? 1 : 0;
1591 update_dci_ctl(&ctx->params);
1592 break;
1593 case VDPP_PARAM_TYPE_ES:
1594 memcpy(&ctx->params.es_params, ¶m->es, sizeof(EsParams));
1595 update_es_tan(&ctx->params.es_params);
1596 break;
1597 case VDPP_PARAM_TYPE_HIST:
1598 ctx->params.hist_cnt_en = param->hist.hist_cnt_en;
1599 ctx->params.dci_hsd_mode = param->hist.dci_hsd_mode;
1600 ctx->params.dci_vsd_mode = param->hist.dci_vsd_mode;
1601 ctx->params.dci_yrgb_gather_num = param->hist.dci_yrgb_gather_num;
1602 ctx->params.dci_yrgb_gather_en = param->hist.dci_yrgb_gather_en;
1603 ctx->params.dci_csc_range = param->hist.dci_csc_range;
1604 update_dci_ctl(&ctx->params);
1605 break;
1606 case VDPP_PARAM_TYPE_SHARP:
1607 memcpy(&ctx->params.shp_params, ¶m->sharp, sizeof(ShpParams));
1608 break;
1609 default:
1610 break;
1611 }
1612
1613 return MPP_OK;
1614 }
1615
check_cap(struct vdpp2_params * params)1616 static RK_S32 check_cap(struct vdpp2_params *params)
1617 {
1618 RK_S32 ret_cap = VDPP_CAP_UNSUPPORTED;
1619 RK_U32 vep_mode_check = 0;
1620 RK_U32 hist_mode_check = 0;
1621
1622 if (NULL == params) {
1623 VDPP2_DBG(VDPP2_DBG_CHECK, "found null pointer params\n");
1624 return VDPP_CAP_UNSUPPORTED;
1625 }
1626
1627 if (params->src_height_vir < params->src_height ||
1628 params->src_width_vir < params->src_width) {
1629 VDPP2_DBG(VDPP2_DBG_CHECK, "invalid src img_w %d img_h %d img_w_vir %d img_h_vir %d\n",
1630 params->src_width, params->src_height,
1631 params->src_width_vir, params->src_height_vir);
1632 return VDPP_CAP_UNSUPPORTED;
1633 }
1634
1635 if ((params->src_fmt != MPP_FMT_YUV420SP) &&
1636 (params->src_fmt != MPP_FMT_YUV420SP_VU)) {
1637 VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support nv12 or nv21\n");
1638 vep_mode_check++;
1639 }
1640
1641 if ((params->src_height_vir > VDPP2_VEP_MAX_HEIGHT) ||
1642 (params->src_width_vir > VDPP2_VEP_MAX_WIDTH) ||
1643 (params->src_height < VDPP2_MODE_MIN_HEIGH) ||
1644 (params->src_width < VDPP2_MODE_MIN_WIDTH) ||
1645 (params->src_height_vir < VDPP2_MODE_MIN_HEIGH) ||
1646 (params->src_width_vir < VDPP2_MODE_MIN_WIDTH)) {
1647 VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported src img_w %d img_h %d img_w_vir %d img_h_vir %d\n",
1648 params->src_width, params->src_height,
1649 params->src_width_vir, params->src_height_vir);
1650 vep_mode_check++;
1651 }
1652
1653 if ((params->dst_height_vir > VDPP2_VEP_MAX_HEIGHT) ||
1654 (params->dst_width_vir > VDPP2_VEP_MAX_WIDTH) ||
1655 (params->dst_height < VDPP2_MODE_MIN_HEIGH) ||
1656 (params->dst_width < VDPP2_MODE_MIN_WIDTH) ||
1657 (params->dst_height_vir < VDPP2_MODE_MIN_HEIGH) ||
1658 (params->dst_width_vir < VDPP2_MODE_MIN_WIDTH) ||
1659 (params->dst_height_vir < params->dst_height) ||
1660 (params->dst_width_vir < params->dst_width)) {
1661 VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported dst img_w %d img_h %d img_w_vir %d img_h_vir %d\n",
1662 params->dst_width, params->dst_height,
1663 params->dst_width_vir, params->dst_height_vir);
1664 vep_mode_check++;
1665 }
1666
1667 if ((params->src_width_vir & 0xf) || (params->dst_width_vir & 0xf)) {
1668 VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_w_i/o_vir 16Byte align\n");
1669 VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported src img_w_vir %d dst img_w_vir %d\n",
1670 params->src_width_vir, params->dst_width_vir);
1671 vep_mode_check++;
1672 }
1673
1674 if (params->src_height_vir & 0x7) {
1675 VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_h_in_vir 8pix align\n");
1676 VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported src img_h_vir %d\n", params->src_height_vir);
1677 vep_mode_check++;
1678 }
1679
1680 if (params->dst_height_vir & 0x1) {
1681 VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_h_out_vir 2pix align\n");
1682 VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported dst img_h_vir %d\n", params->dst_height_vir);
1683 vep_mode_check++;
1684 }
1685
1686 if ((params->src_width & 1) || (params->src_height & 1) ||
1687 (params->dst_width & 1) || (params->dst_height & 1)) {
1688 VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_w/h_vld 2pix align\n");
1689 VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported img_w_i %d img_h_i %d img_w_o %d img_h_o %d\n",
1690 params->src_width, params->src_height, params->dst_width, params->dst_height);
1691 vep_mode_check++;
1692 }
1693
1694 if (params->yuv_out_diff) {
1695 if ((params->dst_c_height_vir > VDPP2_VEP_MAX_HEIGHT) ||
1696 (params->dst_c_width_vir > VDPP2_VEP_MAX_WIDTH) ||
1697 (params->dst_c_height < VDPP2_MODE_MIN_HEIGH) ||
1698 (params->dst_c_width < VDPP2_MODE_MIN_WIDTH) ||
1699 (params->dst_c_height_vir < VDPP2_MODE_MIN_HEIGH) ||
1700 (params->dst_c_width_vir < VDPP2_MODE_MIN_WIDTH) ||
1701 (params->dst_c_height_vir < params->dst_c_height) ||
1702 (params->dst_c_width_vir < params->dst_c_width)) {
1703 VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported dst_c img_w %d img_h %d img_w_vir %d img_h_vir %d\n",
1704 params->dst_c_width, params->dst_c_height,
1705 params->dst_c_width_vir, params->dst_c_height_vir);
1706 vep_mode_check++;
1707 }
1708
1709 if (params->dst_c_width_vir & 0xf) {
1710 VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_w_c_out_vir 16Byte align\n");
1711 VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported dst img_w_c_vir %d\n", params->dst_c_width_vir);
1712 vep_mode_check++;
1713 }
1714
1715 if (params->dst_c_height_vir & 0x1) {
1716 VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_h_c_out_vir 2pix align\n");
1717 VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported dst img_h_vir %d\n", params->dst_c_height_vir);
1718 vep_mode_check++;
1719 }
1720
1721 if ((params->dst_c_width & 1) || (params->dst_c_height & 1)) {
1722 VDPP2_DBG(VDPP2_DBG_CHECK, "vep only support img_c_w/h_vld 2pix align\n");
1723 VDPP2_DBG(VDPP2_DBG_CHECK, "vep unsupported img_w_o %d img_h_o %d\n",
1724 params->dst_c_width, params->dst_c_height);
1725 vep_mode_check++;
1726 }
1727 }
1728
1729 if ((params->src_height_vir > VDPP2_HIST_MAX_HEIGHT) ||
1730 (params->src_width_vir > VDPP2_HIST_MAX_WIDTH) ||
1731 (params->src_height < VDPP2_MODE_MIN_HEIGH) ||
1732 (params->src_width < VDPP2_MODE_MIN_WIDTH)) {
1733 VDPP2_DBG(VDPP2_DBG_CHECK, "dci unsupported src img_w %d img_h %d img_w_vir %d img_h_vir %d\n",
1734 params->src_width, params->src_height,
1735 params->src_width_vir, params->src_height_vir);
1736 hist_mode_check++;
1737 }
1738
1739 /* 10 bit input */
1740 if ((params->src_fmt == MPP_FMT_YUV420SP_10BIT) ||
1741 (params->src_fmt == MPP_FMT_YUV422SP_10BIT) ||
1742 (params->src_fmt == MPP_FMT_YUV444SP_10BIT)) {
1743 if (params->src_width_vir & 0xf) {
1744 VDPP2_DBG(VDPP2_DBG_CHECK, "dci Y-10bit input only support img_w_in_vir 16Byte align\n");
1745 hist_mode_check++;
1746 }
1747 } else {
1748 if (params->src_width_vir & 0x3) {
1749 VDPP2_DBG(VDPP2_DBG_CHECK, "dci only support img_w_in_vir 4Byte align\n");
1750 hist_mode_check++;
1751 }
1752 }
1753
1754 VDPP2_DBG(VDPP2_DBG_INT, "vdpp2 src img resolution: w-%d-%d, h-%d-%d\n",
1755 params->src_width, params->src_width_vir,
1756 params->src_height, params->src_height_vir);
1757 VDPP2_DBG(VDPP2_DBG_INT, "vdpp2 dst img resolution: w-%d-%d, h-%d-%d\n",
1758 params->dst_width, params->dst_width_vir,
1759 params->dst_height, params->dst_height_vir);
1760
1761 if (!vep_mode_check) {
1762 ret_cap |= VDPP_CAP_VEP;
1763 VDPP2_DBG(VDPP2_DBG_INT, "vdpp2 support mode: VDPP_CAP_VEP\n");
1764 }
1765
1766 if (!hist_mode_check) {
1767 VDPP2_DBG(VDPP2_DBG_INT, "vdpp2 support mode: VDPP_CAP_HIST\n");
1768 ret_cap |= VDPP_CAP_HIST;
1769 }
1770
1771 return ret_cap;
1772 }
1773
vdpp2_start(struct vdpp2_api_ctx * ctx)1774 MPP_RET vdpp2_start(struct vdpp2_api_ctx *ctx)
1775 {
1776 MPP_RET ret;
1777 RegOffsetInfo reg_off[2];
1778 MppReqV1 mpp_req[12];
1779 RK_U32 req_cnt = 0;
1780 struct vdpp2_reg *reg = NULL;
1781 struct zme_reg *zme = NULL;
1782 RK_S32 ret_cap = VDPP_CAP_UNSUPPORTED;
1783 RK_S32 work_mode;
1784
1785 if (NULL == ctx) {
1786 mpp_err_f("found NULL input vdpp2 ctx %p\n", ctx);
1787 return MPP_ERR_NULL_PTR;
1788 }
1789
1790 work_mode = ctx->params.working_mode;
1791 ret_cap = check_cap(&ctx->params);
1792 if ((!(ret_cap & VDPP_CAP_VEP) && (VDPP_WORK_MODE_VEP == work_mode)) ||
1793 (!(ret_cap & VDPP_CAP_HIST) && (VDPP_WORK_MODE_DCI == work_mode))) {
1794 mpp_err_f("found incompat work mode %d %s, cap %d\n", work_mode,
1795 working_mode_name[work_mode & 3], ret_cap);
1796 return MPP_NOK;
1797 }
1798
1799 reg = &ctx->reg;
1800 zme = &ctx->zme;
1801
1802 memset(reg_off, 0, sizeof(reg_off));
1803 memset(mpp_req, 0, sizeof(mpp_req));
1804 memset(reg, 0, sizeof(*reg));
1805
1806 vdpp2_params_to_reg(&ctx->params, ctx);
1807
1808 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
1809 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
1810 mpp_req[req_cnt].size = sizeof(zme->yrgb_hor_coe);
1811 mpp_req[req_cnt].offset = VDPP_REG_OFF_YRGB_HOR_COE;
1812 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->yrgb_hor_coe);
1813
1814 req_cnt++;
1815 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
1816 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
1817 mpp_req[req_cnt].size = sizeof(zme->yrgb_ver_coe);
1818 mpp_req[req_cnt].offset = VDPP_REG_OFF_YRGB_VER_COE;
1819 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->yrgb_ver_coe);
1820
1821 req_cnt++;
1822 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
1823 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
1824 mpp_req[req_cnt].size = sizeof(zme->cbcr_hor_coe);
1825 mpp_req[req_cnt].offset = VDPP_REG_OFF_CBCR_HOR_COE;
1826 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->cbcr_hor_coe);
1827
1828 req_cnt++;
1829 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
1830 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
1831 mpp_req[req_cnt].size = sizeof(zme->cbcr_ver_coe);
1832 mpp_req[req_cnt].offset = VDPP_REG_OFF_CBCR_VER_COE;
1833 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->cbcr_ver_coe);
1834
1835 req_cnt++;
1836 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
1837 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
1838 mpp_req[req_cnt].size = sizeof(zme->common);
1839 mpp_req[req_cnt].offset = VDPP_REG_OFF_ZME_COMMON;
1840 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&zme->common);
1841
1842 req_cnt++;
1843 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
1844 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
1845 mpp_req[req_cnt].size = sizeof(ctx->dmsr);
1846 mpp_req[req_cnt].offset = VDPP_REG_OFF_DMSR;
1847 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(&ctx->dmsr);
1848
1849 req_cnt++;
1850 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
1851 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
1852 mpp_req[req_cnt].size = sizeof(reg->dci);
1853 mpp_req[req_cnt].offset = VDPP_REG_OFF_DCI;
1854 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(®->dci);
1855
1856 req_cnt++;
1857 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
1858 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
1859 mpp_req[req_cnt].size = sizeof(reg->es);
1860 mpp_req[req_cnt].offset = VDPP_REG_OFF_ES;
1861 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(®->es);
1862
1863 req_cnt++;
1864 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
1865 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
1866 mpp_req[req_cnt].size = sizeof(reg->sharp);
1867 mpp_req[req_cnt].offset = VDPP_REG_OFF_SHARP;
1868 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(®->sharp);
1869
1870 /* set reg offset */
1871 reg_off[0].reg_idx = 25;
1872 reg_off[0].offset = ctx->params.src.cbcr_offset;
1873 reg_off[1].reg_idx = 27;
1874
1875 if (!ctx->params.yuv_out_diff)
1876 reg_off[1].offset = ctx->params.dst.cbcr_offset;
1877 else
1878 reg_off[1].offset = ctx->params.dst_c.cbcr_offset;
1879 req_cnt++;
1880 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_ADDR_OFFSET;
1881 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG | MPP_FLAGS_REG_OFFSET_ALONE;
1882 mpp_req[req_cnt].size = sizeof(reg_off);
1883 mpp_req[req_cnt].offset = 0;
1884 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(reg_off);
1885
1886 req_cnt++;
1887 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_WRITE;
1888 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG;
1889 mpp_req[req_cnt].size = sizeof(reg->common);
1890 mpp_req[req_cnt].offset = 0;
1891 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(®->common);
1892
1893 req_cnt++;
1894 mpp_req[req_cnt].cmd = MPP_CMD_SET_REG_READ;
1895 mpp_req[req_cnt].flag = MPP_FLAGS_MULTI_MSG | MPP_FLAGS_LAST_MSG;
1896 mpp_req[req_cnt].size = sizeof(reg->common);
1897 mpp_req[req_cnt].offset = 0;
1898 mpp_req[req_cnt].data_ptr = REQ_DATA_PTR(®->common);
1899
1900 ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req[0]);
1901
1902 if (ret) {
1903 mpp_err_f("ioctl SET_REG failed ret %d errno %d %s\n",
1904 ret, errno, strerror(errno));
1905 ret = errno;
1906 }
1907
1908 return ret;
1909 }
1910
vdpp2_wait(struct vdpp2_api_ctx * ctx)1911 static MPP_RET vdpp2_wait(struct vdpp2_api_ctx *ctx)
1912 {
1913 MPP_RET ret;
1914 MppReqV1 mpp_req;
1915
1916 if (NULL == ctx) {
1917 mpp_err_f("found NULL input vdpp ctx %p\n", ctx);
1918 return MPP_ERR_NULL_PTR;
1919 }
1920
1921 memset(&mpp_req, 0, sizeof(mpp_req));
1922 mpp_req.cmd = MPP_CMD_POLL_HW_FINISH;
1923 mpp_req.flag |= MPP_FLAGS_LAST_MSG;
1924
1925 ret = (RK_S32)ioctl(ctx->fd, MPP_IOC_CFG_V1, &mpp_req);
1926 if (ret) {
1927 mpp_err_f("ioctl POLL_HW_FINISH failed ret %d errno %d %s\n",
1928 ret, errno, strerror(errno));
1929 }
1930
1931 return ret;
1932 }
1933
vdpp2_done(struct vdpp2_api_ctx * ctx)1934 static MPP_RET vdpp2_done(struct vdpp2_api_ctx *ctx)
1935 {
1936 struct vdpp2_reg *reg = &ctx->reg;
1937
1938 if (NULL == ctx) {
1939 mpp_err_f("found NULL input vdpp ctx %p\n", ctx);
1940 return MPP_ERR_NULL_PTR;
1941 }
1942
1943 reg = &ctx->reg;
1944
1945 VDPP2_DBG(VDPP2_DBG_INT, "ro_frm_done_sts=%d\n", reg->common.reg10.ro_frm_done_sts);
1946 VDPP2_DBG(VDPP2_DBG_INT, "ro_osd_max_sts=%d\n", reg->common.reg10.ro_osd_max_sts);
1947 VDPP2_DBG(VDPP2_DBG_INT, "ro_bus_error_sts=%d\n", reg->common.reg10.ro_bus_error_sts);
1948 VDPP2_DBG(VDPP2_DBG_INT, "ro_timeout_sts=%d\n", reg->common.reg10.ro_timeout_sts);
1949 VDPP2_DBG(VDPP2_DBG_INT, "ro_config_error_sts=%d\n", reg->common.reg10.ro_timeout_sts);
1950
1951 if (reg->common.reg8.sw_vdpp_frm_done_en &&
1952 !reg->common.reg10.ro_frm_done_sts) {
1953 mpp_err_f("run vdpp failed\n");
1954 return MPP_NOK;
1955 }
1956
1957 VDPP2_DBG(VDPP2_DBG_INT, "run vdpp success\n");
1958
1959 return MPP_OK;
1960 }
1961
set_addr(struct vdpp_addr * addr,VdppImg * img)1962 static inline MPP_RET set_addr(struct vdpp_addr *addr, VdppImg *img)
1963 {
1964 addr->y = img->mem_addr;
1965 addr->cbcr = img->uv_addr;
1966 addr->cbcr_offset = img->uv_off;
1967
1968 return MPP_OK;
1969 }
1970
vdpp2_control(VdppCtx ictx,VdppCmd cmd,void * iparam)1971 MPP_RET vdpp2_control(VdppCtx ictx, VdppCmd cmd, void *iparam)
1972 {
1973 struct vdpp2_api_ctx *ctx = ictx;
1974 MPP_RET ret = MPP_OK;
1975
1976 if ((NULL == iparam && VDPP_CMD_RUN_SYNC != cmd) ||
1977 (NULL == ictx)) {
1978 mpp_err_f("found NULL iparam %p cmd %d ctx %p\n", iparam, cmd, ictx);
1979 return MPP_ERR_NULL_PTR;
1980 }
1981
1982 switch (cmd) {
1983 case VDPP_CMD_SET_COM_CFG:
1984 case VDPP_CMD_SET_DMSR_CFG:
1985 case VDPP_CMD_SET_ZME_COM_CFG:
1986 case VDPP_CMD_SET_ZME_COEFF_CFG:
1987 case VDPP_CMD_SET_COM2_CFG:
1988 case VDPP_CMD_SET_ES:
1989 case VDPP_CMD_SET_DCI_HIST:
1990 case VDPP_CMD_SET_SHARP: {
1991 struct vdpp_api_params *param = (struct vdpp_api_params *)iparam;
1992
1993 ret = vdpp2_set_param(ctx, ¶m->param, param->ptype);
1994 if (ret) {
1995 mpp_err_f("set vdpp parameter failed, type %d\n", param->ptype);
1996 }
1997 break;
1998 }
1999 case VDPP_CMD_SET_SRC:
2000 set_addr(&ctx->params.src, (VdppImg *)iparam);
2001 break;
2002 case VDPP_CMD_SET_DST:
2003 set_addr(&ctx->params.dst, (VdppImg *)iparam);
2004 break;
2005 case VDPP_CMD_SET_DST_C:
2006 set_addr(&ctx->params.dst_c, (VdppImg *)iparam);
2007 break;
2008 case VDPP_CMD_SET_HIST_FD:
2009 ctx->params.hist = *(RK_S32 *)iparam;
2010 break;
2011 case VDPP_CMD_RUN_SYNC:
2012 ret = vdpp2_start(ctx);
2013 if (ret) {
2014 mpp_err_f("run vdpp failed\n");
2015 return MPP_NOK;
2016 }
2017
2018 vdpp2_wait(ctx);
2019 vdpp2_done(ctx);
2020 break;
2021 default:
2022 ;
2023 }
2024
2025 return ret;
2026 }
2027
vdpp2_check_cap(VdppCtx ictx)2028 RK_S32 vdpp2_check_cap(VdppCtx ictx)
2029 {
2030 struct vdpp2_api_ctx *ctx = ictx;
2031
2032 if (NULL == ictx) {
2033 mpp_err_f("found NULL ctx %p\n", ictx);
2034 return VDPP_CAP_UNSUPPORTED;
2035 }
2036
2037 return check_cap(&ctx->params);
2038 }
2039