1*437bfbebSnyanmisaka /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2*437bfbebSnyanmisaka /* 3*437bfbebSnyanmisaka * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4*437bfbebSnyanmisaka */ 5*437bfbebSnyanmisaka 6*437bfbebSnyanmisaka #ifndef __VDPP_H__ 7*437bfbebSnyanmisaka #define __VDPP_H__ 8*437bfbebSnyanmisaka 9*437bfbebSnyanmisaka #include "vdpp_reg.h" 10*437bfbebSnyanmisaka #include "vdpp_common.h" 11*437bfbebSnyanmisaka 12*437bfbebSnyanmisaka /* vdpp log marco */ 13*437bfbebSnyanmisaka #define VDPP_DBG_TRACE (0x00000001) 14*437bfbebSnyanmisaka #define VDPP_DBG_INT (0x00000002) 15*437bfbebSnyanmisaka #define VDPP_DBG_CHECK (0x00000004) 16*437bfbebSnyanmisaka 17*437bfbebSnyanmisaka extern RK_U32 vdpp_debug; 18*437bfbebSnyanmisaka 19*437bfbebSnyanmisaka #define VDPP_DBG(level, fmt, ...)\ 20*437bfbebSnyanmisaka do {\ 21*437bfbebSnyanmisaka if (level & vdpp_debug)\ 22*437bfbebSnyanmisaka { mpp_log(fmt, ## __VA_ARGS__); }\ 23*437bfbebSnyanmisaka } while (0) 24*437bfbebSnyanmisaka 25*437bfbebSnyanmisaka struct vdpp_params { 26*437bfbebSnyanmisaka RK_U32 src_yuv_swap; 27*437bfbebSnyanmisaka RK_U32 dst_fmt; 28*437bfbebSnyanmisaka RK_U32 dst_yuv_swap; 29*437bfbebSnyanmisaka RK_U32 src_width; 30*437bfbebSnyanmisaka RK_U32 src_height; 31*437bfbebSnyanmisaka RK_U32 dst_width; 32*437bfbebSnyanmisaka RK_U32 dst_height; 33*437bfbebSnyanmisaka 34*437bfbebSnyanmisaka struct vdpp_addr src; // src frame 35*437bfbebSnyanmisaka struct vdpp_addr dst; // dst frame 36*437bfbebSnyanmisaka 37*437bfbebSnyanmisaka struct dmsr_params dmsr_params; 38*437bfbebSnyanmisaka struct zme_params zme_params; 39*437bfbebSnyanmisaka }; 40*437bfbebSnyanmisaka 41*437bfbebSnyanmisaka struct vdpp_api_ctx { 42*437bfbebSnyanmisaka RK_S32 fd; 43*437bfbebSnyanmisaka struct vdpp_params params; 44*437bfbebSnyanmisaka struct vdpp_reg reg; 45*437bfbebSnyanmisaka struct dmsr_reg dmsr; 46*437bfbebSnyanmisaka struct zme_reg zme; 47*437bfbebSnyanmisaka }; 48*437bfbebSnyanmisaka 49*437bfbebSnyanmisaka #ifdef __cplusplus 50*437bfbebSnyanmisaka extern "C" { 51*437bfbebSnyanmisaka #endif 52*437bfbebSnyanmisaka 53*437bfbebSnyanmisaka MPP_RET vdpp_init(VdppCtx *ictx); 54*437bfbebSnyanmisaka MPP_RET vdpp_deinit(VdppCtx ictx); 55*437bfbebSnyanmisaka MPP_RET vdpp_control(VdppCtx ictx, VdppCmd cmd, void *iparam); 56*437bfbebSnyanmisaka RK_S32 vdpp_check_cap(VdppCtx ictx); 57*437bfbebSnyanmisaka 58*437bfbebSnyanmisaka #ifdef __cplusplus 59*437bfbebSnyanmisaka } 60*437bfbebSnyanmisaka #endif 61*437bfbebSnyanmisaka 62*437bfbebSnyanmisaka #endif 63