1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __VDPP_API_H__ 7 #define __VDPP_API_H__ 8 9 #include <stdbool.h> 10 11 #include "mpp_debug.h" 12 #include "mpp_frame.h" 13 14 #define CEIL(a) (int)( (double)(a) > (int)(a) ? (int)((a)+1) : (int)(a) ) 15 #define FLOOR(a) (int)( (double)(a) < (int)(a) ? (int)((a)-1) : (int)(a) ) 16 #define ROUND(a) (int)( (a) > 0 ? ((double) (a) + 0.5) : ((double) (a) - 0.5) ) 17 18 #define RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_BITS (8) 19 #define RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_NUMS (1 << (RKVOP_PQ_PREPROCESS_GLOBAL_HIST_BIN_BITS)) 20 #define RKVOP_PQ_PREPROCESS_HIST_BITS_VERI (4) 21 #define RKVOP_PQ_PREPROCESS_HIST_BITS_HORI (4) 22 #define RKVOP_PQ_PREPROCESS_HIST_SIZE_VERI (1 << RKVOP_PQ_PREPROCESS_HIST_BITS_VERI) /* 16 */ 23 #define RKVOP_PQ_PREPROCESS_HIST_SIZE_HORI (1 << RKVOP_PQ_PREPROCESS_HIST_BITS_HORI) /* 16 */ 24 #define RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_BITS (4) 25 #define RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_NUMS (1 << (RKVOP_PQ_PREPROCESS_LOCAL_HIST_BIN_BITS)) 26 27 #define VDPP_COLOR_SPACE_LIMIT_RANGE (0) 28 #define VDPP_COLOR_SPACE_FULL_RANGE (1) 29 30 #define VDPP_CAP_UNSUPPORTED (0) 31 #define VDPP_CAP_VEP (1 << 0) 32 #define VDPP_CAP_HIST (1 << 1) 33 34 #define VDPP_WORK_MODE_VEP (2) 35 #define VDPP_WORK_MODE_DCI (3) /* hist mode */ 36 37 #define VDPP_DMSR_EN (4) 38 #define VDPP_ES_EN (2) 39 #define VDPP_SHARP_EN (1) 40 41 /* DCI horizontal scale down mode select */ 42 #define VDPP_DCI_HSD_DISABLE (0) 43 #define VDPP_DCI_HSD_MODE_1 (1) 44 /* DCI vertical scale down mode select */ 45 #define VDPP_DCI_VSD_DISABLE (0) 46 #define VDPP_DCI_VSD_MODE_1 (1) 47 #define VDPP_DCI_VSD_MODE_2 (2) 48 49 enum VDPP_FMT { 50 VDPP_FMT_YUV444 = 0, 51 VDPP_FMT_YUV420 = 3, 52 }; 53 54 enum VDPP_YUV_SWAP { 55 VDPP_YUV_SWAP_SP_UV, 56 VDPP_YUV_SWAP_SP_VU, 57 }; 58 59 enum VDPP_PARAM_TYPE { 60 VDPP_PARAM_TYPE_COM, 61 VDPP_PARAM_TYPE_DMSR, 62 VDPP_PARAM_TYPE_ZME_COM, 63 VDPP_PARAM_TYPE_ZME_COEFF, 64 VDPP_PARAM_TYPE_COM2 = 0x10, 65 VDPP_PARAM_TYPE_ES, 66 VDPP_PARAM_TYPE_HIST, 67 VDPP_PARAM_TYPE_SHARP, 68 }; 69 70 typedef enum VdppCmd_e { 71 VDPP_CMD_INIT, /* reset msg to all zero */ 72 VDPP_CMD_SET_SRC, /* config source image info */ 73 VDPP_CMD_SET_DST, /* config destination image info */ 74 VDPP_CMD_SET_COM_CFG, 75 /* DMSR command */ 76 VDPP_CMD_SET_DMSR_CFG = 0x0100, /* config DMSR configure */ 77 /* ZME command */ 78 VDPP_CMD_SET_ZME_COM_CFG = 0x0200, /* config ZME COM configure */ 79 VDPP_CMD_SET_ZME_COEFF_CFG, /* config ZME COEFF configure */ 80 /* hardware trigger command */ 81 VDPP_CMD_RUN_SYNC = 0x1000, /* start sync mode process */ 82 VDPP_CMD_SET_COM2_CFG = 0x2000, /* config common params for RK3576 */ 83 VDPP_CMD_SET_DST_C, /* config destination chroma info */ 84 VDPP_CMD_SET_HIST_FD, /* config dci hist fd */ 85 VDPP_CMD_SET_ES, /* config ES configure */ 86 VDPP_CMD_SET_DCI_HIST, /* config dci hist configure */ 87 VDPP_CMD_SET_SHARP, /* config sharp configure */ 88 } VdppCmd; 89 90 typedef void* VdppCtx; 91 typedef struct vdpp_com_ctx_t vdpp_com_ctx; 92 93 typedef struct VdppImg_t { 94 RK_U32 mem_addr; /* base address fd */ 95 RK_U32 uv_addr; /* chroma address fd + (offset << 10) */ 96 RK_U32 uv_off; 97 } VdppImg; 98 99 typedef struct vdpp_com_ops_t { 100 MPP_RET (*init)(VdppCtx *ctx); 101 MPP_RET (*deinit)(VdppCtx ctx); 102 MPP_RET (*control)(VdppCtx ctx, VdppCmd cmd, void *param); 103 void (*release)(vdpp_com_ctx *ctx); 104 RK_S32 (*check_cap)(VdppCtx ctx); 105 MPP_RET (*reserve[3])(VdppCtx *ctx); 106 } vdpp_com_ops; 107 108 typedef struct vdpp_com_ctx_t { 109 vdpp_com_ops *ops; 110 VdppCtx priv; 111 RK_S32 ver; 112 } vdpp_com_ctx; 113 114 union vdpp_api_content { 115 struct { 116 enum VDPP_YUV_SWAP sswap; 117 enum VDPP_FMT dfmt; 118 enum VDPP_YUV_SWAP dswap; 119 RK_S32 src_width; 120 RK_S32 src_height; 121 RK_S32 dst_width; 122 RK_S32 dst_height; 123 } com; 124 125 struct { 126 bool enable; 127 RK_U32 str_pri_y; 128 RK_U32 str_sec_y; 129 RK_U32 dumping_y; 130 RK_U32 wgt_pri_gain_even_1; 131 RK_U32 wgt_pri_gain_even_2; 132 RK_U32 wgt_pri_gain_odd_1; 133 RK_U32 wgt_pri_gain_odd_2; 134 RK_U32 wgt_sec_gain; 135 RK_U32 blk_flat_th; 136 RK_U32 contrast_to_conf_map_x0; 137 RK_U32 contrast_to_conf_map_x1; 138 RK_U32 contrast_to_conf_map_y0; 139 RK_U32 contrast_to_conf_map_y1; 140 RK_U32 diff_core_th0; 141 RK_U32 diff_core_th1; 142 RK_U32 diff_core_wgt0; 143 RK_U32 diff_core_wgt1; 144 RK_U32 diff_core_wgt2; 145 RK_U32 edge_th_low_arr[7]; 146 RK_U32 edge_th_high_arr[7]; 147 } dmsr; 148 149 struct { 150 bool bypass_enable; 151 bool dering_enable; 152 RK_U32 dering_sen_0; 153 RK_U32 dering_sen_1; 154 RK_U32 dering_blend_alpha; 155 RK_U32 dering_blend_beta; 156 RK_S16 (*tap8_coeff)[17][8]; 157 RK_S16 (*tap6_coeff)[17][8]; 158 } zme; 159 160 struct { 161 MppFrameFormat sfmt; 162 enum VDPP_YUV_SWAP sswap; 163 enum VDPP_FMT dfmt; 164 enum VDPP_YUV_SWAP dswap; 165 RK_U32 src_width; 166 RK_U32 src_height; 167 RK_U32 src_width_vir; 168 RK_U32 src_height_vir; 169 RK_U32 dst_width; 170 RK_U32 dst_height; 171 RK_U32 dst_width_vir; 172 RK_U32 dst_height_vir; 173 RK_U32 yuv_out_diff; 174 RK_U32 dst_c_width; 175 RK_U32 dst_c_height; 176 RK_U32 dst_c_width_vir; 177 RK_U32 dst_c_height_vir; 178 RK_U32 hist_mode_en; /* 0 - vdpp, 1 - hist */ 179 /* high 16 bit: mask; low 3 bit: dmsr|es|sharp */ 180 RK_U32 cfg_set; 181 } com2; 182 183 struct { 184 RK_U32 es_bEnabledES; 185 RK_U32 es_iAngleDelta; 186 RK_U32 es_iAngleDeltaExtra; 187 RK_U32 es_iGradNoDirTh; 188 RK_U32 es_iGradFlatTh; 189 RK_U32 es_iWgtGain; 190 RK_U32 es_iWgtDecay; 191 RK_U32 es_iLowConfTh; 192 RK_U32 es_iLowConfRatio; 193 RK_U32 es_iConfCntTh; 194 RK_U32 es_iWgtLocalTh; 195 RK_U32 es_iK1; 196 RK_U32 es_iK2; 197 RK_U32 es_iDeltaLimit; 198 RK_U32 es_iDiff2conf_lut_x[9]; 199 RK_U32 es_iDiff2conf_lut_y[9]; 200 RK_U32 es_bEndpointCheckEnable; 201 /* generated by es_iAngleDelta and es_iAngleDeltaExtra */ 202 RK_U32 es_tan_hi_th; 203 RK_U32 es_tan_lo_th; 204 } es; 205 206 struct { 207 RK_U32 hist_cnt_en; 208 RK_U32 dci_hsd_mode; 209 RK_U32 dci_vsd_mode; 210 RK_U32 dci_yrgb_gather_num; 211 RK_U32 dci_yrgb_gather_en; 212 RK_U32 dci_csc_range; 213 } hist; 214 215 struct { 216 RK_S32 sharp_enable; 217 RK_S32 sharp_coloradj_bypass_en; 218 219 RK_S32 lti_h_enable; 220 RK_S32 lti_h_radius; 221 RK_S32 lti_h_slope; 222 RK_S32 lti_h_thresold; 223 RK_S32 lti_h_gain; 224 RK_S32 lti_h_noise_thr_pos; 225 RK_S32 lti_h_noise_thr_neg; 226 227 RK_S32 lti_v_enable; 228 RK_S32 lti_v_radius; 229 RK_S32 lti_v_slope; 230 RK_S32 lti_v_thresold; 231 RK_S32 lti_v_gain; 232 RK_S32 lti_v_noise_thr_pos; 233 RK_S32 lti_v_noise_thr_neg; 234 235 RK_S32 cti_h_enable; 236 RK_S32 cti_h_radius; 237 RK_S32 cti_h_slope; 238 RK_S32 cti_h_thresold; 239 RK_S32 cti_h_gain; 240 RK_S32 cti_h_noise_thr_pos; 241 RK_S32 cti_h_noise_thr_neg; 242 243 RK_S32 peaking_enable; 244 RK_S32 peaking_gain; 245 246 RK_S32 peaking_coring_enable; 247 RK_S32 peaking_coring_zero[8]; 248 RK_S32 peaking_coring_thr[8]; 249 RK_S32 peaking_coring_ratio[8]; 250 251 RK_S32 peaking_gain_enable; 252 RK_S32 peaking_gain_pos[8]; 253 RK_S32 peaking_gain_neg[8]; 254 255 RK_S32 peaking_limit_ctrl_enable; 256 RK_S32 peaking_limit_ctrl_pos0[8]; 257 RK_S32 peaking_limit_ctrl_pos1[8]; 258 RK_S32 peaking_limit_ctrl_neg0[8]; 259 RK_S32 peaking_limit_ctrl_neg1[8]; 260 RK_S32 peaking_limit_ctrl_ratio[8]; 261 RK_S32 peaking_limit_ctrl_bnd_pos[8]; 262 RK_S32 peaking_limit_ctrl_bnd_neg[8]; 263 264 RK_S32 peaking_edge_ctrl_enable; 265 RK_S32 peaking_edge_ctrl_non_dir_thr; 266 RK_S32 peaking_edge_ctrl_dir_cmp_ratio; 267 RK_S32 peaking_edge_ctrl_non_dir_wgt_offset; 268 RK_S32 peaking_edge_ctrl_non_dir_wgt_ratio; 269 RK_S32 peaking_edge_ctrl_dir_cnt_thr; 270 RK_S32 peaking_edge_ctrl_dir_cnt_avg; 271 RK_S32 peaking_edge_ctrl_dir_cnt_offset; 272 RK_S32 peaking_edge_ctrl_diag_dir_thr; 273 RK_S32 peaking_edge_ctrl_diag_adj_gain_tab[8]; 274 275 RK_S32 peaking_estc_enable; 276 RK_S32 peaking_estc_delta_offset_h; 277 RK_S32 peaking_estc_alpha_over_h; 278 RK_S32 peaking_estc_alpha_under_h; 279 RK_S32 peaking_estc_alpha_over_unlimit_h; 280 RK_S32 peaking_estc_alpha_under_unlimit_h; 281 RK_S32 peaking_estc_delta_offset_v; 282 RK_S32 peaking_estc_alpha_over_v; 283 RK_S32 peaking_estc_alpha_under_v; 284 RK_S32 peaking_estc_alpha_over_unlimit_v; 285 RK_S32 peaking_estc_alpha_under_unlimit_v; 286 RK_S32 peaking_estc_delta_offset_d0; 287 RK_S32 peaking_estc_alpha_over_d0; 288 RK_S32 peaking_estc_alpha_under_d0; 289 RK_S32 peaking_estc_alpha_over_unlimit_d0; 290 RK_S32 peaking_estc_alpha_under_unlimit_d0; 291 RK_S32 peaking_estc_delta_offset_d1; 292 RK_S32 peaking_estc_alpha_over_d1; 293 RK_S32 peaking_estc_alpha_under_d1; 294 RK_S32 peaking_estc_alpha_over_unlimit_d1; 295 RK_S32 peaking_estc_alpha_under_unlimit_d1; 296 RK_S32 peaking_estc_delta_offset_non; 297 RK_S32 peaking_estc_alpha_over_non; 298 RK_S32 peaking_estc_alpha_under_non; 299 RK_S32 peaking_estc_alpha_over_unlimit_non; 300 RK_S32 peaking_estc_alpha_under_unlimit_non; 301 RK_S32 peaking_filter_cfg_diag_enh_coef; 302 303 RK_S32 peaking_filt_core_H0[6]; 304 RK_S32 peaking_filt_core_H1[6]; 305 RK_S32 peaking_filt_core_H2[6]; 306 RK_S32 peaking_filt_core_H3[6]; 307 RK_S32 peaking_filt_core_V0[3]; 308 RK_S32 peaking_filt_core_V1[3]; 309 RK_S32 peaking_filt_core_V2[3]; 310 RK_S32 peaking_filt_core_USM[3]; 311 312 RK_S32 shootctrl_enable; 313 RK_S32 shootctrl_filter_radius; 314 RK_S32 shootctrl_delta_offset; 315 RK_S32 shootctrl_alpha_over; 316 RK_S32 shootctrl_alpha_under; 317 RK_S32 shootctrl_alpha_over_unlimit; 318 RK_S32 shootctrl_alpha_under_unlimit; 319 320 RK_S32 global_gain_enable; 321 RK_S32 global_gain_lum_mode; 322 RK_S32 global_gain_lum_grd[6]; 323 RK_S32 global_gain_lum_val[6]; 324 RK_S32 global_gain_adp_grd[6]; 325 RK_S32 global_gain_adp_val[6]; 326 RK_S32 global_gain_var_grd[6]; 327 RK_S32 global_gain_var_val[6]; 328 329 RK_S32 color_ctrl_enable; 330 331 RK_S32 color_ctrl_p0_scaling_coef; 332 RK_S32 color_ctrl_p0_point_u; 333 RK_S32 color_ctrl_p0_point_v; 334 RK_S32 color_ctrl_p0_roll_tab[16]; 335 336 RK_S32 color_ctrl_p1_scaling_coef; 337 RK_S32 color_ctrl_p1_point_u; 338 RK_S32 color_ctrl_p1_point_v; 339 RK_S32 color_ctrl_p1_roll_tab[16]; 340 341 RK_S32 color_ctrl_p2_scaling_coef; 342 RK_S32 color_ctrl_p2_point_u; 343 RK_S32 color_ctrl_p2_point_v; 344 RK_S32 color_ctrl_p2_roll_tab[16]; 345 346 RK_S32 color_ctrl_p3_scaling_coef; 347 RK_S32 color_ctrl_p3_point_u; 348 RK_S32 color_ctrl_p3_point_v; 349 RK_S32 color_ctrl_p3_roll_tab[16]; 350 351 RK_S32 tex_adj_enable; 352 RK_S32 tex_adj_y_mode_select; 353 RK_S32 tex_adj_mode_select; 354 RK_S32 tex_adj_grd[6]; 355 RK_S32 tex_adj_val[6]; 356 } sharp; 357 }; 358 359 struct vdpp_api_params { 360 enum VDPP_PARAM_TYPE ptype; 361 union vdpp_api_content param; 362 }; 363 364 #ifdef __cplusplus 365 extern "C" { 366 #endif 367 368 vdpp_com_ctx* rockchip_vdpp_api_alloc_ctx(void); 369 void rockchip_vdpp_api_release_ctx(vdpp_com_ctx *com_ctx); 370 MPP_RET dci_hist_info_parser(RK_U8* p_pack_hist_addr, RK_U32* p_hist_local, RK_U32* p_hist_global); 371 372 #ifdef __cplusplus 373 } 374 #endif 375 376 #endif 377