xref: /rockchip-linux_mpp/mpp/vproc/inc/hwpq_vdpp_proc_api.h (revision 437bfbeb9567cca9cd9080e3f6954aa9d6a94f18)
1*437bfbebSnyanmisaka /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2*437bfbebSnyanmisaka /*
3*437bfbebSnyanmisaka  * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4*437bfbebSnyanmisaka  */
5*437bfbebSnyanmisaka 
6*437bfbebSnyanmisaka #ifndef __HWPQ_VDPP_PROC_API_H__
7*437bfbebSnyanmisaka #define __HWPQ_VDPP_PROC_API_H__
8*437bfbebSnyanmisaka 
9*437bfbebSnyanmisaka typedef void* rk_vdpp_context;
10*437bfbebSnyanmisaka 
11*437bfbebSnyanmisaka /* hwpq vdpp color format definition */
12*437bfbebSnyanmisaka #define VDPP_FRAME_FMT_COLOR_MASK    (0x000f0000)
13*437bfbebSnyanmisaka #define VDPP_FRAME_FMT_YUV           (0x00000000)
14*437bfbebSnyanmisaka #define VDPP_FRAME_FMT_RGB           (0x00010000)
15*437bfbebSnyanmisaka 
16*437bfbebSnyanmisaka typedef enum {
17*437bfbebSnyanmisaka     // YUV
18*437bfbebSnyanmisaka     VDPP_FMT_YUV_MIN = 0,   /* the min YUV format value, please DO NOT use this item! */
19*437bfbebSnyanmisaka     VDPP_FMT_NV24 = 0,      /* YUV444SP, 2 plane YCbCr, 24bpp/8 bpc, non-subsampled Cr:Cb plane */
20*437bfbebSnyanmisaka     VDPP_FMT_NV16,          /* YUV422SP, 2 plane YCbCr, 16bpp/8 bpc, 2x1 subsampled Cr:Cb plane */
21*437bfbebSnyanmisaka     VDPP_FMT_NV12,          /* YUV420SP, 2 plane YCbCr, 12bpp/8 bpc, 2x2 subsampled Cr:Cb plane */
22*437bfbebSnyanmisaka     VDPP_FMT_NV15,          /* YUV420SP, 2 plane YCbCr, 15bpp/10bpc, 10bit packed data */
23*437bfbebSnyanmisaka     VDPP_FMT_NV20,          /* YUV422SP, 2 plane YCbCr, 20bpp/10bpc, 10bit packed data, output supported only */ /* reserved */
24*437bfbebSnyanmisaka     VDPP_FMT_NV30,          /* YUV444SP, 2 plane YCbCr, 30bpp/10bpc, 10bit packed data, output supported only */
25*437bfbebSnyanmisaka     VDPP_FMT_P010,          /* YUV420SP, 2 plane YCbCr, 24bpp/16bpc, 10bit unpacked data with MSB aligned, output supported only */
26*437bfbebSnyanmisaka     VDPP_FMT_P210,          /* YUV422SP, 2 plane YCbCr, 32bpp/16bpc, 10bit unpacked data with MSB aligned, output supported only */ /* reserved */
27*437bfbebSnyanmisaka     VDPP_FMT_Q410,          /* YUV444P , 3 plane YCbCr, 48bpp/16bpc, 10bit unpacked data with MSB aligned, output supported only */
28*437bfbebSnyanmisaka     VDPP_FMT_Y_ONLY_8BIT,   /* Only 8bit-Y Plane, For VDPP y-uv diff mode */
29*437bfbebSnyanmisaka     VDPP_FMT_UV_ONLY_8BIT,  /* Only 8bit-UV Plane, For VDPP y-uv diff mode */
30*437bfbebSnyanmisaka     VDPP_FMT_NV24_VU,
31*437bfbebSnyanmisaka     VDPP_FMT_NV16_VU,
32*437bfbebSnyanmisaka     VDPP_FMT_NV12_VU,
33*437bfbebSnyanmisaka     VDPP_FMT_YUV_MAX,       /* the max YUV format value, please DO NOT use this item! */
34*437bfbebSnyanmisaka 
35*437bfbebSnyanmisaka     // RGB
36*437bfbebSnyanmisaka     VDPP_FMT_RGB_MIN = 1000,/* the min RGB format value, please DO NOT use this item! */
37*437bfbebSnyanmisaka     VDPP_FMT_RGBA = 1000,   /* RGBA8888, 32bpp */
38*437bfbebSnyanmisaka     VDPP_FMT_RG24,          /* RGB888, 24bpp */
39*437bfbebSnyanmisaka     VDPP_FMT_BG24,          /* BGR888, 24bpp */
40*437bfbebSnyanmisaka     VDPP_FMT_AB30,          /* ABGR2101010, reserved */
41*437bfbebSnyanmisaka     VDPP_FMT_RGB_MAX,       /* the max RGB format value, please DO NOT use this item! */
42*437bfbebSnyanmisaka } vdpp_frame_format;
43*437bfbebSnyanmisaka 
44*437bfbebSnyanmisaka typedef enum {
45*437bfbebSnyanmisaka     VDPP_RUN_MODE_UNSUPPORTED = -1,
46*437bfbebSnyanmisaka     VDPP_RUN_MODE_VEP         = 0,
47*437bfbebSnyanmisaka     VDPP_RUN_MODE_HIST        = 1,
48*437bfbebSnyanmisaka } VdppRunMode;
49*437bfbebSnyanmisaka 
50*437bfbebSnyanmisaka #define VDPP_HIST_LENGTH        (10240)
51*437bfbebSnyanmisaka 
52*437bfbebSnyanmisaka typedef struct {
53*437bfbebSnyanmisaka     int     fd;
54*437bfbebSnyanmisaka     void*   addr;
55*437bfbebSnyanmisaka     int     offset;
56*437bfbebSnyanmisaka 
57*437bfbebSnyanmisaka     int     w_vld;
58*437bfbebSnyanmisaka     int     h_vld;
59*437bfbebSnyanmisaka     int     w_vir;
60*437bfbebSnyanmisaka     int     h_vir;
61*437bfbebSnyanmisaka } vdpp_plane_info;
62*437bfbebSnyanmisaka 
63*437bfbebSnyanmisaka typedef struct {
64*437bfbebSnyanmisaka     vdpp_plane_info     img_yrgb;
65*437bfbebSnyanmisaka     vdpp_plane_info     img_cbcr;
66*437bfbebSnyanmisaka 
67*437bfbebSnyanmisaka     vdpp_frame_format   img_fmt;
68*437bfbebSnyanmisaka } vdpp_img_info;
69*437bfbebSnyanmisaka 
70*437bfbebSnyanmisaka /* vdpp module config */
71*437bfbebSnyanmisaka typedef struct {
72*437bfbebSnyanmisaka     // dmsr config
73*437bfbebSnyanmisaka     unsigned int dmsr_en;
74*437bfbebSnyanmisaka     unsigned int str_pri_y;
75*437bfbebSnyanmisaka     unsigned int str_sec_y;
76*437bfbebSnyanmisaka     unsigned int dumping_y;
77*437bfbebSnyanmisaka     unsigned int reserve_dmsr[4];
78*437bfbebSnyanmisaka 
79*437bfbebSnyanmisaka     // es config
80*437bfbebSnyanmisaka     unsigned int es_en;
81*437bfbebSnyanmisaka     unsigned int es_iWgtGain;
82*437bfbebSnyanmisaka     unsigned int reserve_es[4];
83*437bfbebSnyanmisaka 
84*437bfbebSnyanmisaka     // zme config
85*437bfbebSnyanmisaka     unsigned int zme_dering_en;
86*437bfbebSnyanmisaka     unsigned int reserve_zme[4];
87*437bfbebSnyanmisaka 
88*437bfbebSnyanmisaka     // hist_cnt config
89*437bfbebSnyanmisaka     unsigned int hist_cnt_en;
90*437bfbebSnyanmisaka     unsigned int hist_csc_range;
91*437bfbebSnyanmisaka     unsigned int reserve_hist_cnt[4];
92*437bfbebSnyanmisaka 
93*437bfbebSnyanmisaka     // sharp config
94*437bfbebSnyanmisaka     unsigned int shp_en;
95*437bfbebSnyanmisaka     unsigned int peaking_gain;
96*437bfbebSnyanmisaka     unsigned int shp_shoot_ctrl_en;
97*437bfbebSnyanmisaka     unsigned int shp_shoot_ctrl_over;
98*437bfbebSnyanmisaka     unsigned int shp_shoot_ctrl_under;
99*437bfbebSnyanmisaka     unsigned int reserve_shp[4];
100*437bfbebSnyanmisaka } vdpp_params;
101*437bfbebSnyanmisaka 
102*437bfbebSnyanmisaka typedef struct {
103*437bfbebSnyanmisaka     void*               p_hist_addr;
104*437bfbebSnyanmisaka     unsigned int        hist_length;
105*437bfbebSnyanmisaka     unsigned short      vdpp_img_w_in;
106*437bfbebSnyanmisaka     unsigned short      vdpp_img_h_in;
107*437bfbebSnyanmisaka     unsigned short      vdpp_img_w_out;
108*437bfbebSnyanmisaka     unsigned short      vdpp_img_h_out;
109*437bfbebSnyanmisaka     unsigned short      vdpp_blk_size_h;
110*437bfbebSnyanmisaka     unsigned short      vdpp_blk_size_v;
111*437bfbebSnyanmisaka } hwpq_vdpp_info_t;
112*437bfbebSnyanmisaka 
113*437bfbebSnyanmisaka typedef struct {
114*437bfbebSnyanmisaka     unsigned int    frame_idx;
115*437bfbebSnyanmisaka     unsigned int    yuv_diff_flag;
116*437bfbebSnyanmisaka     unsigned int    hist_mode_en;
117*437bfbebSnyanmisaka 
118*437bfbebSnyanmisaka     vdpp_img_info   src_img_info;
119*437bfbebSnyanmisaka     vdpp_img_info   dst_img_info;
120*437bfbebSnyanmisaka     unsigned int    hist_buf_fd;
121*437bfbebSnyanmisaka     void*           p_hist_buf;
122*437bfbebSnyanmisaka 
123*437bfbebSnyanmisaka     unsigned int    vdpp_config_update_flag;
124*437bfbebSnyanmisaka     vdpp_params     vdpp_config;
125*437bfbebSnyanmisaka 
126*437bfbebSnyanmisaka     hwpq_vdpp_info_t dci_vdpp_info;
127*437bfbebSnyanmisaka 
128*437bfbebSnyanmisaka } rk_vdpp_proc_params;
129*437bfbebSnyanmisaka 
130*437bfbebSnyanmisaka #ifdef __cplusplus
131*437bfbebSnyanmisaka extern "C"
132*437bfbebSnyanmisaka {
133*437bfbebSnyanmisaka #endif
134*437bfbebSnyanmisaka 
135*437bfbebSnyanmisaka int hwpq_vdpp_init(rk_vdpp_context *p_ctx_ptr);
136*437bfbebSnyanmisaka int hwpq_vdpp_check_work_mode(rk_vdpp_context ctx, rk_vdpp_proc_params *p_proc_param);
137*437bfbebSnyanmisaka int hwpq_vdpp_proc(rk_vdpp_context ctx, rk_vdpp_proc_params *p_proc_param);
138*437bfbebSnyanmisaka int hwpq_vdpp_deinit(rk_vdpp_context ctx);
139*437bfbebSnyanmisaka 
140*437bfbebSnyanmisaka #ifdef __cplusplus
141*437bfbebSnyanmisaka }
142*437bfbebSnyanmisaka #endif
143*437bfbebSnyanmisaka 
144*437bfbebSnyanmisaka #endif // __HWPQ_VDPP_PROC_API_H__