xref: /rockchip-linux_mpp/mpp/hal/vpu/vp8e/hal_vp8e_table.h (revision 437bfbeb9567cca9cd9080e3f6954aa9d6a94f18)
1*437bfbebSnyanmisaka /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2*437bfbebSnyanmisaka /*
3*437bfbebSnyanmisaka  * Copyright (c) 2017 Rockchip Electronics Co., Ltd.
4*437bfbebSnyanmisaka  */
5*437bfbebSnyanmisaka 
6*437bfbebSnyanmisaka #ifndef __HAL_VP8E_TABLE_H__
7*437bfbebSnyanmisaka #define __HAL_VP8E_TABLE_H__
8*437bfbebSnyanmisaka 
9*437bfbebSnyanmisaka #include "hal_vp8e_base.h"
10*437bfbebSnyanmisaka #include "hal_vp8e_putbit.h"
11*437bfbebSnyanmisaka 
12*437bfbebSnyanmisaka extern RK_S32 const default_prob_coeff_tbl[4][8][3][11];
13*437bfbebSnyanmisaka 
14*437bfbebSnyanmisaka extern RK_S32 const default_prob_mv_tbl[2][19];
15*437bfbebSnyanmisaka 
16*437bfbebSnyanmisaka extern RK_S32 const vp8_prob_cost_tbl[];
17*437bfbebSnyanmisaka 
18*437bfbebSnyanmisaka extern RK_S32 const coeff_update_prob_tbl[4][8][3][11];
19*437bfbebSnyanmisaka 
20*437bfbebSnyanmisaka extern RK_S32 const mv_update_prob_tbl[2][19];
21*437bfbebSnyanmisaka 
22*437bfbebSnyanmisaka extern RK_S32 const default_skip_false_prob_tbl[128];
23*437bfbebSnyanmisaka 
24*437bfbebSnyanmisaka extern RK_S32 const y_mode_prob_tbl[4];
25*437bfbebSnyanmisaka 
26*437bfbebSnyanmisaka extern RK_S32 const uv_mode_prob_tbl[3];
27*437bfbebSnyanmisaka 
28*437bfbebSnyanmisaka extern Vp8eTree const mv_tree_tbl[];
29*437bfbebSnyanmisaka 
30*437bfbebSnyanmisaka extern RK_S32 const dc_q_lookup_tbl[QINDEX_RANGE];
31*437bfbebSnyanmisaka 
32*437bfbebSnyanmisaka extern RK_S32 const ac_q_lookup_tbl[QINDEX_RANGE];
33*437bfbebSnyanmisaka 
34*437bfbebSnyanmisaka extern RK_S32 const q_rounding_factors_tbl[QINDEX_RANGE];
35*437bfbebSnyanmisaka 
36*437bfbebSnyanmisaka extern RK_S32 const q_zbin_factors_tbl[QINDEX_RANGE];
37*437bfbebSnyanmisaka 
38*437bfbebSnyanmisaka extern RK_S32 const zbin_boost_tbl[16];
39*437bfbebSnyanmisaka 
40*437bfbebSnyanmisaka extern RK_S32 const vp8_split_penalty_tbl[128];
41*437bfbebSnyanmisaka 
42*437bfbebSnyanmisaka extern RK_S32 const weight_tbl[128];
43*437bfbebSnyanmisaka 
44*437bfbebSnyanmisaka extern RK_S32 const intra4_mode_tree_penalty_tbl[];
45*437bfbebSnyanmisaka 
46*437bfbebSnyanmisaka extern RK_S32 const intra16_mode_tree_penalty_tbl[];
47*437bfbebSnyanmisaka 
48*437bfbebSnyanmisaka extern const RK_S32 inter_level_tbl[128];
49*437bfbebSnyanmisaka 
50*437bfbebSnyanmisaka extern RK_S32 const offset_tbl[];
51*437bfbebSnyanmisaka 
52*437bfbebSnyanmisaka #endif /*__HAL_VP8E_TBL_H__*/
53