xref: /rockchip-linux_mpp/mpp/hal/vpu/mpg4d/hal_m4vd_api.c (revision 437bfbeb9567cca9cd9080e3f6954aa9d6a94f18)
1*437bfbebSnyanmisaka /*
2*437bfbebSnyanmisaka  * Copyright 2017 Rockchip Electronics Co. LTD
3*437bfbebSnyanmisaka  *
4*437bfbebSnyanmisaka  * Licensed under the Apache License, Version 2.0 (the "License");
5*437bfbebSnyanmisaka  * you may not use this file except in compliance with the License.
6*437bfbebSnyanmisaka  * You may obtain a copy of the License at
7*437bfbebSnyanmisaka  *
8*437bfbebSnyanmisaka  *      http://www.apache.org/licenses/LICENSE-2.0
9*437bfbebSnyanmisaka  *
10*437bfbebSnyanmisaka  * Unless required by applicable law or agreed to in writing, software
11*437bfbebSnyanmisaka  * distributed under the License is distributed on an "AS IS" BASIS,
12*437bfbebSnyanmisaka  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13*437bfbebSnyanmisaka  * See the License for the specific language governing permissions and
14*437bfbebSnyanmisaka  * limitations under the License.
15*437bfbebSnyanmisaka  */
16*437bfbebSnyanmisaka 
17*437bfbebSnyanmisaka #define MODULE_TAG "hal_m4vd_api"
18*437bfbebSnyanmisaka 
19*437bfbebSnyanmisaka #include <stdio.h>
20*437bfbebSnyanmisaka #include <stdlib.h>
21*437bfbebSnyanmisaka #include <string.h>
22*437bfbebSnyanmisaka #include <dlfcn.h>
23*437bfbebSnyanmisaka #include <unistd.h>
24*437bfbebSnyanmisaka 
25*437bfbebSnyanmisaka #include "mpp_err.h"
26*437bfbebSnyanmisaka #include "mpp_mem.h"
27*437bfbebSnyanmisaka #include "mpp_env.h"
28*437bfbebSnyanmisaka #include "mpp_debug.h"
29*437bfbebSnyanmisaka #include "mpp_platform.h"
30*437bfbebSnyanmisaka 
31*437bfbebSnyanmisaka #include "hal_mpg4d_api.h"
32*437bfbebSnyanmisaka #include "hal_m4vd_com.h"
33*437bfbebSnyanmisaka 
34*437bfbebSnyanmisaka #include "hal_m4vd_vdpu1.h"
35*437bfbebSnyanmisaka #include "hal_m4vd_vdpu2.h"
36*437bfbebSnyanmisaka 
37*437bfbebSnyanmisaka RK_U32 hal_mpg4d_debug = 1;
38*437bfbebSnyanmisaka 
39*437bfbebSnyanmisaka /*!
40*437bfbebSnyanmisaka ***********************************************************************
41*437bfbebSnyanmisaka * \brief
42*437bfbebSnyanmisaka *    init
43*437bfbebSnyanmisaka ***********************************************************************
44*437bfbebSnyanmisaka */
45*437bfbebSnyanmisaka //extern "C"
hal_vpu_mpg4d_init(void * hal,MppHalCfg * cfg)46*437bfbebSnyanmisaka static MPP_RET hal_vpu_mpg4d_init(void *hal, MppHalCfg *cfg)
47*437bfbebSnyanmisaka {
48*437bfbebSnyanmisaka     hal_mpg4_ctx *p_hal = (hal_mpg4_ctx *)hal;
49*437bfbebSnyanmisaka     MppHalApi *p_api = NULL;
50*437bfbebSnyanmisaka     VpuHwMode hw_mode = MODE_NULL;
51*437bfbebSnyanmisaka     RK_U32 hw_flag = 0;
52*437bfbebSnyanmisaka 
53*437bfbebSnyanmisaka     if (NULL == p_hal)
54*437bfbebSnyanmisaka         return MPP_ERR_VALUE;
55*437bfbebSnyanmisaka 
56*437bfbebSnyanmisaka     memset(p_hal, 0, sizeof(hal_mpg4_ctx));
57*437bfbebSnyanmisaka     p_api = &p_hal->hal_api;
58*437bfbebSnyanmisaka 
59*437bfbebSnyanmisaka     hw_flag = mpp_get_vcodec_type();
60*437bfbebSnyanmisaka     mpp_assert(hw_flag & (HAVE_VDPU2 | HAVE_VDPU1));
61*437bfbebSnyanmisaka 
62*437bfbebSnyanmisaka     if (hw_flag & HAVE_VDPU2)
63*437bfbebSnyanmisaka         hw_mode = VDPU2_MODE;
64*437bfbebSnyanmisaka     if (hw_flag & HAVE_VDPU1)
65*437bfbebSnyanmisaka         hw_mode = VDPU1_MODE;
66*437bfbebSnyanmisaka 
67*437bfbebSnyanmisaka     switch (hw_mode) {
68*437bfbebSnyanmisaka     case VDPU2_MODE:
69*437bfbebSnyanmisaka         p_api->init = vdpu2_mpg4d_init;
70*437bfbebSnyanmisaka         p_api->deinit = vdpu2_mpg4d_deinit;
71*437bfbebSnyanmisaka         p_api->reg_gen = vdpu2_mpg4d_gen_regs;
72*437bfbebSnyanmisaka         p_api->start = vdpu2_mpg4d_start;
73*437bfbebSnyanmisaka         p_api->wait = vdpu2_mpg4d_wait;
74*437bfbebSnyanmisaka         p_api->reset = NULL;
75*437bfbebSnyanmisaka         p_api->flush = NULL;
76*437bfbebSnyanmisaka         p_api->control = NULL;
77*437bfbebSnyanmisaka         break;
78*437bfbebSnyanmisaka     case VDPU1_MODE:
79*437bfbebSnyanmisaka         p_api->init = vdpu1_mpg4d_init;
80*437bfbebSnyanmisaka         p_api->deinit = vdpu1_mpg4d_deinit;
81*437bfbebSnyanmisaka         p_api->reg_gen = vdpu1_mpg4d_gen_regs;
82*437bfbebSnyanmisaka         p_api->start = vdpu1_mpg4d_start;
83*437bfbebSnyanmisaka         p_api->wait = vdpu1_mpg4d_wait;
84*437bfbebSnyanmisaka         p_api->reset = NULL;
85*437bfbebSnyanmisaka         p_api->flush = NULL;
86*437bfbebSnyanmisaka         p_api->control = NULL;
87*437bfbebSnyanmisaka         break;
88*437bfbebSnyanmisaka     default:
89*437bfbebSnyanmisaka         return MPP_ERR_INIT;
90*437bfbebSnyanmisaka         break;
91*437bfbebSnyanmisaka     }
92*437bfbebSnyanmisaka 
93*437bfbebSnyanmisaka     return p_api->init (hal, cfg);
94*437bfbebSnyanmisaka }
95*437bfbebSnyanmisaka 
96*437bfbebSnyanmisaka /*!
97*437bfbebSnyanmisaka ***********************************************************************
98*437bfbebSnyanmisaka * \brief
99*437bfbebSnyanmisaka *    deinit
100*437bfbebSnyanmisaka ***********************************************************************
101*437bfbebSnyanmisaka */
102*437bfbebSnyanmisaka //extern "C"
hal_vpu_mpg4d_deinit(void * hal)103*437bfbebSnyanmisaka static MPP_RET hal_vpu_mpg4d_deinit(void *hal)
104*437bfbebSnyanmisaka {
105*437bfbebSnyanmisaka     hal_mpg4_ctx *p_hal = (hal_mpg4_ctx *)hal;
106*437bfbebSnyanmisaka 
107*437bfbebSnyanmisaka     return p_hal->hal_api.deinit(hal);
108*437bfbebSnyanmisaka }
109*437bfbebSnyanmisaka 
110*437bfbebSnyanmisaka /*!
111*437bfbebSnyanmisaka ***********************************************************************
112*437bfbebSnyanmisaka * \brief
113*437bfbebSnyanmisaka *    generate register
114*437bfbebSnyanmisaka ***********************************************************************
115*437bfbebSnyanmisaka */
116*437bfbebSnyanmisaka //extern "C"
hal_vpu_mpg4d_gen_regs(void * hal,HalTaskInfo * task)117*437bfbebSnyanmisaka static MPP_RET hal_vpu_mpg4d_gen_regs(void *hal, HalTaskInfo *task)
118*437bfbebSnyanmisaka {
119*437bfbebSnyanmisaka     hal_mpg4_ctx *p_hal = (hal_mpg4_ctx *)hal;
120*437bfbebSnyanmisaka 
121*437bfbebSnyanmisaka     return p_hal->hal_api.reg_gen(hal, task);
122*437bfbebSnyanmisaka }
123*437bfbebSnyanmisaka 
124*437bfbebSnyanmisaka /*!
125*437bfbebSnyanmisaka ***********************************************************************
126*437bfbebSnyanmisaka * \brief h
127*437bfbebSnyanmisaka *    start hard
128*437bfbebSnyanmisaka ***********************************************************************
129*437bfbebSnyanmisaka */
130*437bfbebSnyanmisaka //extern "C"
hal_vpu_mpg4d_start(void * hal,HalTaskInfo * task)131*437bfbebSnyanmisaka static MPP_RET hal_vpu_mpg4d_start(void *hal, HalTaskInfo *task)
132*437bfbebSnyanmisaka {
133*437bfbebSnyanmisaka     hal_mpg4_ctx *p_hal = (hal_mpg4_ctx *)hal;
134*437bfbebSnyanmisaka 
135*437bfbebSnyanmisaka     return p_hal->hal_api.start(hal, task);
136*437bfbebSnyanmisaka }
137*437bfbebSnyanmisaka 
138*437bfbebSnyanmisaka /*!
139*437bfbebSnyanmisaka ***********************************************************************
140*437bfbebSnyanmisaka * \brief
141*437bfbebSnyanmisaka *    wait hard
142*437bfbebSnyanmisaka ***********************************************************************
143*437bfbebSnyanmisaka */
144*437bfbebSnyanmisaka //extern "C"
hal_vpu_mpg4d_wait(void * hal,HalTaskInfo * task)145*437bfbebSnyanmisaka static MPP_RET hal_vpu_mpg4d_wait(void *hal, HalTaskInfo *task)
146*437bfbebSnyanmisaka {
147*437bfbebSnyanmisaka     hal_mpg4_ctx *p_hal = (hal_mpg4_ctx *)hal;
148*437bfbebSnyanmisaka 
149*437bfbebSnyanmisaka     return p_hal->hal_api.wait(hal, task);
150*437bfbebSnyanmisaka }
151*437bfbebSnyanmisaka 
152*437bfbebSnyanmisaka const MppHalApi hal_api_mpg4d = {
153*437bfbebSnyanmisaka     .name = "mpg4d_vpu",
154*437bfbebSnyanmisaka     .type = MPP_CTX_DEC,
155*437bfbebSnyanmisaka     .coding = MPP_VIDEO_CodingMPEG4,
156*437bfbebSnyanmisaka     .ctx_size = sizeof(hal_mpg4_ctx),
157*437bfbebSnyanmisaka     .flag = 0,
158*437bfbebSnyanmisaka     .init = hal_vpu_mpg4d_init,
159*437bfbebSnyanmisaka     .deinit = hal_vpu_mpg4d_deinit,
160*437bfbebSnyanmisaka     .reg_gen = hal_vpu_mpg4d_gen_regs,
161*437bfbebSnyanmisaka     .start = hal_vpu_mpg4d_start,
162*437bfbebSnyanmisaka     .wait = hal_vpu_mpg4d_wait,
163*437bfbebSnyanmisaka     .reset = NULL,
164*437bfbebSnyanmisaka     .flush = NULL,
165*437bfbebSnyanmisaka     .control = NULL,
166*437bfbebSnyanmisaka };
167