1 /*
2 * Copyright 2015 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_h264e_vepu1_v2"
18
19 #include <string.h>
20
21 #include "mpp_env.h"
22 #include "mpp_mem.h"
23 #include "mpp_frame.h"
24 #include "mpp_common.h"
25 #include "mpp_device.h"
26 #include "mpp_rc.h"
27 #include "mpp_packet_impl.h"
28
29 #include "mpp_enc_hal.h"
30 #include "h264e_debug.h"
31 #include "h264e_sps.h"
32 #include "h264e_pps.h"
33 #include "h264e_slice.h"
34
35 #include "hal_h264e_debug.h"
36 #include "hal_h264e_vpu_tbl.h"
37 #include "hal_h264e_vepu_v2.h"
38 #include "hal_h264e_stream_amend.h"
39
40 #include "hal_h264e_vepu1_reg_tbl.h"
41
42 typedef struct HalH264eVepu1Ctx_t {
43 MppEncCfgSet *cfg;
44
45 MppDev dev;
46 RK_S32 frame_cnt;
47
48 /* buffers management */
49 HalH264eVepuBufs hw_bufs;
50
51 /* preprocess config */
52 HalH264eVepuPrep hw_prep;
53
54 /* input / recon / refer address config */
55 HalH264eVepuAddr hw_addr;
56 VepuOffsetCfg hw_offset;
57
58 /* macroblock ratecontrol config */
59 HalH264eVepuMbRc hw_mbrc;
60
61 /* syntax for input from enc_impl */
62 RK_U32 updated;
63 H264eSps *sps;
64 H264ePps *pps;
65 H264eSlice *slice;
66 H264eFrmInfo *frms;
67 H264eReorderInfo *reorder;
68 H264eMarkingInfo *marking;
69 H264ePrefixNal *prefix;
70
71 /* special TSVC stream header fixup */
72 HalH264eVepuStreamAmend amend;
73
74 /* vepu1 macroblock ratecontrol context */
75 HalH264eVepuMbRcCtx rc_ctx;
76
77 H264eVpu1RegSet regs_set;
78 H264eVpu1RegSet regs_get;
79 } HalH264eVepu1Ctx;
80
hal_h264e_vepu1_deinit_v2(void * hal)81 static MPP_RET hal_h264e_vepu1_deinit_v2(void *hal)
82 {
83 HalH264eVepu1Ctx *p = (HalH264eVepu1Ctx *)hal;
84
85 hal_h264e_dbg_func("enter %p\n", p);
86
87 if (p->dev) {
88 mpp_dev_deinit(p->dev);
89 p->dev = NULL;
90 }
91
92 h264e_vepu_buf_deinit(&p->hw_bufs);
93
94 if (p->rc_ctx) {
95 h264e_vepu_mbrc_deinit(p->rc_ctx);
96 p->rc_ctx = NULL;
97 }
98
99 h264e_vepu_stream_amend_deinit(&p->amend);
100
101 hal_h264e_dbg_func("leave %p\n", p);
102
103 return MPP_OK;
104 }
105
hal_h264e_vepu1_init_v2(void * hal,MppEncHalCfg * cfg)106 static MPP_RET hal_h264e_vepu1_init_v2(void *hal, MppEncHalCfg *cfg)
107 {
108 HalH264eVepu1Ctx *p = (HalH264eVepu1Ctx *)hal;
109 MPP_RET ret = MPP_OK;
110
111 hal_h264e_dbg_func("enter %p\n", p);
112
113 p->cfg = cfg->cfg;
114
115 /* update output to MppEnc */
116 cfg->type = VPU_CLIENT_VEPU1;
117 ret = mpp_dev_init(&cfg->dev, cfg->type);
118 if (ret) {
119 mpp_err_f("mpp_dev_init failed ret: %d\n", ret);
120 goto DONE;
121 }
122 p->dev = cfg->dev;
123
124 ret = h264e_vepu_buf_init(&p->hw_bufs);
125 if (ret) {
126 mpp_err_f("init vepu buffer failed ret: %d\n", ret);
127 goto DONE;
128 }
129
130 ret = h264e_vepu_mbrc_init(&p->rc_ctx, &p->hw_mbrc);
131 if (ret) {
132 mpp_err_f("init mb rate control failed ret: %d\n", ret);
133 goto DONE;
134 }
135
136 /* create buffer to TSVC stream */
137 h264e_vepu_stream_amend_init(&p->amend);
138
139 DONE:
140 if (ret)
141 hal_h264e_vepu1_deinit_v2(hal);
142
143 hal_h264e_dbg_func("leave %p\n", p);
144 return ret;
145 }
146
update_vepu1_syntax(HalH264eVepu1Ctx * ctx,MppSyntax * syntax)147 static RK_U32 update_vepu1_syntax(HalH264eVepu1Ctx *ctx, MppSyntax *syntax)
148 {
149 H264eSyntaxDesc *desc = syntax->data;
150 RK_S32 syn_num = syntax->number;
151 RK_U32 updated = 0;
152 RK_S32 i;
153
154 for (i = 0; i < syn_num; i++, desc++) {
155 switch (desc->type) {
156 case H264E_SYN_CFG : {
157 hal_h264e_dbg_detail("update cfg");
158 ctx->cfg = desc->p;
159 } break;
160 case H264E_SYN_SPS : {
161 hal_h264e_dbg_detail("update sps");
162 ctx->sps = desc->p;
163 } break;
164 case H264E_SYN_PPS : {
165 hal_h264e_dbg_detail("update pps");
166 ctx->pps = desc->p;
167 } break;
168 case H264E_SYN_DPB : {
169 hal_h264e_dbg_detail("update dpb");
170 } break;
171 case H264E_SYN_SLICE : {
172 hal_h264e_dbg_detail("update slice");
173 ctx->slice = desc->p;
174 } break;
175 case H264E_SYN_FRAME : {
176 hal_h264e_dbg_detail("update frames");
177 ctx->frms = desc->p;
178 } break;
179 case H264E_SYN_PREFIX : {
180 hal_h264e_dbg_detail("update prefix nal");
181 ctx->prefix = desc->p;
182 } break;
183 default : {
184 mpp_log_f("invalid syntax type %d\n", desc->type);
185 } break;
186 }
187
188 updated |= SYN_TYPE_FLAG(desc->type);
189 }
190
191 return updated;
192 }
193
hal_h264e_vepu1_get_task_v2(void * hal,HalEncTask * task)194 static MPP_RET hal_h264e_vepu1_get_task_v2(void *hal, HalEncTask *task)
195 {
196 HalH264eVepu1Ctx *ctx = (HalH264eVepu1Ctx *)hal;
197 RK_U32 updated = update_vepu1_syntax(ctx, &task->syntax);
198 MppEncPrepCfg *prep = &ctx->cfg->prep;
199 HalH264eVepuPrep *hw_prep = &ctx->hw_prep;
200 HalH264eVepuAddr *hw_addr = &ctx->hw_addr;
201 HalH264eVepuBufs *hw_bufs = &ctx->hw_bufs;
202 VepuOffsetCfg *hw_offset = &ctx->hw_offset;
203 H264eFrmInfo *frms = ctx->frms;
204
205 hal_h264e_dbg_func("enter %p\n", hal);
206
207 if (updated & SYN_TYPE_FLAG(H264E_SYN_CFG)) {
208 h264e_vepu_buf_set_frame_size(hw_bufs, prep->width, prep->height);
209
210 /* preprocess setup */
211 if (h264e_vepu_prep_setup(hw_prep, prep))
212 return MPP_NOK;
213
214 h264e_vepu_mbrc_setup(ctx->rc_ctx, ctx->cfg);
215 }
216
217 if (updated & SYN_TYPE_FLAG(H264E_SYN_SLICE)) {
218 H264eSlice *slice = ctx->slice;
219
220 h264e_vepu_buf_set_cabac_idc(hw_bufs, slice->cabac_init_idc);
221 }
222
223 h264e_vepu_prep_get_addr(hw_prep, task->input, &hw_addr->orig);
224
225 MppBuffer recn = h264e_vepu_buf_get_frame_buffer(hw_bufs, frms->curr_idx);
226 MppBuffer refr = h264e_vepu_buf_get_frame_buffer(hw_bufs, frms->refr_idx);
227
228 hw_addr->recn[0] = mpp_buffer_get_fd(recn);
229 hw_addr->refr[0] = mpp_buffer_get_fd(refr);
230 hw_addr->recn[1] = hw_addr->recn[0];
231 hw_addr->refr[1] = hw_addr->refr[0];
232
233 hw_offset->fmt = prep->format;
234 hw_offset->width = prep->width;
235 hw_offset->height = prep->height;
236 hw_offset->hor_stride = prep->hor_stride;
237 hw_offset->ver_stride = prep->ver_stride;
238 hw_offset->offset_x = mpp_frame_get_offset_x(task->frame);
239 hw_offset->offset_y = mpp_frame_get_offset_y(task->frame);
240
241 get_vepu_offset_cfg(hw_offset);
242
243 h264e_vepu_stream_amend_config(&ctx->amend, task->packet, ctx->cfg,
244 ctx->slice, ctx->prefix);
245
246 hal_h264e_dbg_func("leave %p\n", hal);
247
248 return MPP_OK;
249 }
250
setup_output_packet(HalH264eVepu1Ctx * ctx,RK_U32 * reg,MppBuffer buf,RK_U32 offset)251 static RK_S32 setup_output_packet(HalH264eVepu1Ctx *ctx, RK_U32 *reg, MppBuffer buf, RK_U32 offset)
252 {
253 RK_U32 offset8 = offset & (~0x7);
254 RK_S32 fd = mpp_buffer_get_fd(buf);
255 RK_U32 hdr_rem_msb = 0;
256 RK_U32 hdr_rem_lsb = 0;
257 RK_U32 limit = 0;
258
259 if (offset) {
260 RK_U8 *buf32 = (RK_U8 *)mpp_buffer_get_ptr(buf) + offset8;
261
262 hdr_rem_msb = MPP_RB32(buf32);
263 hdr_rem_lsb = MPP_RB32(buf32 + 4);
264 }
265
266 hal_h264e_dbg_detail("offset %d offset8 %d\n", offset, offset8);
267 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_STREAM, fd);
268 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_OUTPUT_STREAM >> 2, offset8);
269
270 /* output buffer size is 64 bit address then 8 multiple size */
271 limit = mpp_buffer_get_size(buf);
272 limit -= offset8;
273 limit >>= 3;
274 limit &= ~7;
275 H264E_HAL_SET_REG(reg, VEPU_REG_STR_BUF_LIMIT, limit);
276
277 hal_h264e_dbg_detail("msb %08x lsb %08x", hdr_rem_msb, hdr_rem_lsb);
278
279 H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_MSB, hdr_rem_msb);
280 H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_LSB, hdr_rem_lsb);
281
282 return (offset - offset8) * 8;
283 }
284
hal_h264e_vepu1_gen_regs_v2(void * hal,HalEncTask * task)285 static MPP_RET hal_h264e_vepu1_gen_regs_v2(void *hal, HalEncTask *task)
286 {
287 //MPP_RET ret = MPP_OK;
288 HalH264eVepu1Ctx *ctx = (HalH264eVepu1Ctx *)hal;
289 HalH264eVepuBufs *hw_bufs = &ctx->hw_bufs;
290 HalH264eVepuPrep *hw_prep = &ctx->hw_prep;
291 HalH264eVepuAddr *hw_addr = &ctx->hw_addr;
292 HalH264eVepuMbRc *hw_mbrc = &ctx->hw_mbrc;
293 VepuOffsetCfg *hw_offset = &ctx->hw_offset;
294 EncRcTaskInfo *rc_info = &task->rc_task->info;
295 EncFrmStatus *frm = &task->rc_task->frm;
296 H264eSps *sps = ctx->sps;
297 H264ePps *pps = ctx->pps;
298 H264eSlice *slice = ctx->slice;
299 RK_U32 *reg = ctx->regs_set.val;
300 RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
301 RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
302 RK_U32 offset = mpp_packet_get_length(task->packet);
303 RK_U32 first_free_bit = 0;
304 RK_U32 val = 0;
305 RK_S32 i = 0;
306
307 if (hw_prep->rotation) {
308 mb_w = ctx->sps->pic_height_in_mbs;
309 mb_h = ctx->sps->pic_width_in_mbs;
310 }
311
312 hw_mbrc->qp_init = rc_info->quality_target;
313 hw_mbrc->qp_max = rc_info->quality_max;
314 hw_mbrc->qp_min = rc_info->quality_min;
315
316 hal_h264e_dbg_func("enter %p\n", hal);
317
318 hal_h264e_dbg_detail("frame %d generate regs now", frm->seq_idx);
319
320 // prepare mb rc config
321 h264e_vepu_mbrc_prepare(ctx->rc_ctx, &ctx->hw_mbrc, task->rc_task);
322
323 h264e_vepu_slice_split_cfg(ctx->slice, &ctx->hw_mbrc, task->rc_task, ctx->cfg);
324
325 /* setup output address with offset */
326 first_free_bit = setup_output_packet(ctx, reg, task->output, offset);
327 /* set extra byte for header */
328 hw_mbrc->hdr_strm_size = offset;
329 hw_mbrc->hdr_free_size = first_free_bit / 8;
330 hw_mbrc->out_strm_size = 0;
331
332 /*
333 * The hardware needs only the value for luma plane, because
334 * values of other planes are calculated internally based on
335 * format setting.
336 */
337 val = VEPU_REG_INTRA_AREA_TOP(mb_h)
338 | VEPU_REG_INTRA_AREA_BOTTOM(mb_h)
339 | VEPU_REG_INTRA_AREA_LEFT(mb_w)
340 | VEPU_REG_INTRA_AREA_RIGHT(mb_w);
341 H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_AREA_CTRL, val); //FIXED
342
343 val = VEPU_REG_AXI_CTRL_WRITE_ID(0)
344 | VEPU_REG_AXI_CTRL_READ_ID(0)
345 | VEPU_REG_OUTPUT_SWAP16
346 | VEPU_REG_INPUT_SWAP16_(hw_prep->swap_16_in)
347 | VEPU_REG_AXI_CTRL_BURST_LEN(16)
348 | VEPU_REG_OUTPUT_SWAP32
349 | VEPU_REG_INPUT_SWAP32_(hw_prep->swap_32_in)
350 | VEPU_REG_OUTPUT_SWAP8
351 | VEPU_REG_INPUT_SWAP8_(hw_prep->swap_8_in);
352 H264E_HAL_SET_REG(reg, VEPU_REG_AXI_CTRL, val);
353
354 val = VEPU_REG_MAD_QP_ADJUSTMENT (hw_mbrc->mad_qp_change)
355 | VEPU_REG_MAD_THRESHOLD(hw_mbrc->mad_threshold);
356 H264E_HAL_SET_REG(reg, VEPU_REG_MAD_CTRL, val);
357
358 val = 0;
359 if (mb_w * mb_h > 3600)
360 val = VEPU_REG_DISABLE_QUARTER_PIXEL_MV;
361 val |= VEPU_REG_CABAC_INIT_IDC(slice->cabac_init_idc);
362 if (pps->entropy_coding_mode)
363 val |= VEPU_REG_ENTROPY_CODING_MODE;
364 if (pps->transform_8x8_mode)
365 val |= VEPU_REG_H264_TRANS8X8_MODE;
366 if (sps->profile_idc > 31)
367 val |= VEPU_REG_H264_INTER4X4_MODE;
368 /*reg |= VEPU_REG_H264_STREAM_MODE;*/
369 val |= VEPU_REG_H264_SLICE_SIZE(hw_mbrc->slice_size_mb_rows)
370 | VEPU_REG_INTRA16X16_MODE(h264_intra16_favor[hw_mbrc->qp_init]);
371
372 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL2, val);
373
374 RK_U32 scaler = MPP_MAX(1, 200 / (mb_w + mb_h));
375 RK_U32 skip_penalty = MPP_MIN(255, h264_skip_sad_penalty[hw_mbrc->qp_init] * scaler);
376 RK_U32 overfill_r = (hw_prep->src_w & 0x0f) ?
377 ((16 - (hw_prep->src_w & 0x0f)) / 4) : 0;
378 RK_U32 overfill_b = (hw_prep->src_h & 0x0f) ?
379 (16 - (hw_prep->src_h & 0x0f)) : 0;
380
381 val = VEPU_REG_SKIP_MACROBLOCK_PENALTY(skip_penalty)
382 | VEPU_REG_INTER_MODE(h264_inter_favor[hw_mbrc->qp_init]);
383 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL_4, val);
384
385 val = VEPU_REG_STREAM_START_OFFSET(first_free_bit);
386 H264E_HAL_SET_REG(reg, VEPU_REG_RLC_CTRL, val);
387
388 // When offset is zero row length should be total 16 aligned width
389 val = VEPU_REG_IN_IMG_CHROMA_OFFSET(0)
390 | VEPU_REG_IN_IMG_LUMA_OFFSET(0)
391 | VEPU_REG_IN_IMG_CTRL_ROW_LEN(hw_prep->pixel_stride)
392 | VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(overfill_r)
393 | VEPU_REG_IN_IMG_CTRL_OVRFLB(overfill_b)
394 | VEPU_REG_IN_IMG_CTRL_FMT(hw_prep->src_fmt)
395 | VEPU_REG_IN_IMG_ROTATE_MODE(hw_prep->rotation);
396
397 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_INPUT_IMAGE_CTRL, val);
398
399 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[0])
400 | VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[1]);
401 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(0), val);
402
403 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[2])
404 | VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[3]);
405 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(1), val);
406
407 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[4])
408 | VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[5]);
409 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(2), val);
410
411 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[6])
412 | VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[7]);
413 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(3), val);
414
415 val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[8])
416 | VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[9]);
417 H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(4), val);
418
419 val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[0])
420 | VEPU_REG_CHKPT_WORD_ERR_CHK0(hw_mbrc->cp_error[1]);
421 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(0), val);
422
423 val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[2])
424 | VEPU_REG_CHKPT_WORD_ERR_CHK0(hw_mbrc->cp_error[3]);
425 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(1), val);
426
427 val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[4])
428 | VEPU_REG_CHKPT_WORD_ERR_CHK0(hw_mbrc->cp_error[5]);
429 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(2), val);
430
431 val = VEPU_REG_CHKPT_DELTA_QP_CHK6(hw_mbrc->cp_delta_qp[6])
432 | VEPU_REG_CHKPT_DELTA_QP_CHK5(hw_mbrc->cp_delta_qp[5])
433 | VEPU_REG_CHKPT_DELTA_QP_CHK4(hw_mbrc->cp_delta_qp[4])
434 | VEPU_REG_CHKPT_DELTA_QP_CHK3(hw_mbrc->cp_delta_qp[3])
435 | VEPU_REG_CHKPT_DELTA_QP_CHK2(hw_mbrc->cp_delta_qp[2])
436 | VEPU_REG_CHKPT_DELTA_QP_CHK1(hw_mbrc->cp_delta_qp[1])
437 | VEPU_REG_CHKPT_DELTA_QP_CHK0(hw_mbrc->cp_delta_qp[0]);
438 H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_DELTA_QP, val);
439
440 val = VEPU_REG_PPS_INIT_QP(pps->pic_init_qp)
441 | VEPU_REG_SLICE_FILTER_ALPHA(slice->slice_alpha_c0_offset_div2)
442 | VEPU_REG_SLICE_FILTER_BETA(slice->slice_beta_offset_div2)
443 | VEPU_REG_CHROMA_QP_OFFSET(pps->chroma_qp_index_offset)
444 | VEPU_REG_IDR_PIC_ID(slice->idr_pic_id);
445
446 if (pps->constrained_intra_pred)
447 val |= VEPU_REG_CONSTRAINED_INTRA_PREDICTION;
448 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL0, val);
449
450 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_NEXT_PIC, 0);
451 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_MV_OUT, 0);
452
453 MppBuffer cabac_table = hw_bufs->cabac_table;
454 RK_S32 cabac_table_fd = cabac_table ? mpp_buffer_get_fd(cabac_table) : 0;
455
456 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_CABAC_TBL, cabac_table_fd);
457
458 val = VEPU_REG_ROI1_TOP_MB(mb_h)
459 | VEPU_REG_ROI1_BOTTOM_MB(mb_h)
460 | VEPU_REG_ROI1_LEFT_MB(mb_w)
461 | VEPU_REG_ROI1_RIGHT_MB(mb_w);
462 H264E_HAL_SET_REG(reg, VEPU_REG_ROI1, val);
463
464 val = VEPU_REG_ROI2_TOP_MB(mb_h)
465 | VEPU_REG_ROI2_BOTTOM_MB(mb_h)
466 | VEPU_REG_ROI2_LEFT_MB(mb_w)
467 | VEPU_REG_ROI2_RIGHT_MB(mb_w);
468 H264E_HAL_SET_REG(reg, VEPU_REG_ROI2, val);
469 H264E_HAL_SET_REG(reg, VEPU_REG_STABLILIZATION_OUTPUT, 0);
470
471 val = VEPU_REG_RGB2YUV_CONVERSION_COEFB(hw_prep->color_conversion_coeff_b)
472 | VEPU_REG_RGB2YUV_CONVERSION_COEFA(hw_prep->color_conversion_coeff_a);
473 H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF1, val);
474
475 val = VEPU_REG_RGB2YUV_CONVERSION_COEFE(hw_prep->color_conversion_coeff_e)
476 | VEPU_REG_RGB2YUV_CONVERSION_COEFC(hw_prep->color_conversion_coeff_c);
477 H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF2, val);
478
479 val = VEPU_REG_RGB2YUV_CONVERSION_COEFF(hw_prep->color_conversion_coeff_f)
480 | VEPU_REG_RGB_MASK_B_MSB(hw_prep->b_mask_msb)
481 | VEPU_REG_RGB_MASK_G_MSB(hw_prep->g_mask_msb)
482 | VEPU_REG_RGB_MASK_R_MSB(hw_prep->r_mask_msb);
483 H264E_HAL_SET_REG(reg, VEPU_REG_RGB_MASK_MSB, val);
484
485 {
486 RK_U32 diff_mv_penalty[3] = {0};
487 diff_mv_penalty[0] = h264_diff_mv_penalty4p[hw_mbrc->qp_init];
488 diff_mv_penalty[1] = h264_diff_mv_penalty[hw_mbrc->qp_init];
489 diff_mv_penalty[2] = h264_diff_mv_penalty[hw_mbrc->qp_init];
490
491 val = VEPU_REG_1MV_PENALTY(diff_mv_penalty[1])
492 | VEPU_REG_QMV_PENALTY(diff_mv_penalty[2])
493 | VEPU_REG_4MV_PENALTY(diff_mv_penalty[0]);
494 }
495
496 val |= VEPU_REG_SPLIT_MV_MODE_EN;
497 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL3, val);
498
499 val = VEPU_REG_H264_LUMA_INIT_QP(hw_mbrc->qp_init)
500 | VEPU_REG_H264_QP_MAX(hw_mbrc->qp_max)
501 | VEPU_REG_H264_QP_MIN(hw_mbrc->qp_min)
502 | VEPU_REG_H264_CHKPT_DISTANCE(hw_mbrc->cp_distance_mbs);
503 H264E_HAL_SET_REG(reg, VEPU_REG_QP_VAL, val);
504
505 val = VEPU_REG_ZERO_MV_FAVOR_D2(10);
506 H264E_HAL_SET_REG(reg, VEPU_REG_MVC_RELATE, val);
507
508 val = VEPU_REG_PPS_ID(pps->pps_id)
509 | VEPU_REG_INTRA_PRED_MODE(h264_prev_mode_favor[hw_mbrc->qp_init])
510 | VEPU_REG_FRAME_NUM(slice->frame_num);
511 H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL1, val);
512
513 {
514 RK_U8 dmv_penalty[128] = {0};
515 RK_U8 dmv_qpel_penalty[128] = {0};
516
517 for (i = 0; i < 128; i++) {
518 dmv_penalty[i] = i;
519 dmv_qpel_penalty[i] = MPP_MIN(255, exp_golomb_signed(i));
520 }
521
522 for (i = 0; i < 128; i += 4) {
523 val = VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i], 3);
524 val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 1], 2);
525 val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 2], 1);
526 val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 3], 0);
527 H264E_HAL_SET_REG(reg, VEPU_REG_DMV_PENALTY_TBL(i / 4), val);
528
529 val = VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(dmv_qpel_penalty[i], 3);
530 val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(dmv_qpel_penalty[i + 1], 2);
531 val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(dmv_qpel_penalty[i + 2], 1);
532 val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(dmv_qpel_penalty[i + 3], 0);
533 H264E_HAL_SET_REG(reg, VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i / 4), val);
534 }
535 }
536
537 /* set buffers addr */
538 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_LUMA, hw_addr->orig[0]);
539 if (hw_offset->offset_byte[0])
540 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_LUMA >> 2,
541 hw_offset->offset_byte[0]);
542 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_CB, hw_addr->orig[1]);
543 if (hw_offset->offset_byte[1])
544 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CB >> 2,
545 hw_offset->offset_byte[1]);
546 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_CR, hw_addr->orig[2]);
547 if (hw_offset->offset_byte[2])
548 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CR >> 2,
549 hw_offset->offset_byte[2]);
550
551 MppBuffer nal_size_table = h264e_vepu_buf_get_nal_size_table(hw_bufs);
552 RK_S32 nal_size_table_fd = nal_size_table ? mpp_buffer_get_fd(nal_size_table) : 0;
553
554 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_CTRL, nal_size_table_fd);
555
556 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REC_LUMA, hw_addr->recn[0]);
557 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REC_CHROMA, hw_addr->recn[1]);
558 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_REC_CHROMA >> 2, hw_bufs->yuv_size);
559 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REF_LUMA, hw_addr->refr[0]);
560 H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REF_CHROMA, hw_addr->refr[1]);
561 mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_REF_CHROMA >> 2, hw_bufs->yuv_size);
562
563 /* set important encode mode info */
564 val = VEPU_REG_INTERRUPT_TIMEOUT_EN
565 | VEPU_REG_SIZE_TABLE_PRESENT
566 | VEPU_REG_MB_HEIGHT(mb_h)
567 | VEPU_REG_MB_WIDTH(mb_w)
568 | VEPU_REG_PIC_TYPE(slice->idr_flag)
569 | VEPU_REG_ENCODE_FORMAT(3)
570 | VEPU_REG_ENCODE_ENABLE;
571 H264E_HAL_SET_REG(reg, VEPU_REG_ENCODE_CTRL, val);
572
573 ctx->frame_cnt++;
574
575 hal_h264e_dbg_func("leave %p\n", hal);
576 return MPP_OK;
577 }
578
hal_h264e_vepu1_start_v2(void * hal,HalEncTask * task)579 static MPP_RET hal_h264e_vepu1_start_v2(void *hal, HalEncTask *task)
580 {
581 MPP_RET ret = MPP_NOK;
582 HalH264eVepu1Ctx *ctx = (HalH264eVepu1Ctx *)hal;
583 (void)task;
584
585 hal_h264e_dbg_func("enter %p\n", hal);
586
587 if (ctx->dev) {
588 MppDevRegWrCfg wr_cfg;
589 MppDevRegRdCfg rd_cfg;
590 RK_U32 reg_size = sizeof(ctx->regs_set);
591
592 do {
593 wr_cfg.reg = &ctx->regs_set;
594 wr_cfg.size = reg_size;
595 wr_cfg.offset = 0;
596
597 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
598 if (ret) {
599 mpp_err_f("set register write failed %d\n", ret);
600 break;
601 }
602
603 rd_cfg.reg = &ctx->regs_get;
604 rd_cfg.size = reg_size;
605 rd_cfg.offset = 0;
606
607 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
608 if (ret) {
609 mpp_err_f("set register read failed %d\n", ret);
610 break;
611 }
612
613 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
614 if (ret) {
615 mpp_err_f("send cmd failed %d\n", ret);
616 break;
617 }
618 } while (0);
619 } else
620 mpp_err("invalid NULL device ctx\n");
621
622 hal_h264e_dbg_func("leave %p\n", hal);
623
624 return ret;
625 }
626
h264e_vepu1_get_mbrc(HalH264eVepuMbRc * mb_rc,H264eVpu1RegSet * reg)627 static void h264e_vepu1_get_mbrc(HalH264eVepuMbRc *mb_rc, H264eVpu1RegSet *reg)
628 {
629 RK_S32 i = 0;
630 RK_U32 cpt_prev = 0;
631 RK_U32 overflow = 0;
632 RK_U32 cpt_idx = VEPU_REG_CHECKPOINT(0) / 4;
633 RK_U32 *reg_val = reg->val;
634
635 mb_rc->hw_status = reg_val[VEPU_REG_INTERRUPT / 4];
636 mb_rc->out_strm_size = reg_val[VEPU_REG_STR_BUF_LIMIT / 4] / 8 - mb_rc->hdr_free_size;
637 mb_rc->qp_sum = VEPU_REG_QP_SUM(reg_val[VEPU_REG_MAD_CTRL / 4]);
638 mb_rc->less_mad_count = VEPU_REG_MB_CNT_SET(reg_val[VEPU_REG_MB_CTRL / 4]);
639 mb_rc->rlc_count = VEPU_REG_RLC_SUM_OUT(reg_val[VEPU_REG_RLC_CTRL / 4]);
640
641 for (i = 0; i < VEPU_CHECK_POINTS_MAX; i++) {
642 RK_U32 cpt = VEPU_REG_CHECKPOINT_RESULT(reg_val[cpt_idx]);
643
644 if (cpt < cpt_prev)
645 overflow += (1 << 21);
646
647 cpt_prev = cpt;
648 mb_rc->cp_usage[i] = cpt + overflow;
649 cpt_idx += (i & 1);
650 }
651 }
652
hal_h264e_vepu1_wait_v2(void * hal,HalEncTask * task)653 static MPP_RET hal_h264e_vepu1_wait_v2(void *hal, HalEncTask *task)
654 {
655 HalH264eVepu1Ctx *ctx = (HalH264eVepu1Ctx *)hal;
656 HalH264eVepuMbRc *hw_mbrc = &ctx->hw_mbrc;
657 H264NaluType type = task->rc_task->frm.is_idr ? H264_NALU_TYPE_IDR : H264_NALU_TYPE_SLICE;
658 MppPacket pkt = task->packet;
659 RK_S32 offset = mpp_packet_get_length(pkt);
660 MPP_RET ret = MPP_NOK;
661
662 hal_h264e_dbg_func("enter %p\n", hal);
663
664 if (ctx->dev) {
665 ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
666 if (ret)
667 mpp_err_f("poll cmd failed %d\n", ret);
668 } else {
669 mpp_err("invalid NULL device ctx\n");
670 return ret;
671 }
672
673 h264e_vepu1_get_mbrc(hw_mbrc, &ctx->regs_get);
674 h264e_vepu_mbrc_update(ctx->rc_ctx, hw_mbrc);
675
676 mpp_packet_add_segment_info(pkt, type, offset, hw_mbrc->out_strm_size);
677
678 {
679 HalH264eVepuStreamAmend *amend = &ctx->amend;
680
681 if (amend->enable) {
682 amend->old_length = hw_mbrc->out_strm_size;
683 h264e_vepu_stream_amend_proc(amend, &ctx->cfg->h264.hw_cfg);
684 ctx->hw_mbrc.out_strm_size = amend->new_length;
685 } else if (amend->prefix) {
686 /* check prefix value */
687 amend->old_length = hw_mbrc->out_strm_size;
688 h264e_vepu_stream_amend_sync_ref_idc(amend);
689 }
690 }
691
692 task->hw_length += ctx->hw_mbrc.out_strm_size;
693
694 hal_h264e_dbg_func("leave %p\n", hal);
695
696 return MPP_OK;
697 }
698
hal_h264e_vepu1_ret_task_v2(void * hal,HalEncTask * task)699 static MPP_RET hal_h264e_vepu1_ret_task_v2(void *hal, HalEncTask *task)
700 {
701 HalH264eVepu1Ctx *ctx = (HalH264eVepu1Ctx *)hal;
702 EncRcTaskInfo *rc_info = &task->rc_task->info;
703 RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
704 RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
705 RK_U32 mbs = mb_w * mb_h;
706
707 hal_h264e_dbg_func("enter %p\n", hal);
708
709 task->length += task->hw_length;
710
711 rc_info->bit_real = task->hw_length * 8;
712 rc_info->quality_real = ctx->hw_mbrc.qp_sum / mbs;
713
714 hal_h264e_dbg_rc("real bit %d quality %d\n", rc_info->bit_real, rc_info->quality_real);
715
716 task->hal_ret.data = rc_info;
717 task->hal_ret.number = 1;
718
719 hal_h264e_dbg_func("leave %p\n", hal);
720
721 return MPP_OK;
722 }
723
724 const MppEncHalApi hal_h264e_vepu1 = {
725 .name = "hal_h264e_vepu1",
726 .coding = MPP_VIDEO_CodingAVC,
727 .ctx_size = sizeof(HalH264eVepu1Ctx),
728 .flag = 0,
729 .init = hal_h264e_vepu1_init_v2,
730 .deinit = hal_h264e_vepu1_deinit_v2,
731 .prepare = NULL,
732 .get_task = hal_h264e_vepu1_get_task_v2,
733 .gen_regs = hal_h264e_vepu1_gen_regs_v2,
734 .start = hal_h264e_vepu1_start_v2,
735 .wait = hal_h264e_vepu1_wait_v2,
736 .part_start = NULL,
737 .part_wait = NULL,
738 .ret_task = hal_h264e_vepu1_ret_task_v2,
739 };
740