1*437bfbebSnyanmisaka /* 2*437bfbebSnyanmisaka * Copyright 2022 Rockchip Electronics Co. LTD 3*437bfbebSnyanmisaka * 4*437bfbebSnyanmisaka * Licensed under the Apache License, Version 2.0 (the "License"); 5*437bfbebSnyanmisaka * you may not use this file except in compliance with the License. 6*437bfbebSnyanmisaka * You may obtain a copy of the License at 7*437bfbebSnyanmisaka * 8*437bfbebSnyanmisaka * http://www.apache.org/licenses/LICENSE-2.0 9*437bfbebSnyanmisaka * 10*437bfbebSnyanmisaka * Unless required by applicable law or agreed to in writing, software 11*437bfbebSnyanmisaka * distributed under the License is distributed on an "AS IS" BASIS, 12*437bfbebSnyanmisaka * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13*437bfbebSnyanmisaka * See the License for the specific language governing permissions and 14*437bfbebSnyanmisaka * limitations under the License. 15*437bfbebSnyanmisaka */ 16*437bfbebSnyanmisaka 17*437bfbebSnyanmisaka #ifndef __VEPU5XX_COMMON_H__ 18*437bfbebSnyanmisaka #define __VEPU5XX_COMMON_H__ 19*437bfbebSnyanmisaka 20*437bfbebSnyanmisaka #include "rk_venc_cmd.h" 21*437bfbebSnyanmisaka #include "mpp_device.h" 22*437bfbebSnyanmisaka 23*437bfbebSnyanmisaka /* 24*437bfbebSnyanmisaka * Invert color threshold is for the absolute difference between background 25*437bfbebSnyanmisaka * and foregroud color. 26*437bfbebSnyanmisaka * If background color and foregroud color are close enough then trigger the 27*437bfbebSnyanmisaka * invert color process. 28*437bfbebSnyanmisaka */ 29*437bfbebSnyanmisaka #define ENC_DEFAULT_OSD_INV_THR 15 30*437bfbebSnyanmisaka #define SET_OSD_INV_THR(index, reg, region)\ 31*437bfbebSnyanmisaka if(region[index].inverse) \ 32*437bfbebSnyanmisaka reg.osd_ithd_r##index = ENC_DEFAULT_OSD_INV_THR; 33*437bfbebSnyanmisaka 34*437bfbebSnyanmisaka typedef enum Vepu5xxOsdPltType_e { 35*437bfbebSnyanmisaka VEPU5xx_OSD_PLT_TYPE_USERDEF = 0, 36*437bfbebSnyanmisaka VEPU5xx_OSD_PLT_TYPE_DEFAULT = 1, 37*437bfbebSnyanmisaka } Vepu5xxOsdPltType; 38*437bfbebSnyanmisaka 39*437bfbebSnyanmisaka typedef enum VepuFmt_e { 40*437bfbebSnyanmisaka VEPU5xx_FMT_BGRA8888, // 0 41*437bfbebSnyanmisaka VEPU5xx_FMT_BGR888, // 1 42*437bfbebSnyanmisaka VEPU5xx_FMT_BGR565, // 2 43*437bfbebSnyanmisaka VEPU5xx_FMT_ARGB1555, // 3 44*437bfbebSnyanmisaka VEPU5xx_FMT_YUV422SP, // 4 45*437bfbebSnyanmisaka VEPU5xx_FMT_YUV422P, // 5 46*437bfbebSnyanmisaka VEPU5xx_FMT_YUV420SP, // 6 47*437bfbebSnyanmisaka VEPU5xx_FMT_YUV420P, // 7 48*437bfbebSnyanmisaka VEPU5xx_FMT_YUYV422, // 8 49*437bfbebSnyanmisaka VEPU5xx_FMT_UYVY422, // 9 50*437bfbebSnyanmisaka VEPU5xx_FMT_YUV400, // 10 51*437bfbebSnyanmisaka VEPU5xx_FMT_AYUV2BPP, // 11 52*437bfbebSnyanmisaka VEPU5xx_FMT_YUV444SP, // 12 53*437bfbebSnyanmisaka VEPU5xx_FMT_YUV444P, // 13 54*437bfbebSnyanmisaka VEPU5xx_FMT_ARGB4444, // 14 55*437bfbebSnyanmisaka VEPU5xx_FMT_AYUV1BPP, // 15 56*437bfbebSnyanmisaka VEPU5xx_FMT_BUTT, // 16 57*437bfbebSnyanmisaka } VepuFmt; 58*437bfbebSnyanmisaka 59*437bfbebSnyanmisaka typedef struct VepuFmtCfg_t { 60*437bfbebSnyanmisaka VepuFmt format; 61*437bfbebSnyanmisaka RK_U32 alpha_swap; 62*437bfbebSnyanmisaka RK_U32 rbuv_swap; 63*437bfbebSnyanmisaka RK_U32 src_range; 64*437bfbebSnyanmisaka RK_U32 src_endian; 65*437bfbebSnyanmisaka const RK_S32 *weight; 66*437bfbebSnyanmisaka const RK_S32 *offset; 67*437bfbebSnyanmisaka } VepuFmtCfg; 68*437bfbebSnyanmisaka 69*437bfbebSnyanmisaka typedef struct Vepu5xxOsdCfg_t { 70*437bfbebSnyanmisaka void *reg_base; 71*437bfbebSnyanmisaka MppDev dev; 72*437bfbebSnyanmisaka MppDevRegOffCfgs *reg_cfg; 73*437bfbebSnyanmisaka MppEncOSDPltCfg *plt_cfg; 74*437bfbebSnyanmisaka MppEncOSDData *osd_data; 75*437bfbebSnyanmisaka MppEncOSDData2 *osd_data2; 76*437bfbebSnyanmisaka } Vepu5xxOsdCfg; 77*437bfbebSnyanmisaka 78*437bfbebSnyanmisaka typedef struct VepuRgb2YuvCoeffs_t { 79*437bfbebSnyanmisaka RK_S16 r_coeff; 80*437bfbebSnyanmisaka RK_S16 g_coeff; 81*437bfbebSnyanmisaka RK_S16 b_coeff; 82*437bfbebSnyanmisaka RK_S16 offset; 83*437bfbebSnyanmisaka } VepuRgb2YuvCoeffs; 84*437bfbebSnyanmisaka 85*437bfbebSnyanmisaka /* formula: y(r, g, b) = (r_coeff x r + g_coeff x g + b_coeff x b + 128) >> 8 + offset */ 86*437bfbebSnyanmisaka typedef struct VepuRgb2YuvCfg_t { 87*437bfbebSnyanmisaka /* YUV colorspace type */ 88*437bfbebSnyanmisaka MppFrameColorSpace color; 89*437bfbebSnyanmisaka /* MPEG vs JPEG YUV range */ 90*437bfbebSnyanmisaka MppFrameColorRange dst_range; 91*437bfbebSnyanmisaka /* coeffs of rgb 2 yuv */ 92*437bfbebSnyanmisaka VepuRgb2YuvCoeffs _2y; 93*437bfbebSnyanmisaka VepuRgb2YuvCoeffs _2u; 94*437bfbebSnyanmisaka VepuRgb2YuvCoeffs _2v; 95*437bfbebSnyanmisaka } VepuRgb2YuvCfg; 96*437bfbebSnyanmisaka 97*437bfbebSnyanmisaka /** 98*437bfbebSnyanmisaka * @brief Get rgb2yuv cfg by color range and color space. If not found, return default cfg. 99*437bfbebSnyanmisaka * default cfg's yuv range - limit. 100*437bfbebSnyanmisaka * default cfg's color space - BT.601. 101*437bfbebSnyanmisaka */ 102*437bfbebSnyanmisaka const VepuRgb2YuvCfg* get_rgb2yuv_cfg(MppFrameColorRange range, MppFrameColorSpace color); 103*437bfbebSnyanmisaka 104*437bfbebSnyanmisaka MPP_RET copy2osd2(MppEncOSDData2* dst, MppEncOSDData *src1, MppEncOSDData2 *src2); 105*437bfbebSnyanmisaka 106*437bfbebSnyanmisaka MPP_RET vepu5xx_set_fmt(VepuFmtCfg *cfg, MppFrameFormat format); 107*437bfbebSnyanmisaka 108*437bfbebSnyanmisaka extern const RK_U32 vepu580_540_h264_flat_scl_tab[576]; 109*437bfbebSnyanmisaka 110*437bfbebSnyanmisaka extern const RK_U32 klut_weight[24]; 111*437bfbebSnyanmisaka extern const RK_U32 lamd_satd_qp[52]; 112*437bfbebSnyanmisaka extern const RK_U32 lamd_moda_qp[52]; 113*437bfbebSnyanmisaka extern const RK_U32 lamd_modb_qp[52]; 114*437bfbebSnyanmisaka extern const RK_U32 lamd_satd_qp_510[52]; 115*437bfbebSnyanmisaka 116*437bfbebSnyanmisaka #endif /* __VEPU5XX_COMMON_H__ */