1 /*
2 * Copyright 2021 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "vepu540c_common"
18
19 #include <linux/string.h>
20
21 #include "mpp_log.h"
22 #include "mpp_debug.h"
23 #include "mpp_mem.h"
24 #include "mpp_common.h"
25 #include "jpege_syntax.h"
26 #include "vepu5xx_common.h"
27 #include "vepu540c_common.h"
28 #include "hal_enc_task.h"
29 #include "mpp_frame_impl.h"
30 #include "mpp_packet.h"
31
vepu540c_set_roi(void * roi_reg_base,MppEncROICfg * roi,RK_S32 w,RK_S32 h)32 MPP_RET vepu540c_set_roi(void *roi_reg_base, MppEncROICfg * roi,
33 RK_S32 w, RK_S32 h)
34 {
35 MppEncROIRegion *region = roi->regions;
36 Vepu540cRoiCfg *roi_cfg = (Vepu540cRoiCfg *)roi_reg_base;
37 Vepu540cRoiRegion *reg_regions = &roi_cfg->regions[0];
38 MPP_RET ret = MPP_NOK;
39 RK_S32 i = 0;
40 memset(reg_regions, 0, sizeof(Vepu540cRoiRegion) * 8);
41 if (NULL == roi_cfg || NULL == roi) {
42 mpp_err_f("invalid buf %p roi %p\n", roi_cfg, roi);
43 goto DONE;
44 }
45
46 if (roi->number > VEPU540C_MAX_ROI_NUM) {
47 mpp_err_f("invalid region number %d\n", roi->number);
48 goto DONE;
49 }
50
51 /* check region config */
52 ret = MPP_OK;
53 for (i = 0; i < (RK_S32) roi->number; i++, region++) {
54 if (region->x + region->w > w || region->y + region->h > h)
55 ret = MPP_NOK;
56
57 if (region->intra > 1
58 || region->qp_area_idx >= VEPU540C_MAX_ROI_NUM
59 || region->area_map_en > 1 || region->abs_qp_en > 1)
60 ret = MPP_NOK;
61
62 if ((region->abs_qp_en && region->quality > 51) ||
63 (!region->abs_qp_en
64 && (region->quality > 51 || region->quality < -51)))
65 ret = MPP_NOK;
66
67 if (ret) {
68 mpp_err_f("region %d invalid param:\n", i);
69 mpp_err_f("position [%d:%d:%d:%d] vs [%d:%d]\n",
70 region->x, region->y, region->w, region->h, w,
71 h);
72 mpp_err_f("force intra %d qp area index %d\n",
73 region->intra, region->qp_area_idx);
74 mpp_err_f("abs qp mode %d value %d\n",
75 region->abs_qp_en, region->quality);
76 goto DONE;
77 }
78 reg_regions->roi_pos_lt.roi_lt_x = MPP_ALIGN(region->x, 16) >> 4;
79 reg_regions->roi_pos_lt.roi_lt_y = MPP_ALIGN(region->y, 16) >> 4;
80 reg_regions->roi_pos_rb.roi_rb_x = MPP_ALIGN(region->x + region->w, 16) >> 4;
81 reg_regions->roi_pos_rb.roi_rb_y = MPP_ALIGN(region->y + region->h, 16) >> 4;
82 reg_regions->roi_base.roi_qp_value = region->quality;
83 reg_regions->roi_base.roi_qp_adj_mode = region->abs_qp_en;
84 reg_regions->roi_base.roi_en = 1;
85 reg_regions->roi_base.roi_pri = 0x1f;
86 if (region->intra) {
87 reg_regions->roi_mdc.roi_mdc_intra16 = 1;
88 reg_regions->roi_mdc.roi0_mdc_intra32_hevc = 1;
89 }
90 reg_regions++;
91 }
92
93 DONE:
94 return ret;
95 }
96
vepu540c_jpeg_set_patch_info(MppDev dev,JpegeSyntax * syn,VepuFmt input_fmt,HalEncTask * task)97 static MPP_RET vepu540c_jpeg_set_patch_info(MppDev dev, JpegeSyntax *syn,
98 VepuFmt input_fmt,
99 HalEncTask *task)
100 {
101 RK_U32 hor_stride = syn->hor_stride;
102 RK_U32 ver_stride = syn->ver_stride ? syn->ver_stride : syn->height;
103 RK_U32 frame_size = hor_stride * ver_stride;
104 RK_U32 u_offset = 0, v_offset = 0;
105 MPP_RET ret = MPP_OK;
106
107 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(task->frame))) {
108 u_offset = mpp_frame_get_fbc_offset(task->frame);
109 v_offset = 0;
110 mpp_log("fbc case u_offset = %d", u_offset);
111 } else {
112 switch (input_fmt) {
113 case VEPU5xx_FMT_YUV420P: {
114 u_offset = frame_size;
115 v_offset = frame_size * 5 / 4;
116 } break;
117 case VEPU5xx_FMT_YUV420SP:
118 case VEPU5xx_FMT_YUV422SP: {
119 u_offset = frame_size;
120 v_offset = frame_size;
121 } break;
122 case VEPU5xx_FMT_YUV422P: {
123 u_offset = frame_size;
124 v_offset = frame_size * 3 / 2;
125 } break;
126 case VEPU5xx_FMT_YUYV422:
127 case VEPU5xx_FMT_UYVY422: {
128 u_offset = 0;
129 v_offset = 0;
130 } break;
131 case VEPU5xx_FMT_BGR565:
132 case VEPU5xx_FMT_BGR888:
133 case VEPU5xx_FMT_BGRA8888: {
134 u_offset = 0;
135 v_offset = 0;
136 } break;
137 default: {
138 mpp_err("unknown color space: %d\n", input_fmt);
139 u_offset = frame_size;
140 v_offset = frame_size * 5 / 4;
141 }
142 }
143 }
144
145 /* input cb addr */
146 if (u_offset)
147 mpp_dev_set_reg_offset(dev, 265, u_offset);
148
149 /* input cr addr */
150 if (v_offset)
151 mpp_dev_set_reg_offset(dev, 266, v_offset);
152
153 return ret;
154 }
155
156
vepu540c_set_jpeg_reg(Vepu540cJpegCfg * cfg)157 MPP_RET vepu540c_set_jpeg_reg(Vepu540cJpegCfg *cfg)
158 {
159 HalEncTask *task = ( HalEncTask *)cfg->enc_task;
160 JpegeSyntax *syn = (JpegeSyntax *)task->syntax.data;
161 Vepu540cJpegReg *regs = (Vepu540cJpegReg *)cfg->jpeg_reg_base;
162 VepuFmtCfg *fmt = (VepuFmtCfg *)cfg->input_fmt;
163 RK_U32 pic_width_align8, pic_height_align8;
164 RK_S32 stridey = 0;
165 RK_S32 stridec = 0;
166
167 pic_width_align8 = (syn->width + 7) & (~7);
168 pic_height_align8 = (syn->height + 7) & (~7);
169
170 regs->reg0264_adr_src0 = mpp_buffer_get_fd(task->input);
171 regs->reg0265_adr_src1 = regs->reg0264_adr_src0;
172 regs->reg0266_adr_src2 = regs->reg0264_adr_src0;
173
174 vepu540c_jpeg_set_patch_info(cfg->dev, syn, (VepuFmt)fmt->format, task);
175
176 regs->reg0256_adr_bsbt = mpp_buffer_get_fd(task->output);
177 regs->reg0257_adr_bsbb = regs->reg0256_adr_bsbt;
178 regs->reg0258_adr_bsbs = regs->reg0256_adr_bsbt;
179 regs->reg0259_adr_bsbr = regs->reg0256_adr_bsbt;
180
181 mpp_dev_set_reg_offset(cfg->dev, 258, mpp_packet_get_length(task->packet));
182 mpp_dev_set_reg_offset(cfg->dev, 256, mpp_buffer_get_size(task->output));
183
184 regs->reg0272_enc_rsl.pic_wd8_m1 = pic_width_align8 / 8 - 1;
185 regs->reg0273_src_fill.pic_wfill = (syn->width & 0x7)
186 ? (8 - (syn->width & 0x7)) : 0;
187 regs->reg0272_enc_rsl.pic_hd8_m1 = pic_height_align8 / 8 - 1;
188 regs->reg0273_src_fill.pic_hfill = (syn->height & 0x7)
189 ? (8 - (syn->height & 0x7)) : 0;
190
191 regs->reg0274_src_fmt.src_cfmt = fmt->format;
192 regs->reg0274_src_fmt.alpha_swap = fmt->alpha_swap;
193 regs->reg0274_src_fmt.rbuv_swap = fmt->rbuv_swap;
194 regs->reg0274_src_fmt.src_range_trns_en = 0;
195 regs->reg0274_src_fmt.src_range_trns_sel = 0;
196 regs->reg0274_src_fmt.chroma_ds_mode = 0;
197 regs->reg0274_src_fmt.out_fmt = 1;
198
199 regs->reg0279_src_proc.src_mirr = 0 ;//prep_cfg->mirroring > 0;
200 regs->reg0279_src_proc.src_rot = syn->rotation;
201
202 if (syn->hor_stride) {
203 stridey = syn->hor_stride;
204 } else {
205 if (regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_BGRA8888)
206 stridey = syn->width * 4;
207 else if (regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_BGR888)
208 stridey = syn->width * 3;
209 else if (regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_BGR565 ||
210 regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_YUYV422 ||
211 regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_UYVY422)
212 stridey = syn->width * 2;
213 }
214
215 stridec = (regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_YUV422SP ||
216 regs->reg0274_src_fmt.src_cfmt == VEPU5xx_FMT_YUV420SP) ?
217 stridey : stridey / 2;
218
219 if (regs->reg0274_src_fmt.src_cfmt < VEPU5xx_FMT_ARGB1555) {
220 regs->reg0275_src_udfy.csc_wgt_r2y = 66;
221 regs->reg0275_src_udfy.csc_wgt_g2y = 129;
222 regs->reg0275_src_udfy.csc_wgt_b2y = 25;
223
224 regs->reg0276_src_udfu.csc_wgt_r2u = -38;
225 regs->reg0276_src_udfu.csc_wgt_g2u = -74;
226 regs->reg0276_src_udfu.csc_wgt_b2u = 112;
227
228 regs->reg0277_src_udfv.csc_wgt_r2v = 112;
229 regs->reg0277_src_udfv.csc_wgt_g2v = -94;
230 regs->reg0277_src_udfv.csc_wgt_b2v = -18;
231
232 regs->reg0278_src_udfo.csc_ofst_y = 16;
233 regs->reg0278_src_udfo.csc_ofst_u = 128;
234 regs->reg0278_src_udfo.csc_ofst_v = 128;
235 }
236 regs->reg0281_src_strd0.src_strd0 = stridey;
237 regs->reg0282_src_strd1.src_strd1 = stridec;
238 regs->reg0280_pic_ofst.pic_ofst_y = mpp_frame_get_offset_y(task->frame);
239 regs->reg0280_pic_ofst.pic_ofst_x = mpp_frame_get_offset_x(task->frame);
240 //to be done
241
242 // no 0283 ?
243 // regs->reg0283_src_flt.pp_corner_filter_strength = 0;
244 // regs->reg0283_src_flt.pp_edge_filter_strength = 0;
245 // regs->reg0283_src_flt.pp_internal_filter_strength = 0;
246
247 regs->reg0284_y_cfg.bias_y = 0;
248 regs->reg0285_u_cfg.bias_u = 0;
249 regs->reg0286_v_cfg.bias_v = 0;
250
251 regs->reg0287_base_cfg.jpeg_ri = 0;
252 regs->reg0287_base_cfg.jpeg_out_mode = 0;
253 regs->reg0287_base_cfg.jpeg_start_rst_m = 0;
254 regs->reg0287_base_cfg.jpeg_pic_last_ecs = 1;
255 regs->reg0287_base_cfg.jpeg_slen_fifo = 0;
256 regs->reg0287_base_cfg.jpeg_stnd = 1; //enable
257
258 regs->reg0288_uvc_cfg.uvc_partition0_len = 0;
259 regs->reg0288_uvc_cfg.uvc_partition_len = 0;
260 regs->reg0288_uvc_cfg.uvc_skip_len = 0;
261 return MPP_OK;
262 }
263