xref: /rockchip-linux_mpp/mpp/hal/rkenc/common/rkv_enc_def.h (revision 437bfbeb9567cca9cd9080e3f6954aa9d6a94f18)
1*437bfbebSnyanmisaka /*
2*437bfbebSnyanmisaka  * Copyright 2015 Rockchip Electronics Co. LTD
3*437bfbebSnyanmisaka  *
4*437bfbebSnyanmisaka  * Licensed under the Apache License, Version 2.0 (the "License");
5*437bfbebSnyanmisaka  * you may not use this file except in compliance with the License.
6*437bfbebSnyanmisaka  * You may obtain a copy of the License at
7*437bfbebSnyanmisaka  *
8*437bfbebSnyanmisaka  *      http://www.apache.org/licenses/LICENSE-2.0
9*437bfbebSnyanmisaka  *
10*437bfbebSnyanmisaka  * Unless required by applicable law or agreed to in writing, software
11*437bfbebSnyanmisaka  * distributed under the License is distributed on an "AS IS" BASIS,
12*437bfbebSnyanmisaka  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13*437bfbebSnyanmisaka  * See the License for the specific language governing permissions and
14*437bfbebSnyanmisaka  * limitations under the License.
15*437bfbebSnyanmisaka  */
16*437bfbebSnyanmisaka #ifndef __RKV_ENC_DEF_H__
17*437bfbebSnyanmisaka #define __RKV_ENC_DEF_H__
18*437bfbebSnyanmisaka 
19*437bfbebSnyanmisaka #define RKV_ENC_INT_ONE_FRAME_FINISH    0x00000001
20*437bfbebSnyanmisaka #define RKV_ENC_INT_LINKTABLE_FINISH    0x00000002
21*437bfbebSnyanmisaka #define RKV_ENC_INT_SAFE_CLEAR_FINISH   0x00000004
22*437bfbebSnyanmisaka #define RKV_ENC_INT_ONE_SLICE_FINISH    0x00000008
23*437bfbebSnyanmisaka #define RKV_ENC_INT_BIT_STREAM_OVERFLOW 0x00000010
24*437bfbebSnyanmisaka #define RKV_ENC_INT_BUS_WRITE_FULL      0x00000020
25*437bfbebSnyanmisaka #define RKV_ENC_INT_BUS_WRITE_ERROR     0x00000040
26*437bfbebSnyanmisaka #define RKV_ENC_INT_BUS_READ_ERROR      0x00000080
27*437bfbebSnyanmisaka #define RKV_ENC_INT_TIMEOUT_ERROR       0x00000100
28*437bfbebSnyanmisaka 
29*437bfbebSnyanmisaka #define RKVENC_CODING_TYPE_AUTO          0x0000  /* Let enc choose the right type */
30*437bfbebSnyanmisaka #define RKVENC_CODING_TYPE_IDR           0x0001
31*437bfbebSnyanmisaka #define RKVENC_CODING_TYPE_I             0x0002
32*437bfbebSnyanmisaka #define RKVENC_CODING_TYPE_P             0x0003
33*437bfbebSnyanmisaka #define RKVENC_CODING_TYPE_BREF          0x0004  /* Non-disposable B-frame */
34*437bfbebSnyanmisaka #define RKVENC_CODING_TYPE_B             0x0005
35*437bfbebSnyanmisaka #define RKVENC_CODING_TYPE_KEYFRAME      0x0006  /* IDR or I depending on b_open_gop option */
36*437bfbebSnyanmisaka 
37*437bfbebSnyanmisaka #define RKVE_IOC_CUSTOM_BASE           0x1000
38*437bfbebSnyanmisaka #define RKVE_IOC_SET_OSD_PLT           (RKVE_IOC_CUSTOM_BASE + 1)
39*437bfbebSnyanmisaka #define RKVE_IOC_SET_L2_REG            (RKVE_IOC_CUSTOM_BASE + 2)
40*437bfbebSnyanmisaka 
41*437bfbebSnyanmisaka 
42*437bfbebSnyanmisaka #define RKVE_CSP2_MASK             0x00ff  /* */
43*437bfbebSnyanmisaka #define RKVE_CSP2_NONE             0x0000  /* Invalid mode     */
44*437bfbebSnyanmisaka #define RKVE_CSP2_I420             0x0001  /* yuv 4:2:0 planar */
45*437bfbebSnyanmisaka #define RKVE_CSP2_YV12             0x0002  /* yvu 4:2:0 planar */
46*437bfbebSnyanmisaka #define RKVE_CSP2_NV12             0x0003  /* yuv 4:2:0, with one y plane and one packed u+v */
47*437bfbebSnyanmisaka #define RKVE_CSP2_I422             0x0004  /* yuv 4:2:2 planar */
48*437bfbebSnyanmisaka #define RKVE_CSP2_YV16             0x0005  /* yvu 4:2:2 planar */
49*437bfbebSnyanmisaka #define RKVE_CSP2_NV16             0x0006  /* yuv 4:2:2, with one y plane and one packed u+v */
50*437bfbebSnyanmisaka #define RKVE_CSP2_V210             0x0007  /* 10-bit yuv 4:2:2 packed in 32 */
51*437bfbebSnyanmisaka #define RKVE_CSP2_I444             0x0008  /* yuv 4:4:4 planar */
52*437bfbebSnyanmisaka #define RKVE_CSP2_YV24             0x0009  /* yvu 4:4:4 planar */
53*437bfbebSnyanmisaka #define RKVE_CSP2_BGR              0x000a  /* packed bgr 24bits   */
54*437bfbebSnyanmisaka #define RKVE_CSP2_BGRA             0x000b  /* packed bgr 32bits   */
55*437bfbebSnyanmisaka #define RKVE_CSP2_RGB              0x000c  /* packed rgb 24bits   */
56*437bfbebSnyanmisaka #define RKVE_CSP2_MAX              0x000d  /* end of list */
57*437bfbebSnyanmisaka #define RKVE_CSP2_VFLIP            0x1000  /* the csp is vertically flipped */
58*437bfbebSnyanmisaka #define RKVE_CSP2_HIGH_DEPTH       0x2000  /* the csp has a depth of 16 bits per pixel component */
59*437bfbebSnyanmisaka 
60*437bfbebSnyanmisaka #define RKVE_MB_RC_ONLY_QUALITY    0
61*437bfbebSnyanmisaka #define RKVE_MB_RC_MORE_QUALITY    1
62*437bfbebSnyanmisaka #define RKVE_MB_RC_BALANCE         2
63*437bfbebSnyanmisaka #define RKVE_MB_RC_MORE_BITRATE    3
64*437bfbebSnyanmisaka #define RKVE_MB_RC_ONLY_BITRATE    4
65*437bfbebSnyanmisaka #define RKVE_MB_RC_WIDE_RANGE      5
66*437bfbebSnyanmisaka #define RKVE_MB_RC_ONLY_AQ         6
67*437bfbebSnyanmisaka #define RKVE_MB_RC_M_NUM           7
68*437bfbebSnyanmisaka 
69*437bfbebSnyanmisaka typedef enum RkveCsp_e {
70*437bfbebSnyanmisaka     RKVE_CSP_BGRA8888,         // 0
71*437bfbebSnyanmisaka     RKVE_CSP_BGR888,           // 1
72*437bfbebSnyanmisaka     RKVE_CSP_BGR565,           // 2
73*437bfbebSnyanmisaka     RKVE_CSP_NONE,             // 3
74*437bfbebSnyanmisaka     RKVE_CSP_YUV422SP,         // 4
75*437bfbebSnyanmisaka     RKVE_CSP_YUV422P,          // 5
76*437bfbebSnyanmisaka     RKVE_CSP_YUV420SP,         // 6
77*437bfbebSnyanmisaka     RKVE_CSP_YUV420P,          // 7
78*437bfbebSnyanmisaka     RKVE_CSP_YUYV422,          // 8
79*437bfbebSnyanmisaka     RKVE_CSP_UYVY422,          // 9
80*437bfbebSnyanmisaka     RKVE_CSP_BUTT,             // 10
81*437bfbebSnyanmisaka } RkveCsp;
82*437bfbebSnyanmisaka 
83*437bfbebSnyanmisaka typedef enum enc_hal_rkv_buf_grp_t {
84*437bfbebSnyanmisaka     ENC_HAL_RKV_BUF_GRP_PP,
85*437bfbebSnyanmisaka     ENC_HAL_RKV_BUF_GRP_DSP,
86*437bfbebSnyanmisaka     ENC_HAL_RKV_BUF_GRP_MEI,
87*437bfbebSnyanmisaka     ENC_HAL_RKV_BUF_GRP_CMV,
88*437bfbebSnyanmisaka     ENC_HAL_RKV_BUF_GRP_ROI,
89*437bfbebSnyanmisaka     ENC_HAL_RKV_BUF_GRP_REC,
90*437bfbebSnyanmisaka     ENC_HAL_RKV_BUF_GRP_BUTT
91*437bfbebSnyanmisaka } enc_hal_rkv_buf_grp;
92*437bfbebSnyanmisaka 
93*437bfbebSnyanmisaka typedef enum enc_rkv_lnktable_t {
94*437bfbebSnyanmisaka     RKVENC_LINKTABLE_DISABLE = 1,
95*437bfbebSnyanmisaka     RKVENC_LINKTABLE_START,
96*437bfbebSnyanmisaka     RKVENC_LINKTABLE_UPDATE
97*437bfbebSnyanmisaka } enc_rkv_lnk_table;
98*437bfbebSnyanmisaka 
99*437bfbebSnyanmisaka typedef struct {
100*437bfbebSnyanmisaka     RK_U8 qp_y          : 6;
101*437bfbebSnyanmisaka     RK_U8 set_qp_y_en   : 1;
102*437bfbebSnyanmisaka     RK_U8 forbid_inter  : 1;
103*437bfbebSnyanmisaka } RkvRoiCfg;
104*437bfbebSnyanmisaka 
105*437bfbebSnyanmisaka typedef struct {
106*437bfbebSnyanmisaka     RK_U16 forbid_inter    : 1;      /* intra flag for cu 16x16 */
107*437bfbebSnyanmisaka     RK_U16 reserved        : 3;      /* reserved */
108*437bfbebSnyanmisaka     RK_U16 qp_area_idx     : 3;      /* roi range index */
109*437bfbebSnyanmisaka     RK_U16 area_map        : 1;      /* roi en */
110*437bfbebSnyanmisaka     RK_S16 qp_y            : 7;      /* qp_value,  absolute qp or relative qp*/
111*437bfbebSnyanmisaka     RK_U16 set_qp_y        : 1;
112*437bfbebSnyanmisaka } RkvRoiCfg_v2;
113*437bfbebSnyanmisaka 
114*437bfbebSnyanmisaka typedef enum ReOsdPltType_e {
115*437bfbebSnyanmisaka     RKVE_OSD_PLT_TYPE_NONE     = -1,
116*437bfbebSnyanmisaka     RKVE_OSD_PLT_TYPE_USERDEF  = 0,
117*437bfbebSnyanmisaka     RKVE_OSD_PLT_TYPE_DEFAULT  = 1,
118*437bfbebSnyanmisaka } RkveOsdPltType;
119*437bfbebSnyanmisaka 
120*437bfbebSnyanmisaka 
121*437bfbebSnyanmisaka #define RKV_ENC_MODE                  RKVENC_LINKTABLE_DISABLE //2
122*437bfbebSnyanmisaka #define RKVE_LINKTABLE_FRAME_NUM       1 //2
123*437bfbebSnyanmisaka 
124*437bfbebSnyanmisaka #if RKVE_ENC_MODE == RKVENC_LINKTABLE_START
125*437bfbebSnyanmisaka #define RKVE_LINKTABLE_EACH_NUM        RKVE_LINKTABLE_FRAME_NUM
126*437bfbebSnyanmisaka #else
127*437bfbebSnyanmisaka #define RKVE_LINKTABLE_EACH_NUM        1
128*437bfbebSnyanmisaka #endif
129*437bfbebSnyanmisaka #define RKVE_LINKTABLE_MAX_SIZE        256
130*437bfbebSnyanmisaka 
131*437bfbebSnyanmisaka #define RKVE_RC_TEXTURE_THR_SIZE 16
132*437bfbebSnyanmisaka 
133*437bfbebSnyanmisaka #endif
134