1 /*
2 * Copyright 2020 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "hal_vp9d_vdpu34x"
18
19 #include <stdio.h>
20 #include <string.h>
21
22 #include "mpp_env.h"
23 #include "mpp_mem.h"
24 #include "mpp_common.h"
25 #include "mpp_device.h"
26 #include "mpp_hal.h"
27
28 #include "hal_bufs.h"
29 #include "hal_vp9d_debug.h"
30 #include "hal_vp9d_com.h"
31 #include "hal_vp9d_vdpu34x.h"
32 #include "hal_vp9d_ctx.h"
33 #include "vdpu34x_vp9d.h"
34 #include "vp9d_syntax.h"
35
36 #define HW_PROB 1
37 #define VP9_CONTEXT 4
38 #define VP9_CTU_SIZE 64
39 #define PROB_SIZE_ALIGN_TO_4K MPP_ALIGN(PROB_SIZE, SZ_4K)
40 #define COUNT_SIZE_ALIGN_TO_4K MPP_ALIGN(COUNT_SIZE, SZ_4K)
41 #define MAX_SEGMAP_SIZE_ALIGN_TO_4K MPP_ALIGN(MAX_SEGMAP_SIZE, SZ_4K)
42
43 #define VDPU34X_OFFSET_COUNT (PROB_SIZE_ALIGN_TO_4K)
44 #define VDPU34X_PROBE_BUFFER_SIZE (PROB_SIZE_ALIGN_TO_4K + COUNT_SIZE_ALIGN_TO_4K)
45
46 typedef struct Vdpu34xVp9dCtx_t {
47 Vp9dRegBuf g_buf[MAX_GEN_REG];
48 MppBuffer probe_base;
49 MppBuffer seg_base;
50 RK_U32 offset_count;
51 RK_U32 offset_segid_cur;
52 RK_U32 offset_segid_last;
53 MppBuffer prob_default_base;
54 void* hw_regs;
55 RK_S32 mv_base_addr;
56 RK_S32 pre_mv_base_addr;
57 Vp9dLastInfo ls_info;
58 /*
59 * swap between segid_cur_base & segid_last_base
60 * 0 used segid_cur_base as last
61 * 1 used segid_last_base as
62 */
63 RK_U32 last_segid_flag;
64 RK_S32 width;
65 RK_S32 height;
66 /* rcb buffers info */
67 RK_S32 rcb_buf_size;
68 Vdpu34xRcbInfo rcb_info[RCB_BUF_COUNT];
69 MppBuffer rcb_buf;
70 RK_U32 num_row_tiles;
71 RK_U32 bit_depth;
72 /* colmv buffers info */
73 HalBufs cmv_bufs;
74 RK_S32 mv_size;
75 RK_S32 mv_count;
76 RK_U32 prob_ctx_valid[VP9_CONTEXT];
77 MppBuffer prob_loop_base[VP9_CONTEXT];
78 RK_U32 prob_ref_poc[VP9_CONTEXT];
79 RK_U32 col_ref_poc;
80 RK_U32 segid_ref_poc;
81 } Vdpu34xVp9dCtx;
82
hal_vp9d_alloc_res(HalVp9dCtx * hal)83 static MPP_RET hal_vp9d_alloc_res(HalVp9dCtx *hal)
84 {
85 RK_S32 i = 0;
86 RK_S32 ret = 0;
87 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
88 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
89 hw_ctx->offset_count = VDPU34X_OFFSET_COUNT;
90 hw_ctx->offset_segid_cur = 0;
91 hw_ctx->offset_segid_last = MAX_SEGMAP_SIZE_ALIGN_TO_4K;
92 /* alloc common buffer */
93 for (i = 0; i < VP9_CONTEXT; i++) {
94 ret = mpp_buffer_get(p_hal->group, &hw_ctx->prob_loop_base[i], PROB_SIZE);
95 if (ret) {
96 mpp_err("vp9 probe_loop_base get buffer failed\n");
97 return ret;
98 }
99 }
100 ret = mpp_buffer_get(p_hal->group, &hw_ctx->prob_default_base, PROB_SIZE);
101 if (ret) {
102 mpp_err("vp9 probe_default_base get buffer failed\n");
103 return ret;
104 }
105 /* alloc buffer for fast mode or normal */
106 if (p_hal->fast_mode) {
107 for (i = 0; i < MAX_GEN_REG; i++) {
108 hw_ctx->g_buf[i].hw_regs = mpp_calloc_size(void, sizeof(Vdpu34xVp9dRegSet));
109 ret = mpp_buffer_get(p_hal->group, &hw_ctx->g_buf[i].probe_base, VDPU34X_PROBE_BUFFER_SIZE);
110 if (ret) {
111 mpp_err("vp9 probe_base get buffer failed\n");
112 return ret;
113 }
114 }
115 } else {
116 hw_ctx->hw_regs = mpp_calloc_size(void, sizeof(Vdpu34xVp9dRegSet));
117 ret = mpp_buffer_get(p_hal->group, &hw_ctx->probe_base, VDPU34X_PROBE_BUFFER_SIZE);
118 if (ret) {
119 mpp_err("vp9 probe_base get buffer failed\n");
120 return ret;
121 }
122 }
123 ret = mpp_buffer_get(p_hal->group, &hw_ctx->seg_base, MAX_SEGMAP_SIZE_ALIGN_TO_4K * 2);
124 if (ret) {
125 mpp_err("vp9 segid_base get buffer failed\n");
126 return ret;
127 }
128 return MPP_OK;
129 }
130
hal_vp9d_release_res(HalVp9dCtx * hal)131 static MPP_RET hal_vp9d_release_res(HalVp9dCtx *hal)
132 {
133 RK_S32 i = 0;
134 RK_S32 ret = 0;
135 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
136 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
137
138 if (hw_ctx->prob_default_base) {
139 ret = mpp_buffer_put(hw_ctx->prob_default_base);
140 if (ret) {
141 mpp_err("vp9 probe_wr_base put buffer failed\n");
142 return ret;
143 }
144 }
145 for (i = 0; i < VP9_CONTEXT; i++) {
146 if (hw_ctx->prob_loop_base[i]) {
147 ret = mpp_buffer_put(hw_ctx->prob_loop_base[i]);
148 if (ret) {
149 mpp_err("vp9 probe_base put buffer failed\n");
150 return ret;
151 }
152 }
153 }
154 if (p_hal->fast_mode) {
155 for (i = 0; i < MAX_GEN_REG; i++) {
156 if (hw_ctx->g_buf[i].probe_base) {
157 ret = mpp_buffer_put(hw_ctx->g_buf[i].probe_base);
158 if (ret) {
159 mpp_err("vp9 probe_base put buffer failed\n");
160 return ret;
161 }
162 }
163 if (hw_ctx->g_buf[i].hw_regs) {
164 mpp_free(hw_ctx->g_buf[i].hw_regs);
165 hw_ctx->g_buf[i].hw_regs = NULL;
166 }
167 if (hw_ctx->g_buf[i].rcb_buf) {
168 ret = mpp_buffer_put(hw_ctx->g_buf[i].rcb_buf);
169 if (ret) {
170 mpp_err("vp9 rcb_buf[%d] put buffer failed\n", i);
171 return ret;
172 }
173 }
174 }
175 } else {
176 if (hw_ctx->probe_base) {
177 ret = mpp_buffer_put(hw_ctx->probe_base);
178 if (ret) {
179 mpp_err("vp9 probe_base put buffer failed\n");
180 return ret;
181 }
182 }
183
184 if (hw_ctx->hw_regs) {
185 mpp_free(hw_ctx->hw_regs);
186 hw_ctx->hw_regs = NULL;
187 }
188 if (hw_ctx->rcb_buf) {
189 ret = mpp_buffer_put(hw_ctx->rcb_buf);
190 if (ret) {
191 mpp_err("vp9 rcb_buf put buffer failed\n");
192 return ret;
193 }
194 }
195 }
196
197 if (hw_ctx->cmv_bufs) {
198 ret = hal_bufs_deinit(hw_ctx->cmv_bufs);
199 if (ret) {
200 mpp_err("vp9 cmv bufs deinit buffer failed\n");
201 return ret;
202 }
203 }
204
205 if (hw_ctx->seg_base) {
206 ret = mpp_buffer_put(hw_ctx->seg_base);
207 if (ret) {
208 mpp_err("vp9 seg_base put buffer failed\n");
209 return ret;
210 }
211 }
212
213 return MPP_OK;
214 }
215
hal_vp9d_vdpu34x_deinit(void * hal)216 static MPP_RET hal_vp9d_vdpu34x_deinit(void *hal)
217 {
218 MPP_RET ret = MPP_OK;
219 HalVp9dCtx *p_hal = (HalVp9dCtx *)hal;
220
221 hal_vp9d_release_res(p_hal);
222
223 if (p_hal->group) {
224 ret = mpp_buffer_group_put(p_hal->group);
225 if (ret) {
226 mpp_err("vp9d group free buffer failed\n");
227 return ret;
228 }
229 }
230 MPP_FREE(p_hal->hw_ctx);
231 return ret = MPP_OK;
232 }
233
hal_vp9d_vdpu34x_init(void * hal,MppHalCfg * cfg)234 static MPP_RET hal_vp9d_vdpu34x_init(void *hal, MppHalCfg *cfg)
235 {
236 MPP_RET ret = MPP_OK;
237 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
238 MEM_CHECK(ret, p_hal->hw_ctx = mpp_calloc_size(void, sizeof(Vdpu34xVp9dCtx)));
239 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
240
241 hw_ctx->mv_base_addr = -1;
242 hw_ctx->pre_mv_base_addr = -1;
243 mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, vp9_hor_align);
244 mpp_slots_set_prop(p_hal->slots, SLOTS_VER_ALIGN, vp9_ver_align);
245
246 if (p_hal->group == NULL) {
247 ret = mpp_buffer_group_get_internal(&p_hal->group, MPP_BUFFER_TYPE_ION);
248 if (ret) {
249 mpp_err("vp9 mpp_buffer_group_get failed\n");
250 goto __FAILED;
251 }
252 }
253
254 ret = hal_vp9d_alloc_res(p_hal);
255 if (ret) {
256 mpp_err("hal_vp9d_alloc_res failed\n");
257 goto __FAILED;
258 }
259
260 hw_ctx->last_segid_flag = 1;
261
262 if (cfg->hal_fbc_adj_cfg) {
263 cfg->hal_fbc_adj_cfg->func = vdpu34x_afbc_align_calc;
264 cfg->hal_fbc_adj_cfg->expand = 0;
265 }
266
267 return ret;
268 __FAILED:
269 hal_vp9d_vdpu34x_deinit(hal);
270 return ret;
271 }
272
vp9d_refine_rcb_size(Vdpu34xRcbInfo * rcb_info,Vdpu34xVp9dRegSet * vp9_hw_regs,RK_S32 width,RK_S32 height,void * data)273 static void vp9d_refine_rcb_size(Vdpu34xRcbInfo *rcb_info,
274 Vdpu34xVp9dRegSet *vp9_hw_regs,
275 RK_S32 width, RK_S32 height, void* data)
276 {
277 RK_U32 rcb_bits = 0;
278 DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)data;
279 RK_U32 num_tiles = pic_param->log2_tile_rows;
280 RK_U32 bit_depth = pic_param->BitDepthMinus8Luma + 8;
281 RK_U32 ext_align_size = num_tiles * 64 * 8;
282
283 width = MPP_ALIGN(width, VP9_CTU_SIZE);
284 height = MPP_ALIGN(height, VP9_CTU_SIZE);
285 /* RCB_STRMD_ROW */
286 if (width > 4096)
287 rcb_bits = MPP_ALIGN(width, 64) * 232 + ext_align_size;
288 else
289 rcb_bits = 0;
290 rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
291 /* RCB_TRANSD_ROW */
292 if (width > 8192)
293 rcb_bits = (MPP_ALIGN(width - 8192, 4) << 1) + ext_align_size;
294 else
295 rcb_bits = 0;
296 rcb_info[RCB_TRANSD_ROW].size = MPP_RCB_BYTES(rcb_bits);
297 /* RCB_TRANSD_COL */
298 if (height > 8192)
299 rcb_bits = (MPP_ALIGN(height - 8192, 4) << 1) + ext_align_size;
300 else
301 rcb_bits = 0;
302 rcb_info[RCB_TRANSD_COL].size = MPP_RCB_BYTES(rcb_bits);
303 /* RCB_INTER_ROW */
304 rcb_bits = width * 36 + ext_align_size;
305 rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
306 /* RCB_INTER_COL */
307 rcb_info[RCB_INTER_COL].size = 0;
308 /* RCB_INTRA_ROW */
309 rcb_bits = width * 48 + ext_align_size;
310 rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
311 /* RCB_DBLK_ROW */
312 rcb_bits = width * (1 + 16 * bit_depth) + num_tiles * 192 * bit_depth + ext_align_size;
313 rcb_info[RCB_DBLK_ROW].size = MPP_RCB_BYTES(rcb_bits);
314 /* RCB_SAO_ROW */
315 rcb_info[RCB_SAO_ROW].size = 0;
316 /* RCB_FBC_ROW */
317 if (vp9_hw_regs->common.reg012.fbc_e) {
318 rcb_bits = 8 * width * bit_depth + ext_align_size;
319 } else
320 rcb_bits = 0;
321 rcb_info[RCB_FBC_ROW].size = MPP_RCB_BYTES(rcb_bits);
322 /* RCB_FILT_COL */
323 if (vp9_hw_regs->common.reg012.fbc_e) {
324 rcb_bits = height * (4 + 24 * bit_depth);
325 } else
326 rcb_bits = height * (4 + 16 * bit_depth);
327 rcb_bits += ext_align_size;
328 rcb_info[RCB_FILT_COL].size = MPP_RCB_BYTES(rcb_bits);
329 }
330
hal_vp9d_rcb_info_update(void * hal,Vdpu34xVp9dRegSet * hw_regs,void * data)331 static void hal_vp9d_rcb_info_update(void *hal, Vdpu34xVp9dRegSet *hw_regs, void *data)
332 {
333 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
334 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
335 DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)data;
336 RK_U32 num_tiles = pic_param->log2_tile_rows;
337 RK_U32 bit_depth = pic_param->BitDepthMinus8Luma + 8;
338 RK_S32 height = vp9_ver_align(pic_param->height);
339 RK_S32 width = vp9_ver_align(pic_param->width);
340
341 if (hw_ctx->num_row_tiles != num_tiles ||
342 hw_ctx->bit_depth != bit_depth ||
343 hw_ctx->width != width ||
344 hw_ctx->height != height) {
345
346 hw_ctx->rcb_buf_size = vdpu34x_get_rcb_buf_size(hw_ctx->rcb_info, width, height);
347 vp9d_refine_rcb_size(hw_ctx->rcb_info, hw_regs, width, height, pic_param);
348
349 if (p_hal->fast_mode) {
350 RK_U32 i;
351
352 for (i = 0; i < MPP_ARRAY_ELEMS(hw_ctx->g_buf); i++) {
353 MppBuffer rcb_buf = hw_ctx->g_buf[i].rcb_buf;
354
355 if (rcb_buf) {
356 mpp_buffer_put(rcb_buf);
357 hw_ctx->g_buf[i].rcb_buf = NULL;
358 }
359 mpp_buffer_get(p_hal->group, &rcb_buf, hw_ctx->rcb_buf_size);
360 hw_ctx->g_buf[i].rcb_buf = rcb_buf;
361 }
362 } else {
363 MppBuffer rcb_buf = hw_ctx->rcb_buf;
364
365 if (rcb_buf) {
366 mpp_buffer_put(rcb_buf);
367 rcb_buf = NULL;
368 }
369 mpp_buffer_get(p_hal->group, &rcb_buf, hw_ctx->rcb_buf_size);
370 hw_ctx->rcb_buf = rcb_buf;
371 }
372
373 hw_ctx->num_row_tiles = num_tiles;
374 hw_ctx->bit_depth = bit_depth;
375 hw_ctx->width = width;
376 hw_ctx->height = height;
377 }
378 }
379
hal_vp9d_vdpu34x_setup_colmv_buf(void * hal,HalTaskInfo * task)380 static MPP_RET hal_vp9d_vdpu34x_setup_colmv_buf(void *hal, HalTaskInfo *task)
381 {
382 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
383 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
384 DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
385 RK_U32 width = pic_param->width;
386 RK_U32 height = pic_param->height;
387 RK_S32 mv_size = 0, colmv_size = 8, colmv_byte = 16;
388 RK_U32 compress = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress : 1;
389
390 mv_size = vdpu34x_get_colmv_size(width, height, VP9_CTU_SIZE, colmv_byte, colmv_size, compress);
391 if (hw_ctx->cmv_bufs == NULL || hw_ctx->mv_size < mv_size) {
392 size_t size = mv_size;
393
394 if (hw_ctx->cmv_bufs) {
395 hal_bufs_deinit(hw_ctx->cmv_bufs);
396 hw_ctx->cmv_bufs = NULL;
397 }
398
399 hal_bufs_init(&hw_ctx->cmv_bufs);
400 if (hw_ctx->cmv_bufs == NULL) {
401 mpp_err_f("colmv bufs init fail");
402 return MPP_ERR_NOMEM;
403 }
404 hw_ctx->mv_size = mv_size;
405 hw_ctx->mv_count = mpp_buf_slot_get_count(p_hal ->slots);
406 hal_bufs_setup(hw_ctx->cmv_bufs, hw_ctx->mv_count, 1, &size);
407 }
408
409 return MPP_OK;
410 }
411
hal_vp9d_vdpu34x_gen_regs(void * hal,HalTaskInfo * task)412 static MPP_RET hal_vp9d_vdpu34x_gen_regs(void *hal, HalTaskInfo *task)
413 {
414 RK_S32 i;
415 RK_U8 bit_depth = 0;
416 RK_U32 ref_frame_width_y;
417 RK_U32 ref_frame_height_y;
418 RK_S32 stream_len = 0, aglin_offset = 0;
419 RK_U32 y_hor_virstride, uv_hor_virstride, y_virstride;
420 RK_U8 *bitstream = NULL;
421 MppBuffer streambuf = NULL;
422 RK_U32 sw_y_hor_virstride;
423 RK_U32 sw_uv_hor_virstride;
424 RK_U32 sw_y_virstride;
425 RK_U8 ref_idx = 0;
426 RK_U8 ref_frame_idx = 0;
427 RK_U32 *reg_ref_base = 0;
428 RK_S32 intraFlag = 0;
429 MppBuffer framebuf = NULL;
430 HalBuf *mv_buf = NULL;
431 RK_U32 fbc_en = 0;
432
433 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
434 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
435 DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
436 RK_U32 frame_ctx_id = pic_param->frame_context_idx;
437
438 if (p_hal->fast_mode) {
439 for (i = 0; i < MAX_GEN_REG; i++) {
440 if (!hw_ctx->g_buf[i].use_flag) {
441 task->dec.reg_index = i;
442 hw_ctx->probe_base = hw_ctx->g_buf[i].probe_base;
443
444 hw_ctx->hw_regs = hw_ctx->g_buf[i].hw_regs;
445 hw_ctx->g_buf[i].use_flag = 1;
446 break;
447 }
448 }
449 if (i == MAX_GEN_REG) {
450 mpp_err("vp9 fast mode buf all used\n");
451 return MPP_ERR_NOMEM;
452 }
453 }
454
455 if (hal_vp9d_vdpu34x_setup_colmv_buf(hal, task))
456 return MPP_ERR_NOMEM;
457
458 Vdpu34xVp9dRegSet *vp9_hw_regs = (Vdpu34xVp9dRegSet*)hw_ctx->hw_regs;
459 intraFlag = (!pic_param->frame_type || pic_param->intra_only);
460 stream_len = (RK_S32)mpp_packet_get_length(task->dec.input_packet);
461 memset(hw_ctx->hw_regs, 0, sizeof(Vdpu34xVp9dRegSet));
462 #if HW_PROB
463 hal_vp9d_prob_flag_delta(mpp_buffer_get_ptr(hw_ctx->probe_base), task->dec.syntax.data);
464 mpp_buffer_sync_end(hw_ctx->probe_base);
465 if (intraFlag) {
466 hal_vp9d_prob_default(mpp_buffer_get_ptr(hw_ctx->prob_default_base), task->dec.syntax.data);
467 mpp_buffer_sync_end(hw_ctx->prob_default_base);
468 }
469
470 /* config reg103 */
471 vp9_hw_regs->vp9d_param.reg103.prob_update_en = 1;
472 vp9_hw_regs->vp9d_param.reg103.intra_only_flag = intraFlag;
473 if (!intraFlag) {
474 vp9_hw_regs->vp9d_param.reg103.txfmmode_rfsh_en = (pic_param->txmode == 4) ? 1 : 0;
475 vp9_hw_regs->vp9d_param.reg103.interp_filter_switch_en = pic_param->interp_filter == 4 ? 1 : 0;
476 }
477 vp9_hw_regs->vp9d_param.reg103.ref_mode_rfsh_en = 1;
478 vp9_hw_regs->vp9d_param.reg103.single_ref_rfsh_en = 1;
479 vp9_hw_regs->vp9d_param.reg103.comp_ref_rfsh_en = 1;
480 vp9_hw_regs->vp9d_param.reg103.inter_coef_rfsh_flag = 0;
481 vp9_hw_regs->vp9d_param.reg103.refresh_en =
482 !pic_param->error_resilient_mode && !pic_param->parallelmode;
483 vp9_hw_regs->vp9d_param.reg103.prob_save_en = pic_param->refresh_frame_context;
484 vp9_hw_regs->vp9d_param.reg103.allow_high_precision_mv = pic_param->allow_high_precision_mv;
485 vp9_hw_regs->vp9d_param.reg103.last_key_frame_flag = hw_ctx->ls_info.last_intra_only;
486
487 /* set info for multi core */
488 {
489 MppFrame mframe = NULL;
490
491 mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
492 vp9_hw_regs->vp9d_param.reg65.cur_poc = mframe ? mpp_frame_get_poc(mframe) : 0;
493 // last poc
494 ref_idx = pic_param->frame_refs[0].Index7Bits;
495 ref_frame_idx = pic_param->ref_frame_map[ref_idx].Index7Bits;
496 if (ref_frame_idx < 0x7f) {
497 mframe = NULL;
498 mpp_buf_slot_get_prop(p_hal ->slots, ref_frame_idx, SLOT_FRAME_PTR, &mframe);
499 vp9_hw_regs->vp9d_param.reg95.last_poc = mframe ? mpp_frame_get_poc(mframe) : 0;
500 }
501 // golden poc
502 ref_idx = pic_param->frame_refs[1].Index7Bits;
503 ref_frame_idx = pic_param->ref_frame_map[ref_idx].Index7Bits;
504 if (ref_frame_idx < 0x7f) {
505 mframe = NULL;
506 mpp_buf_slot_get_prop(p_hal ->slots, ref_frame_idx, SLOT_FRAME_PTR, &mframe);
507 vp9_hw_regs->vp9d_param.reg96.golden_poc = mframe ? mpp_frame_get_poc(mframe) : 0;
508 }
509 // altref poc
510 ref_idx = pic_param->frame_refs[2].Index7Bits;
511 ref_frame_idx = pic_param->ref_frame_map[ref_idx].Index7Bits;
512 if (ref_frame_idx < 0x7f) {
513 mframe = NULL;
514 mpp_buf_slot_get_prop(p_hal ->slots, ref_frame_idx, SLOT_FRAME_PTR, &mframe);
515 vp9_hw_regs->vp9d_param.reg97.altref_poc = mframe ? mpp_frame_get_poc(mframe) : 0;
516 }
517 // colref poc
518 vp9_hw_regs->vp9d_param.reg98.col_ref_poc =
519 hw_ctx->col_ref_poc ? hw_ctx->col_ref_poc : vp9_hw_regs->vp9d_param.reg65.cur_poc;
520 if (pic_param->show_frame && !pic_param->show_existing_frame)
521 hw_ctx->col_ref_poc = vp9_hw_regs->vp9d_param.reg65.cur_poc;
522 // segment id ref poc
523 vp9_hw_regs->vp9d_param.reg100.segid_ref_poc = hw_ctx->segid_ref_poc;
524
525 vp9_hw_regs->vp9d_addr.reg169_segidcur_base = mpp_buffer_get_fd(hw_ctx->seg_base);
526 vp9_hw_regs->vp9d_addr.reg168_segidlast_base = mpp_buffer_get_fd(hw_ctx->seg_base);
527 if (hw_ctx->last_segid_flag) {
528 mpp_dev_set_reg_offset(p_hal->dev, 168, hw_ctx->offset_segid_last);
529 mpp_dev_set_reg_offset(p_hal->dev, 169, hw_ctx->offset_segid_cur);
530 } else {
531 mpp_dev_set_reg_offset(p_hal->dev, 168, hw_ctx->offset_segid_cur);
532 mpp_dev_set_reg_offset(p_hal->dev, 169, hw_ctx->offset_segid_last);
533 }
534
535 if ((pic_param->stVP9Segments.enabled && pic_param->stVP9Segments.update_map) ||
536 (hw_ctx->ls_info.last_width != pic_param->width) ||
537 (hw_ctx->ls_info.last_height != pic_param->height) ||
538 intraFlag || pic_param->error_resilient_mode) {
539 hw_ctx->segid_ref_poc = vp9_hw_regs->vp9d_param.reg65.cur_poc;
540 hw_ctx->last_segid_flag = !hw_ctx->last_segid_flag;
541 vp9_hw_regs->vp9d_param.reg100.segid_ref_poc = 0;
542 vp9_hw_regs->vp9d_param.reg75.vp9_segment_id_update = 1;
543 } else
544 vp9_hw_regs->vp9d_param.reg75.vp9_segment_id_update = 0;
545 }
546
547 /* config last prob base and update write base */
548 {
549
550 if (intraFlag || pic_param->error_resilient_mode) {
551 if (intraFlag
552 || pic_param->error_resilient_mode
553 || (pic_param->reset_frame_context == 3)) {
554 memset(hw_ctx->prob_ctx_valid, 0, sizeof(hw_ctx->prob_ctx_valid));
555 } else if (pic_param->reset_frame_context == 2) {
556 hw_ctx->prob_ctx_valid[frame_ctx_id] = 0;
557 }
558 }
559
560 #if VP9_DUMP
561 {
562 static RK_U32 file_cnt = 0;
563 char file_name[128];
564 RK_U32 i = 0;
565 sprintf(file_name, "/data/vp9/prob_last_%d.txt", file_cnt);
566 FILE *fp = fopen(file_name, "wb");
567 RK_U32 *tmp = NULL;
568 if (hw_ctx->prob_ctx_valid[frame_ctx_id]) {
569 tmp = (RK_U32 *)mpp_buffer_get_ptr(hw_ctx->prob_loop_base[pic_param->frame_context_idx]);
570 } else {
571 tmp = (RK_U32 *)mpp_buffer_get_ptr(hw_ctx->prob_default_base);
572 }
573 for (i = 0; i < PROB_SIZE / 4; i += 2) {
574 fprintf(fp, "%08x%08x\n", tmp[i + 1], tmp[i]);
575 }
576 file_cnt++;
577 fflush(fp);
578 fclose(fp);
579 }
580 #endif
581
582 if (hw_ctx->prob_ctx_valid[frame_ctx_id]) {
583 vp9_hw_regs->vp9d_addr.reg162_last_prob_base =
584 mpp_buffer_get_fd(hw_ctx->prob_loop_base[frame_ctx_id]);
585 vp9_hw_regs->common.reg028.swreg_vp9_rd_prob_idx = frame_ctx_id + 1;
586 vp9_hw_regs->vp9d_param.reg99.prob_ref_poc = hw_ctx->prob_ref_poc[frame_ctx_id];
587 } else {
588 vp9_hw_regs->vp9d_addr.reg162_last_prob_base = mpp_buffer_get_fd(hw_ctx->prob_default_base);
589 hw_ctx->prob_ctx_valid[frame_ctx_id] |= pic_param->refresh_frame_context;
590 vp9_hw_regs->common.reg028.swreg_vp9_rd_prob_idx = 0;
591 vp9_hw_regs->vp9d_param.reg99.prob_ref_poc = 0;
592 hw_ctx->prob_ref_poc[frame_ctx_id] = vp9_hw_regs->vp9d_param.reg65.cur_poc;
593 }
594 hal_vp9d_dbg_par("vp9d intra %d parallelmode %d frame_ctx_id %d refresh %d err %d\n",
595 intraFlag, pic_param->parallelmode, frame_ctx_id,
596 pic_param->refresh_frame_context, pic_param->error_resilient_mode);
597 if (!pic_param->parallelmode)
598 hw_ctx->prob_ref_poc[frame_ctx_id] = vp9_hw_regs->vp9d_param.reg65.cur_poc;
599 vp9_hw_regs->vp9d_addr.reg172_update_prob_wr_base =
600 mpp_buffer_get_fd(hw_ctx->prob_loop_base[frame_ctx_id]);
601 vp9_hw_regs->common.reg028.swreg_vp9_wr_prob_idx = frame_ctx_id + 1;
602
603 }
604 vp9_hw_regs->vp9d_addr.reg160_delta_prob_base = mpp_buffer_get_fd(hw_ctx->probe_base);
605 #else
606 hal_vp9d_output_probe(mpp_buffer_get_ptr(hw_ctx->probe_base), task->dec.syntax.data);
607 mpp_buffer_sync_end(hw_ctx->probe_base);
608 #endif
609 vp9_hw_regs->common.reg012.colmv_compress_en = p_hal->hw_info ? p_hal->hw_info->cap_colmv_compress : 1;
610 vp9_hw_regs->common.reg013.cur_pic_is_idr = !pic_param->frame_type;
611 vp9_hw_regs->common.reg009.dec_mode = 2; //set as vp9 dec
612 vp9_hw_regs->common.reg016_str_len = ((stream_len + 15) & (~15)) + 0x80;
613
614 mpp_buf_slot_get_prop(p_hal ->packet_slots, task->dec.input, SLOT_BUFFER, &streambuf);
615 bitstream = mpp_buffer_get_ptr(streambuf);
616 aglin_offset = vp9_hw_regs->common.reg016_str_len - stream_len;
617 if (aglin_offset > 0) {
618 memset((void *)(bitstream + stream_len), 0, aglin_offset);
619 }
620
621 //--- caculate the yuv_frame_size and mv_size
622 bit_depth = pic_param->BitDepthMinus8Luma + 8;
623
624 {
625 MppFrame mframe = NULL;
626
627 mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
628 fbc_en = MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe));
629
630 if (fbc_en) {
631 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
632 RK_U32 h = MPP_ALIGN(mpp_frame_get_height(mframe), 64);
633 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K);
634
635 vp9_hw_regs->common.reg012.fbc_e = 1;
636 vp9_hw_regs->common.reg018.y_hor_virstride = fbc_hdr_stride >> 4;
637 vp9_hw_regs->common.reg019.uv_hor_virstride = fbc_hdr_stride >> 4;
638 vp9_hw_regs->common.reg020_fbc_payload_off.payload_st_offset = fbd_offset >> 4;
639 } else {
640 sw_y_hor_virstride = mpp_frame_get_hor_stride(mframe) >> 4;
641 sw_uv_hor_virstride = sw_y_hor_virstride;
642 sw_y_virstride = mpp_frame_get_ver_stride(mframe) * sw_y_hor_virstride;
643
644 vp9_hw_regs->common.reg012.fbc_e = 0;
645 vp9_hw_regs->common.reg018.y_hor_virstride = sw_y_hor_virstride;
646 vp9_hw_regs->common.reg019.uv_hor_virstride = sw_uv_hor_virstride;
647 vp9_hw_regs->common.reg020_y_virstride.y_virstride = sw_y_virstride;
648 }
649 }
650 if (!pic_param->intra_only && pic_param->frame_type &&
651 !pic_param->error_resilient_mode && hw_ctx->ls_info.last_show_frame) {
652 hw_ctx->pre_mv_base_addr = hw_ctx->mv_base_addr;
653 }
654
655 mpp_buf_slot_get_prop(p_hal ->slots, task->dec.output, SLOT_BUFFER, &framebuf);
656 vp9_hw_regs->common_addr.reg130_decout_base = mpp_buffer_get_fd(framebuf);
657 vp9_hw_regs->common_addr.reg128_rlc_base = mpp_buffer_get_fd(streambuf);
658 vp9_hw_regs->common_addr.reg129_rlcwrite_base = mpp_buffer_get_fd(streambuf);
659
660 vp9_hw_regs->vp9d_addr.reg167_count_prob_base = mpp_buffer_get_fd(hw_ctx->probe_base);
661 mpp_dev_set_reg_offset(p_hal->dev, 167, hw_ctx->offset_count);
662
663 //set cur colmv base
664 mv_buf = hal_bufs_get_buf(hw_ctx->cmv_bufs, task->dec.output);
665 vp9_hw_regs->common_addr.reg131_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
666 hw_ctx->mv_base_addr = vp9_hw_regs->common_addr.reg131_colmv_cur_base;
667 if (hw_ctx->pre_mv_base_addr < 0) {
668 hw_ctx->pre_mv_base_addr = hw_ctx->mv_base_addr;
669 }
670 vp9_hw_regs->vp9d_addr.reg170_ref_colmv_base = hw_ctx->pre_mv_base_addr;
671
672 vp9_hw_regs->vp9d_param.reg64.cprheader_offset = 0;
673 reg_ref_base = (RK_U32*)&vp9_hw_regs->vp9d_addr.reg164_ref_last_base;
674 for (i = 0; i < 3; i++) {
675 MppFrame frame = NULL;
676
677 ref_idx = pic_param->frame_refs[i].Index7Bits;
678 ref_frame_idx = pic_param->ref_frame_map[ref_idx].Index7Bits;
679 ref_frame_width_y = pic_param->ref_frame_coded_width[ref_idx];
680 ref_frame_height_y = pic_param->ref_frame_coded_height[ref_idx];
681
682 if (ref_frame_idx < 0x7f)
683 mpp_buf_slot_get_prop(p_hal ->slots, ref_frame_idx, SLOT_FRAME_PTR, &frame);
684
685 if (fbc_en && frame) {
686 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(frame);
687 RK_U32 h = MPP_ALIGN(mpp_frame_get_height(frame), 64);
688 RK_U32 fbd_offset = MPP_ALIGN(fbc_hdr_stride * (h + 16) / 16, SZ_4K);
689
690 y_hor_virstride = uv_hor_virstride = fbc_hdr_stride >> 4;
691 y_virstride = fbd_offset;
692 } else {
693 if (frame) {
694 y_hor_virstride = uv_hor_virstride = mpp_frame_get_hor_stride(frame) >> 4;
695 y_virstride = y_hor_virstride * mpp_frame_get_ver_stride(frame);
696 } else {
697 y_hor_virstride = uv_hor_virstride = (vp9_hor_align((ref_frame_width_y * bit_depth) >> 3) >> 4);
698 y_virstride = y_hor_virstride * vp9_ver_align(ref_frame_height_y);
699 }
700 }
701
702 if (pic_param->ref_frame_map[ref_idx].Index7Bits < 0x7f) {
703 mpp_buf_slot_get_prop(p_hal ->slots, pic_param->ref_frame_map[ref_idx].Index7Bits, SLOT_BUFFER, &framebuf);
704 }
705
706 if (pic_param->ref_frame_map[ref_idx].Index7Bits < 0x7f) {
707 switch (i) {
708 case 0: {
709 vp9_hw_regs->vp9d_param.reg106.framewidth_last = ref_frame_width_y;
710 vp9_hw_regs->vp9d_param.reg107.frameheight_last = ref_frame_height_y;
711 vp9_hw_regs->vp9d_param.reg79.lastfy_hor_virstride = y_hor_virstride;
712 vp9_hw_regs->vp9d_param.reg80.lastfuv_hor_virstride = uv_hor_virstride;
713 vp9_hw_regs->vp9d_param.reg85.lastfy_virstride = y_virstride;
714 } break;
715 case 1: {
716 vp9_hw_regs->vp9d_param.reg108.framewidth_golden = ref_frame_width_y;
717 vp9_hw_regs->vp9d_param.reg109.frameheight_golden = ref_frame_height_y;
718 vp9_hw_regs->vp9d_param.reg81.goldenfy_hor_virstride = y_hor_virstride;
719 vp9_hw_regs->vp9d_param.reg82.goldenfuv_hor_virstride = uv_hor_virstride;
720 vp9_hw_regs->vp9d_param.reg86.goldeny_virstride = y_virstride;
721 } break;
722 case 2: {
723 vp9_hw_regs->vp9d_param.reg110.framewidth_alfter = ref_frame_width_y;
724 vp9_hw_regs->vp9d_param.reg111.frameheight_alfter = ref_frame_height_y;
725 vp9_hw_regs->vp9d_param.reg83.altreffy_hor_virstride = y_hor_virstride;
726 vp9_hw_regs->vp9d_param.reg84.altreffuv_hor_virstride = uv_hor_virstride;
727 vp9_hw_regs->vp9d_param.reg87.altrefy_virstride = y_virstride;
728 } break;
729 default:
730 break;
731 }
732
733 /*0 map to 11*/
734 /*1 map to 12*/
735 /*2 map to 13*/
736 if (framebuf != NULL) {
737 reg_ref_base[i] = mpp_buffer_get_fd(framebuf);
738 } else {
739 mpp_log("ref buff address is no valid used out as base slot index 0x%x", pic_param->ref_frame_map[ref_idx].Index7Bits);
740 reg_ref_base[i] = vp9_hw_regs->common_addr.reg130_decout_base;
741 }
742 mv_buf = hal_bufs_get_buf(hw_ctx->cmv_bufs, pic_param->ref_frame_map[ref_idx].Index7Bits);
743 vp9_hw_regs->vp9d_addr.reg181_196_ref_colmv_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
744 } else {
745 reg_ref_base[i] = vp9_hw_regs->common_addr.reg130_decout_base;
746 vp9_hw_regs->vp9d_addr.reg181_196_ref_colmv_base[i] = vp9_hw_regs->common_addr.reg131_colmv_cur_base;
747 }
748 }
749
750 for (i = 0; i < 8; i++) {
751 vp9_hw_regs->vp9d_param.reg67_74[i].segid_frame_qp_delta_en = (hw_ctx->ls_info.feature_mask[i]) & 0x1;
752 vp9_hw_regs->vp9d_param.reg67_74[i].segid_frame_qp_delta = hw_ctx->ls_info.feature_data[i][0];
753 vp9_hw_regs->vp9d_param.reg67_74[i].segid_frame_loopfitler_value_en = (hw_ctx->ls_info.feature_mask[i] >> 1) & 0x1;
754 vp9_hw_regs->vp9d_param.reg67_74[i].segid_frame_loopfilter_value = hw_ctx->ls_info.feature_data[i][1];
755 vp9_hw_regs->vp9d_param.reg67_74[i].segid_referinfo_en = (hw_ctx->ls_info.feature_mask[i] >> 2) & 0x1;
756 vp9_hw_regs->vp9d_param.reg67_74[i].segid_referinfo = hw_ctx->ls_info.feature_data[i][2];
757 vp9_hw_regs->vp9d_param.reg67_74[i].segid_frame_skip_en = (hw_ctx->ls_info.feature_mask[i] >> 3) & 0x1;
758 }
759
760 vp9_hw_regs->vp9d_param.reg67_74[0].segid_abs_delta = hw_ctx->ls_info.abs_delta_last;
761 vp9_hw_regs->vp9d_param.reg76.tx_mode = pic_param->txmode;
762 vp9_hw_regs->vp9d_param.reg76.frame_reference_mode = pic_param->refmode;
763 vp9_hw_regs->vp9d_param.reg94.ref_deltas_lastframe = 0;
764
765 if (!intraFlag) {
766 for (i = 0; i < 4; i++)
767 vp9_hw_regs->vp9d_param.reg94.ref_deltas_lastframe |= (hw_ctx->ls_info.last_ref_deltas[i] & 0x7f) << (7 * i);
768
769 for (i = 0; i < 2; i++)
770 vp9_hw_regs->vp9d_param.reg75.mode_deltas_lastframe |= (hw_ctx->ls_info.last_mode_deltas[i] & 0x7f) << (7 * i);
771 } else {
772 hw_ctx->ls_info.segmentation_enable_flag_last = 0;
773 hw_ctx->ls_info.last_intra_only = 1;
774 }
775
776 vp9_hw_regs->vp9d_param.reg75.segmentation_enable_lstframe = hw_ctx->ls_info.segmentation_enable_flag_last;
777 vp9_hw_regs->vp9d_param.reg75.last_show_frame = hw_ctx->ls_info.last_show_frame;
778 vp9_hw_regs->vp9d_param.reg75.last_intra_only = hw_ctx->ls_info.last_intra_only;
779 vp9_hw_regs->vp9d_param.reg75.last_widthheight_eqcur = (pic_param->width == hw_ctx->ls_info.last_width) && (pic_param->height == hw_ctx->ls_info.last_height);
780 vp9_hw_regs->vp9d_param.reg78.lasttile_size = stream_len - pic_param->first_partition_size;
781
782
783 if (!intraFlag) {
784 vp9_hw_regs->vp9d_param.reg88.lref_hor_scale = pic_param->mvscale[0][0];
785 vp9_hw_regs->vp9d_param.reg89.lref_ver_scale = pic_param->mvscale[0][1];
786 vp9_hw_regs->vp9d_param.reg90.gref_hor_scale = pic_param->mvscale[1][0];
787 vp9_hw_regs->vp9d_param.reg91.gref_ver_scale = pic_param->mvscale[1][1];
788 vp9_hw_regs->vp9d_param.reg92.aref_hor_scale = pic_param->mvscale[2][0];
789 vp9_hw_regs->vp9d_param.reg93.aref_ver_scale = pic_param->mvscale[2][1];
790 }
791
792 vp9_hw_regs->common.reg010.dec_e = 1;
793 vp9_hw_regs->common.reg011.dec_timeout_e = 1;
794 vp9_hw_regs->common.reg011.buf_empty_en = 1;
795 vp9_hw_regs->common.reg011.dec_clkgate_e = 1;
796 vp9_hw_regs->common.reg011.dec_e_strmd_clkgate_dis = 0;
797
798 vp9_hw_regs->common.reg012.wait_reset_en = 1;
799 vp9_hw_regs->common.reg013.timeout_mode = 1;
800
801 vp9_hw_regs->common.reg026.swreg_block_gating_e =
802 (mpp_get_soc_type() == ROCKCHIP_SOC_RK3588) ? 0xfffef : 0xfffff;
803 vp9_hw_regs->common.reg026.reg_cfg_gating_en = 1;
804 vp9_hw_regs->common.reg032_timeout_threshold = 0x3ffff;
805
806 //last info update
807 hw_ctx->ls_info.abs_delta_last = pic_param->stVP9Segments.abs_delta;
808 for (i = 0 ; i < 4; i ++) {
809 hw_ctx->ls_info.last_ref_deltas[i] = pic_param->ref_deltas[i];
810 }
811
812 for (i = 0 ; i < 2; i ++) {
813 hw_ctx->ls_info.last_mode_deltas[i] = pic_param->mode_deltas[i];
814 }
815
816 for (i = 0; i < 8; i++) {
817 hw_ctx->ls_info.feature_data[i][0] = pic_param->stVP9Segments.feature_data[i][0];
818 hw_ctx->ls_info.feature_data[i][1] = pic_param->stVP9Segments.feature_data[i][1];
819 hw_ctx->ls_info.feature_data[i][2] = pic_param->stVP9Segments.feature_data[i][2];
820 hw_ctx->ls_info.feature_data[i][3] = pic_param->stVP9Segments.feature_data[i][3];
821 hw_ctx->ls_info.feature_mask[i] = pic_param->stVP9Segments.feature_mask[i];
822 }
823 if (!hw_ctx->ls_info.segmentation_enable_flag_last)
824 hw_ctx->ls_info.segmentation_enable_flag_last = pic_param->stVP9Segments.enabled;
825
826 hw_ctx->ls_info.last_show_frame = pic_param->show_frame;
827 hw_ctx->ls_info.last_width = pic_param->width;
828 hw_ctx->ls_info.last_height = pic_param->height;
829 hw_ctx->ls_info.last_intra_only = (!pic_param->frame_type || pic_param->intra_only);
830 hal_vp9d_dbg_par("stVP9Segments.enabled %d show_frame %d width %d height %d last_intra_only %d",
831 pic_param->stVP9Segments.enabled, pic_param->show_frame,
832 pic_param->width, pic_param->height,
833 hw_ctx->ls_info.last_intra_only);
834
835 hal_vp9d_rcb_info_update(hal, vp9_hw_regs, pic_param);
836 {
837 MppBuffer rcb_buf = NULL;
838
839 rcb_buf = p_hal->fast_mode ? hw_ctx->g_buf[task->dec.reg_index].rcb_buf : hw_ctx->rcb_buf;
840 vdpu34x_setup_rcb(&vp9_hw_regs->common_addr, p_hal->dev, rcb_buf, hw_ctx->rcb_info);
841 }
842 vdpu34x_setup_statistic(&vp9_hw_regs->common, &vp9_hw_regs->statistic);
843
844 // whether need update counts
845 if (pic_param->refresh_frame_context && !pic_param->parallelmode) {
846 task->dec.flags.wait_done = 1;
847 }
848
849 return MPP_OK;
850 }
851
hal_vp9d_vdpu34x_start(void * hal,HalTaskInfo * task)852 static MPP_RET hal_vp9d_vdpu34x_start(void *hal, HalTaskInfo *task)
853 {
854 MPP_RET ret = MPP_OK;
855 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
856 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
857 Vdpu34xVp9dRegSet *hw_regs = (Vdpu34xVp9dRegSet *)hw_ctx->hw_regs;
858 MppDev dev = p_hal->dev;
859
860 if (p_hal->fast_mode) {
861 RK_S32 index = task->dec.reg_index;
862 hw_regs = (Vdpu34xVp9dRegSet *)hw_ctx->g_buf[index].hw_regs;
863 }
864
865 mpp_assert(hw_regs);
866
867
868 #if VP9_DUMP
869 {
870 static RK_U32 file_cnt = 0;
871 char file_name[128];
872 sprintf(file_name, "/data/vp9_regs/reg_%d.txt", file_cnt);
873 FILE *fp = fopen(file_name, "wb");
874 RK_U32 i = 0;
875 RK_U32 *tmp = NULL;
876 tmp = (RK_U32 *)&hw_regs->common;
877 for (i = 0; i < sizeof(hw_regs->common) / 4; i++) {
878 fprintf(fp, "reg[%d] 0x%08x\n", i + 8, tmp[i]);
879 }
880 fprintf(fp, "\n");
881 tmp = (RK_U32 *)&hw_regs->vp9d_param;
882 for (i = 0; i < sizeof(hw_regs->vp9d_param) / 4; i++) {
883 fprintf(fp, "reg[%d] 0x%08x\n", i + 64, tmp[i]);
884 }
885 fprintf(fp, "\n");
886 tmp = (RK_U32 *)&hw_regs->common_addr;
887 for (i = 0; i < sizeof(hw_regs->common_addr) / 4; i++) {
888 fprintf(fp, "reg[%d] 0x%08x\n", i + 128, tmp[i]);
889 }
890 fprintf(fp, "\n");
891 tmp = (RK_U32 *)&hw_regs->vp9d_addr;
892 for (i = 0; i < sizeof(hw_regs->vp9d_addr) / 4; i++) {
893 fprintf(fp, "reg[%d] 0x%08x\n", i + 160, tmp[i]);
894 }
895 file_cnt++;
896 fflush(fp);
897 fclose(fp);
898 }
899 #endif
900
901 do {
902 MppDevRegWrCfg wr_cfg;
903 MppDevRegRdCfg rd_cfg;
904
905 wr_cfg.reg = &hw_regs->common;
906 wr_cfg.size = sizeof(hw_regs->common);
907 wr_cfg.offset = OFFSET_COMMON_REGS;
908
909 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
910 if (ret) {
911 mpp_err_f("set register write failed %d\n", ret);
912 break;
913 }
914
915 wr_cfg.reg = &hw_regs->vp9d_param;
916 wr_cfg.size = sizeof(hw_regs->vp9d_param);
917 wr_cfg.offset = OFFSET_CODEC_PARAMS_REGS;
918
919 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
920 if (ret) {
921 mpp_err_f("set register write failed %d\n", ret);
922 break;
923 }
924
925 wr_cfg.reg = &hw_regs->common_addr;
926 wr_cfg.size = sizeof(hw_regs->common_addr);
927 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
928
929 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
930 if (ret) {
931 mpp_err_f("set register write failed %d\n", ret);
932 break;
933 }
934
935 wr_cfg.reg = &hw_regs->vp9d_addr;
936 wr_cfg.size = sizeof(hw_regs->vp9d_addr);
937 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
938
939 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
940 if (ret) {
941 mpp_err_f("set register write failed %d\n", ret);
942 break;
943 }
944
945 wr_cfg.reg = &hw_regs->statistic;
946 wr_cfg.size = sizeof(hw_regs->statistic);
947 wr_cfg.offset = OFFSET_STATISTIC_REGS;
948
949 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
950 if (ret) {
951 mpp_err_f("set register write failed %d\n", ret);
952 break;
953 }
954
955 rd_cfg.reg = &hw_regs->irq_status;
956 rd_cfg.size = sizeof(hw_regs->irq_status);
957 rd_cfg.offset = OFFSET_INTERRUPT_REGS;
958
959 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
960 if (ret) {
961 mpp_err_f("set register read failed %d\n", ret);
962 break;
963 }
964
965 /* rcb info for sram */
966 vdpu34x_set_rcbinfo(dev, hw_ctx->rcb_info);
967
968 ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
969 if (ret) {
970 mpp_err_f("send cmd failed %d\n", ret);
971 break;
972 }
973 } while (0);
974
975 (void)task;
976 return ret;
977 }
978
hal_vp9d_vdpu34x_wait(void * hal,HalTaskInfo * task)979 static MPP_RET hal_vp9d_vdpu34x_wait(void *hal, HalTaskInfo *task)
980 {
981 MPP_RET ret = MPP_OK;
982 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
983 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
984 Vdpu34xVp9dRegSet *hw_regs = (Vdpu34xVp9dRegSet *)hw_ctx->hw_regs;
985
986 if (p_hal->fast_mode)
987 hw_regs = (Vdpu34xVp9dRegSet *)hw_ctx->g_buf[task->dec.reg_index].hw_regs;
988
989 mpp_assert(hw_regs);
990
991 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
992 if (ret)
993 mpp_err_f("poll cmd failed %d\n", ret);
994
995 if (hal_vp9d_debug & HAL_VP9D_DBG_REG) {
996 RK_U32 *p = (RK_U32 *)hw_regs;
997 RK_U32 i = 0;
998
999 for (i = 0; i < sizeof(Vdpu34xVp9dRegSet) / 4; i++)
1000 mpp_log("get regs[%02d]: %08X\n", i, *p++);
1001 }
1002
1003 if (task->dec.flags.parse_err ||
1004 task->dec.flags.ref_err ||
1005 !hw_regs->irq_status.reg224.dec_rdy_sta) {
1006 MppFrame mframe = NULL;
1007 mpp_buf_slot_get_prop(p_hal->slots, task->dec.output, SLOT_FRAME_PTR, &mframe);
1008 mpp_frame_set_errinfo(mframe, 1);
1009 }
1010 #if !HW_PROB
1011 if (p_hal->dec_cb && task->dec.flags.wait_done) {
1012 DXVA_PicParams_VP9 *pic_param = (DXVA_PicParams_VP9*)task->dec.syntax.data;
1013
1014 mpp_buffer_sync_end(hw_ctx->count_base);
1015 hal_vp9d_update_counts(mpp_buffer_get_ptr(hw_ctx->count_base), task->dec.syntax.data);
1016 mpp_callback(p_hal->dec_cb, &pic_param->counts);
1017 }
1018 #endif
1019 if (p_hal->fast_mode) {
1020 hw_ctx->g_buf[task->dec.reg_index].use_flag = 0;
1021 }
1022
1023 (void)task;
1024 return ret;
1025 }
1026
hal_vp9d_vdpu34x_reset(void * hal)1027 static MPP_RET hal_vp9d_vdpu34x_reset(void *hal)
1028 {
1029 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
1030 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
1031
1032 hal_vp9d_enter();
1033
1034 memset(&hw_ctx->ls_info, 0, sizeof(hw_ctx->ls_info));
1035 hw_ctx->mv_base_addr = -1;
1036 hw_ctx->pre_mv_base_addr = -1;
1037 hw_ctx->last_segid_flag = 1;
1038 memset(&hw_ctx->prob_ref_poc, 0, sizeof(hw_ctx->prob_ref_poc));
1039 hw_ctx->col_ref_poc = 0;
1040 hw_ctx->segid_ref_poc = 0;
1041
1042 hal_vp9d_leave();
1043
1044 return MPP_OK;
1045 }
1046
hal_vp9d_vdpu34x_flush(void * hal)1047 static MPP_RET hal_vp9d_vdpu34x_flush(void *hal)
1048 {
1049 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
1050 Vdpu34xVp9dCtx *hw_ctx = (Vdpu34xVp9dCtx*)p_hal->hw_ctx;
1051
1052 hal_vp9d_enter();
1053
1054 hw_ctx->mv_base_addr = -1;
1055 hw_ctx->pre_mv_base_addr = -1;
1056
1057 hal_vp9d_leave();
1058
1059 return MPP_OK;
1060 }
1061
hal_vp9d_vdpu34x_control(void * hal,MpiCmd cmd_type,void * param)1062 static MPP_RET hal_vp9d_vdpu34x_control(void *hal, MpiCmd cmd_type, void *param)
1063 {
1064 HalVp9dCtx *p_hal = (HalVp9dCtx*)hal;
1065
1066 switch ((MpiCmd)cmd_type) {
1067 case MPP_DEC_SET_FRAME_INFO : {
1068 MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
1069
1070 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1071 vdpu34x_afbc_align_calc(p_hal->slots, (MppFrame)param, 0);
1072 } else {
1073 mpp_slots_set_prop(p_hal->slots, SLOTS_HOR_ALIGN, vp9_hor_align);
1074 }
1075 } break;
1076 default : {
1077 } break;
1078 }
1079
1080 return MPP_OK;
1081 }
1082
1083 const MppHalApi hal_vp9d_vdpu34x = {
1084 .name = "vp9d_vdpu34x",
1085 .type = MPP_CTX_DEC,
1086 .coding = MPP_VIDEO_CodingVP9,
1087 .ctx_size = sizeof(Vdpu34xVp9dCtx),
1088 .flag = 0,
1089 .init = hal_vp9d_vdpu34x_init,
1090 .deinit = hal_vp9d_vdpu34x_deinit,
1091 .reg_gen = hal_vp9d_vdpu34x_gen_regs,
1092 .start = hal_vp9d_vdpu34x_start,
1093 .wait = hal_vp9d_vdpu34x_wait,
1094 .reset = hal_vp9d_vdpu34x_reset,
1095 .flush = hal_vp9d_vdpu34x_flush,
1096 .control = hal_vp9d_vdpu34x_control,
1097 };
1098