1 /*
2 * Copyright 2020 Rockchip Electronics Co. LTD
3 *
4 * Licensed under the Apache License, Version 2.0 (the "License");
5 * you may not use this file except in compliance with the License.
6 * You may obtain a copy of the License at
7 *
8 * http://www.apache.org/licenses/LICENSE-2.0
9 *
10 * Unless required by applicable law or agreed to in writing, software
11 * distributed under the License is distributed on an "AS IS" BASIS,
12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 * See the License for the specific language governing permissions and
14 * limitations under the License.
15 */
16
17 #define MODULE_TAG "vdpu34x_com"
18
19 #include <string.h>
20 #include <stdlib.h>
21
22 #include "mpp_log.h"
23 #include "mpp_buffer.h"
24 #include "mpp_common.h"
25 #include "mpp_compat_impl.h"
26 #include "mpp_env.h"
27
28 #include "vdpu34x_com.h"
29
30 static RK_U32 rcb_coeff[RCB_BUF_COUNT] = {
31 [RCB_INTRA_ROW] = 6, /* RCB_INTRA_ROW_COEF */
32 [RCB_TRANSD_ROW] = 1, /* RCB_TRANSD_ROW_COEF */
33 [RCB_TRANSD_COL] = 1, /* RCB_TRANSD_COL_COEF */
34 [RCB_STRMD_ROW] = 3, /* RCB_STRMD_ROW_COEF */
35 [RCB_INTER_ROW] = 6, /* RCB_INTER_ROW_COEF */
36 [RCB_INTER_COL] = 3, /* RCB_INTER_COL_COEF */
37 [RCB_DBLK_ROW] = 22, /* RCB_DBLK_ROW_COEF */
38 [RCB_SAO_ROW] = 6, /* RCB_SAO_ROW_COEF */
39 [RCB_FBC_ROW] = 11, /* RCB_FBC_ROW_COEF */
40 [RCB_FILT_COL] = 67, /* RCB_FILT_COL_COEF */
41 };
42
update_size_offset(Vdpu34xRcbInfo * info,RK_U32 reg,RK_S32 offset,RK_S32 len,RK_S32 idx)43 static RK_S32 update_size_offset(Vdpu34xRcbInfo *info, RK_U32 reg,
44 RK_S32 offset, RK_S32 len, RK_S32 idx)
45 {
46 RK_S32 buf_size = 0;
47
48 buf_size = MPP_ALIGN(len * rcb_coeff[idx], RCB_ALLINE_SIZE);
49 info[idx].reg = reg;
50 info[idx].offset = offset;
51 info[idx].size = buf_size;
52
53 return buf_size;
54 }
55
vdpu34x_get_rcb_buf_size(Vdpu34xRcbInfo * info,RK_S32 width,RK_S32 height)56 RK_S32 vdpu34x_get_rcb_buf_size(Vdpu34xRcbInfo *info, RK_S32 width, RK_S32 height)
57 {
58 RK_S32 offset = 0;
59
60 offset += update_size_offset(info, 139, offset, width, RCB_DBLK_ROW);
61 offset += update_size_offset(info, 133, offset, width, RCB_INTRA_ROW);
62 offset += update_size_offset(info, 134, offset, width, RCB_TRANSD_ROW);
63 offset += update_size_offset(info, 136, offset, width, RCB_STRMD_ROW);
64 offset += update_size_offset(info, 137, offset, width, RCB_INTER_ROW);
65 offset += update_size_offset(info, 140, offset, width, RCB_SAO_ROW);
66 offset += update_size_offset(info, 141, offset, width, RCB_FBC_ROW);
67 /* col rcb */
68 offset += update_size_offset(info, 135, offset, height, RCB_TRANSD_COL);
69 offset += update_size_offset(info, 138, offset, height, RCB_INTER_COL);
70 offset += update_size_offset(info, 142, offset, height, RCB_FILT_COL);
71
72 return offset;
73 }
74
vdpu34x_setup_rcb(Vdpu34xRegCommonAddr * reg,MppDev dev,MppBuffer buf,Vdpu34xRcbInfo * info)75 void vdpu34x_setup_rcb(Vdpu34xRegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu34xRcbInfo *info)
76 {
77 RK_S32 fd = mpp_buffer_get_fd(buf);
78
79 reg->reg139_rcb_dblk_base = fd;
80 reg->reg133_rcb_intra_base = fd;
81 reg->reg134_rcb_transd_row_base = fd;
82 reg->reg136_rcb_streamd_row_base = fd;
83 reg->reg137_rcb_inter_row_base = fd;
84 reg->reg140_rcb_sao_base = fd;
85 reg->reg141_rcb_fbc_base = fd;
86 reg->reg135_rcb_transd_col_base = fd;
87 reg->reg138_rcb_inter_col_base = fd;
88 reg->reg142_rcb_filter_col_base = fd;
89
90 if (info[RCB_DBLK_ROW].offset)
91 mpp_dev_set_reg_offset(dev, 139, info[RCB_DBLK_ROW].offset);
92 if (info[RCB_INTRA_ROW].offset)
93 mpp_dev_set_reg_offset(dev, 133, info[RCB_INTRA_ROW].offset);
94 if (info[RCB_TRANSD_ROW].offset)
95 mpp_dev_set_reg_offset(dev, 134, info[RCB_TRANSD_ROW].offset);
96 if (info[RCB_STRMD_ROW].offset)
97 mpp_dev_set_reg_offset(dev, 136, info[RCB_STRMD_ROW].offset);
98 if (info[RCB_INTER_ROW].offset)
99 mpp_dev_set_reg_offset(dev, 137, info[RCB_INTER_ROW].offset);
100 if (info[RCB_SAO_ROW].offset)
101 mpp_dev_set_reg_offset(dev, 140, info[RCB_SAO_ROW].offset);
102 if (info[RCB_FBC_ROW].offset)
103 mpp_dev_set_reg_offset(dev, 141, info[RCB_FBC_ROW].offset);
104 if (info[RCB_TRANSD_COL].offset)
105 mpp_dev_set_reg_offset(dev, 135, info[RCB_TRANSD_COL].offset);
106 if (info[RCB_INTER_COL].offset)
107 mpp_dev_set_reg_offset(dev, 138, info[RCB_INTER_COL].offset);
108 if (info[RCB_FILT_COL].offset)
109 mpp_dev_set_reg_offset(dev, 142, info[RCB_FILT_COL].offset);
110 }
111
vdpu34x_compare_rcb_size(const void * a,const void * b)112 static RK_S32 vdpu34x_compare_rcb_size(const void *a, const void *b)
113 {
114 Vdpu34xRcbInfo *p0 = (Vdpu34xRcbInfo *)a;
115 Vdpu34xRcbInfo *p1 = (Vdpu34xRcbInfo *)b;
116
117 return (p0->size > p1->size) ? -1 : 1;
118 }
119
vdpu34x_set_rcbinfo(MppDev dev,Vdpu34xRcbInfo * rcb_info)120 RK_S32 vdpu34x_set_rcbinfo(MppDev dev, Vdpu34xRcbInfo *rcb_info)
121 {
122 MppDevRcbInfoCfg rcb_cfg;
123 RK_U32 i;
124 /*
125 * RCB_SET_BY_SIZE_SORT_MODE: by size sort
126 * RCB_SET_BY_PRIORITY_MODE: by priority
127 */
128 Vdpu34xRcbSetMode_e set_rcb_mode = RCB_SET_BY_PRIORITY_MODE;
129 RK_U32 rcb_priority[RCB_BUF_COUNT] = {
130 RCB_DBLK_ROW,
131 RCB_INTRA_ROW,
132 RCB_SAO_ROW,
133 RCB_INTER_ROW,
134 RCB_FBC_ROW,
135 RCB_TRANSD_ROW,
136 RCB_STRMD_ROW,
137 RCB_INTER_COL,
138 RCB_FILT_COL,
139 RCB_TRANSD_COL,
140 };
141
142 switch (set_rcb_mode) {
143 case RCB_SET_BY_SIZE_SORT_MODE : {
144 Vdpu34xRcbInfo info[RCB_BUF_COUNT];
145
146 memcpy(info, rcb_info, sizeof(info));
147 qsort(info, MPP_ARRAY_ELEMS(info),
148 sizeof(info[0]), vdpu34x_compare_rcb_size);
149
150 for (i = 0; i < MPP_ARRAY_ELEMS(info); i++) {
151 rcb_cfg.reg_idx = info[i].reg;
152 rcb_cfg.size = info[i].size;
153 if (rcb_cfg.size > 0) {
154 mpp_dev_ioctl(dev, MPP_DEV_RCB_INFO, &rcb_cfg);
155 } else
156 break;
157 }
158 } break;
159 case RCB_SET_BY_PRIORITY_MODE : {
160 Vdpu34xRcbInfo *info = rcb_info;
161 RK_U32 index = 0;
162
163 for (i = 0; i < MPP_ARRAY_ELEMS(rcb_priority); i ++) {
164 index = rcb_priority[i];
165 /*
166 * If the inter row rcb buffer is placed in sram,
167 * may conflict with other buffer in ddr,
168 * will result in slower access to data and degraded decoding performance.
169 * The issue will be resolved in chips after rk3588.
170 */
171 if (index == RCB_INTER_ROW)
172 continue;
173
174 rcb_cfg.reg_idx = info[index].reg;
175 rcb_cfg.size = info[index].size;
176 if (rcb_cfg.size > 0) {
177 mpp_dev_ioctl(dev, MPP_DEV_RCB_INFO, &rcb_cfg);
178 }
179 }
180 } break;
181 default:
182 break;
183 }
184
185 return 0;
186 }
187
vdpu34x_setup_statistic(Vdpu34xRegCommon * com,Vdpu34xRegStatistic * sta)188 void vdpu34x_setup_statistic(Vdpu34xRegCommon *com, Vdpu34xRegStatistic *sta)
189 {
190 com->reg011.pix_range_detection_e = 1;
191
192 memset(sta, 0, sizeof(*sta));
193
194 sta->reg256.axi_perf_work_e = 1;
195 sta->reg256.axi_perf_clr_e = 1;
196 sta->reg256.axi_cnt_type = 1;
197
198 sta->reg257.addr_align_type = 1;
199
200 /* set hurry */
201 sta->reg270.axi_rd_hurry_level = 3;
202 sta->reg270.axi_wr_hurry_level = 1;
203 sta->reg270.axi_wr_qos = 1;
204 sta->reg270.axi_rd_qos = 3;
205 sta->reg270.bus2mc_buffer_qos_level = 255;
206 sta->reg271_wr_wait_cycle_qos = 0;
207 }
208
vdpu34x_afbc_align_calc(MppBufSlots slots,MppFrame frame,RK_U32 expand)209 void vdpu34x_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand)
210 {
211 RK_U32 ver_stride = 0;
212 RK_U32 img_height = mpp_frame_get_height(frame);
213 RK_U32 img_width = mpp_frame_get_width(frame);
214 RK_U32 hdr_stride = (*compat_ext_fbc_hdr_256_odd) ?
215 (MPP_ALIGN(img_width, 256) | 256) :
216 (MPP_ALIGN(img_width, 64));
217
218 mpp_slots_set_prop(slots, SLOTS_HOR_ALIGN, mpp_align_64);
219 mpp_slots_set_prop(slots, SLOTS_VER_ALIGN, mpp_align_16);
220
221 mpp_frame_set_fbc_hdr_stride(frame, hdr_stride);
222
223 ver_stride = mpp_align_16(img_height);
224 if (*compat_ext_fbc_buf_size) {
225 ver_stride += expand;
226 }
227 mpp_frame_set_ver_stride(frame, ver_stride);
228 }
229
vdpu34x_get_colmv_size(RK_U32 width,RK_U32 height,RK_U32 ctu_size,RK_U32 colmv_bytes,RK_U32 colmv_size,RK_U32 compress)230 RK_U32 vdpu34x_get_colmv_size(RK_U32 width, RK_U32 height, RK_U32 ctu_size,
231 RK_U32 colmv_bytes, RK_U32 colmv_size, RK_U32 compress)
232 {
233 RK_U32 colmv_total_size;
234
235 if (compress) {
236 RK_U32 segment_w = (64 * colmv_size * colmv_size) / ctu_size;
237 RK_U32 segment_h = ctu_size;
238 RK_U32 seg_cnt_w = MPP_ALIGN(width, segment_w) / segment_w;
239 RK_U32 seg_cnt_h = MPP_ALIGN(height, segment_h) / segment_h;
240 RK_U32 seg_head_size = MPP_ALIGN(seg_cnt_w, 16) * seg_cnt_h;
241 RK_U32 seg_payload_size = seg_cnt_w * seg_cnt_h * 64 * colmv_bytes;
242
243 colmv_total_size = seg_head_size + seg_payload_size;
244 } else {
245 RK_U32 colmv_block_size_w = MPP_ALIGN(width, 64) / colmv_size;
246 RK_U32 colmv_block_size_h = MPP_ALIGN(height, 64) / colmv_size;
247
248 colmv_total_size = colmv_block_size_w * colmv_block_size_h * colmv_bytes;
249 }
250
251 return MPP_ALIGN(colmv_total_size, 128);
252 }
253