1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __VDPU384A_H264D_H__ 7 #define __VDPU384A_H264D_H__ 8 9 #include "vdpu384a_com.h" 10 11 12 typedef struct Vdpu384aRegH264dParam_t { 13 /* SWREG64_H26X_PARA */ 14 RK_U32 reg64_unused_bits; 15 16 /* SWREG65_STREAM_PARAM_SET */ 17 RK_U32 reg65_strm_start_bit; 18 19 /* SWREG66_STREAM_LEN */ 20 RK_U32 reg66_stream_len; 21 22 /* SWREG67_GLOBAL_LEN */ 23 RK_U32 reg67_global_len; 24 25 /* SWREG68_DPB_HOR_STRIDE */ 26 RK_U32 reg68_dpb_hor_virstride; 27 28 RK_U32 reserve_reg69_70[2]; 29 30 /* SWREG71_SCL_Y_HOR_VIRSTRIDE */ 31 RK_U32 reg71_scl_ref_hor_virstride; 32 33 /* SWREG72_SCL_UV_HOR_VIRSTRIDE */ 34 RK_U32 reg72_scl_ref_raster_uv_hor_virstride; 35 36 /* SWREG73_SCL_Y_VIRSTRIDE */ 37 RK_U32 reg73_scl_ref_virstride; 38 39 /* SWREG74_FGS_Y_HOR_VIRSTRIDE */ 40 RK_U32 reg74_fgs_ref_hor_virstride; 41 42 RK_U32 reserve_reg75_76[2]; 43 44 /* SWREG77_HEAD_HOR_STRIDE */ 45 RK_U32 reg77_pp_m_hor_stride; 46 47 /* SWREG78_PP_M_RASTER_UV_HOR_STRIDE */ 48 RK_U32 reg78_pp_m_uv_hor_stride; 49 50 /* SWREG79_PP_M_Y_STRIDE */ 51 RK_U32 reg79_pp_m_y_virstride; 52 53 /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */ 54 RK_U32 reg80_error_ref_hor_virstride; 55 56 /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */ 57 RK_U32 reg81_error_ref_raster_uv_hor_virstride; 58 59 /* SWREG82_ERROR_REF_Y_VIRSTRIDE */ 60 RK_U32 reg82_error_ref_virstride; 61 62 /* SWREG83_REF0_Y_HOR_VIRSTRIDE */ 63 RK_U32 reg83_ref0_hor_virstride; 64 65 /* SWREG84_REF0_UV_HOR_VIRSTRIDE */ 66 RK_U32 reg84_ref0_raster_uv_hor_virstride; 67 68 /* SWREG85_REF0_Y_VIRSTRIDE */ 69 RK_U32 reg85_ref0_virstride; 70 71 /* SWREG86_REF1_Y_HOR_VIRSTRIDE */ 72 RK_U32 reg86_ref1_hor_virstride; 73 74 /* SWREG87_REF1_UV_HOR_VIRSTRIDE */ 75 RK_U32 reg87_ref1_raster_uv_hor_virstride; 76 77 /* SWREG88_REF1_Y_VIRSTRIDE */ 78 RK_U32 reg88_ref1_virstride; 79 80 /* SWREG89_REF2_Y_HOR_VIRSTRIDE */ 81 RK_U32 reg89_ref2_hor_virstride; 82 83 /* SWREG90_REF2_UV_HOR_VIRSTRIDE */ 84 RK_U32 reg90_ref2_raster_uv_hor_virstride; 85 86 /* SWREG91_REF2_Y_VIRSTRIDE */ 87 RK_U32 reg91_ref2_virstride; 88 89 /* SWREG92_REF3_Y_HOR_VIRSTRIDE */ 90 RK_U32 reg92_ref3_hor_virstride; 91 92 /* SWREG93_REF3_UV_HOR_VIRSTRIDE */ 93 RK_U32 reg93_ref3_raster_uv_hor_virstride; 94 95 /* SWREG94_REF3_Y_VIRSTRIDE */ 96 RK_U32 reg94_ref3_virstride; 97 98 /* SWREG95_REF4_Y_HOR_VIRSTRIDE */ 99 RK_U32 reg95_ref4_hor_virstride; 100 101 /* SWREG96_REF4_UV_HOR_VIRSTRIDE */ 102 RK_U32 reg96_ref4_raster_uv_hor_virstride; 103 104 /* SWREG97_REF4_Y_VIRSTRIDE */ 105 RK_U32 reg97_ref4_virstride; 106 107 /* SWREG98_REF5_Y_HOR_VIRSTRIDE */ 108 RK_U32 reg98_ref5_hor_virstride; 109 110 /* SWREG99_REF5_UV_HOR_VIRSTRIDE */ 111 RK_U32 reg99_ref5_raster_uv_hor_virstride; 112 113 /* SWREG100_REF5_Y_VIRSTRIDE */ 114 RK_U32 reg100_ref5_virstride; 115 116 /* SWREG101_REF6_Y_HOR_VIRSTRIDE */ 117 RK_U32 reg101_ref6_hor_virstride; 118 119 /* SWREG102_REF6_UV_HOR_VIRSTRIDE */ 120 RK_U32 reg102_ref6_raster_uv_hor_virstride; 121 122 /* SWREG103_REF6_Y_VIRSTRIDE */ 123 RK_U32 reg103_ref6_virstride; 124 125 /* SWREG104_REF7_Y_HOR_VIRSTRIDE */ 126 RK_U32 reg104_ref7_hor_virstride; 127 128 /* SWREG105_REF7_UV_HOR_VIRSTRIDE */ 129 RK_U32 reg105_ref7_raster_uv_hor_virstride; 130 131 /* SWREG106_REF7_Y_VIRSTRIDE */ 132 RK_U32 reg106_ref7_virstride; 133 134 } Vdpu384aRegH264dParam; 135 136 typedef struct Vdpu384aRegH264dAddr_t { 137 /* SWREG168_DECOUT_BASE */ 138 RK_U32 reg168_dpb_decout_base; 139 140 /* SWREG169_ERROR_REF_BASE */ 141 RK_U32 reg169_error_ref_base; 142 143 /* SWREG170_185_REF0_15_BASE */ 144 RK_U32 reg170_185_ref_base[16]; 145 146 RK_U32 reserve_reg186_191[6]; 147 148 /* SWREG192_PAYLOAD_ST_CUR_BASE */ 149 RK_U32 reg192_dpb_payload64x4_st_cur_base; 150 151 /* SWREG193_FBC_PAYLOAD_OFFSET */ 152 RK_U32 reg193_dpb_fbc64x4_payload_offset; 153 154 /* SWREG194_PAYLOAD_ST_ERROR_REF_BASE */ 155 RK_U32 reg194_payload_st_error_ref_base; 156 157 /* SWREG195_210_PAYLOAD_ST_REF0_15_BASE */ 158 RK_U32 reg195_210_payload_st_ref_base[16]; 159 160 RK_U32 reserve_reg211_215[5]; 161 162 /* SWREG216_COLMV_CUR_BASE */ 163 RK_U32 reg216_colmv_cur_base; 164 165 /* SWREG217_232_COLMV_REF0_15_BASE */ 166 RK_U32 reg217_232_colmv_ref_base[16]; 167 168 } Vdpu384aRegH264dAddr; 169 170 171 typedef struct Vdpu384aH264dRegSet_t { 172 Vdpu384aRegVersion reg_version; /* 0 */ 173 Vdpu384aCtrlReg ctrl_regs; /* 8-30 */ 174 Vdpu384aRegCommonAddr common_addr; /* 128-134, 140-161 */ 175 // Vdpu384aRegNew new_add; /* 320-359 */ 176 177 Vdpu384aRegH264dParam h264d_paras; /* 64-74, 80-106 */ 178 Vdpu384aRegH264dAddr h264d_addrs; /* 168-185, 192-210, 216-232 */ 179 } Vdpu384aH264dRegSet; 180 181 #endif /* __VDPU384A_H264D_H__ */ 182