1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2 /* 3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __VDPU383_COM_H__ 7 #define __VDPU383_COM_H__ 8 9 #include "mpp_device.h" 10 #include "mpp_buf_slot.h" 11 12 #define OFFSET_CTRL_REGS (8 * sizeof(RK_U32)) 13 #define OFFSET_COMMON_ADDR_REGS (128 * sizeof(RK_U32)) 14 #define OFFSET_COM_NEW_REGS (320 * sizeof(RK_U32)) 15 #define OFFSET_CODEC_PARAS_REGS (64 * sizeof(RK_U32)) 16 #define OFFSET_CODEC_ADDR_REGS (168 * sizeof(RK_U32)) 17 #define OFFSET_INTERRUPT_REGS (15 * sizeof(RK_U32)) 18 19 #define RCB_ALLINE_SIZE (64) 20 21 #define MPP_RCB_BYTES(bits) MPP_ALIGN((bits + 7) / 8, RCB_ALLINE_SIZE) 22 23 // #define DUMP_VDPU383_DATAS 24 25 typedef enum Vdpu383RcbType_e { 26 RCB_STRMD_ROW, 27 RCB_STRMD_TILE_ROW, 28 RCB_INTER_ROW, 29 RCB_INTER_TILE_ROW, 30 RCB_INTRA_ROW, 31 RCB_INTRA_TILE_ROW, 32 RCB_FILTERD_ROW, 33 RCB_FILTERD_PROTECT_ROW, 34 RCB_FILTERD_TILE_ROW, 35 RCB_FILTERD_TILE_COL, 36 RCB_FILTERD_AV1_UP_TILE_COL, 37 38 RCB_BUF_COUNT, 39 } Vdpu383RcbType; 40 41 typedef enum Vdpu383_RCB_SET_MODE_E { 42 RCB_SET_BY_SIZE_SORT_MODE, 43 RCB_SET_BY_PRIORITY_MODE, 44 } Vdpu383RcbSetMode_e; 45 46 typedef struct Vdpu383RegVersion_t { 47 struct SWREG0_ID { 48 RK_U32 minor_ver : 8; 49 RK_U32 major_ver : 8; 50 RK_U32 prod_num : 16; 51 } reg0; 52 53 } Vdpu383RegVersion; 54 55 typedef struct Vdpu383CtrlReg_t { 56 /* SWREG8_DEC_MODE */ 57 RK_U32 reg8_dec_mode; 58 59 struct SWREG9_IMPORTANT_EN { 60 RK_U32 fbc_e : 1; 61 RK_U32 tile_e : 1; 62 RK_U32 reserve0 : 2; 63 RK_U32 buf_empty_en : 1; 64 RK_U32 scale_down_en : 1; 65 RK_U32 reserve1 : 1; 66 RK_U32 pix_range_det_e : 1; 67 RK_U32 av1_fgs_en : 1; 68 RK_U32 reserve2 : 7; 69 RK_U32 line_irq_en : 1; 70 RK_U32 out_cbcr_swap : 1; 71 RK_U32 fbc_force_uncompress : 1; 72 RK_U32 fbc_sparse_mode : 1; 73 RK_U32 reserve3 : 12; 74 } reg9; 75 76 struct SWREG10_BLOCK_GATING_EN { 77 RK_U32 strmd_auto_gating_e : 1; 78 RK_U32 inter_auto_gating_e : 1; 79 RK_U32 intra_auto_gating_e : 1; 80 RK_U32 transd_auto_gating_e : 1; 81 RK_U32 recon_auto_gating_e : 1; 82 RK_U32 filterd_auto_gating_e : 1; 83 RK_U32 bus_auto_gating_e : 1; 84 RK_U32 ctrl_auto_gating_e : 1; 85 RK_U32 rcb_auto_gating_e : 1; 86 RK_U32 err_prc_auto_gating_e : 1; 87 RK_U32 reserve0 : 22; 88 } reg10; 89 90 struct SWREG11_CFG_PARA { 91 RK_U32 reserve0 : 9; 92 RK_U32 dec_timeout_dis : 1; 93 RK_U32 reserve1 : 22; 94 } reg11; 95 96 struct SWREG12_CACHE_HASH_MASK { 97 RK_U32 reserve0 : 7; 98 RK_U32 cache_hash_mask : 25; 99 } reg12; 100 101 /* SWREG13_CORE_TIMEOUT_THRESHOLD */ 102 RK_U32 reg13_core_timeout_threshold; 103 104 struct SWREG14_LINE_IRQ_CTRL { 105 RK_U32 dec_line_irq_step : 16; 106 RK_U32 dec_line_offset_y_st : 16; 107 } reg14; 108 109 /* copy from llp, media group add */ 110 struct SWREG15_IRQ_STA { 111 RK_U32 rkvdec_frame_rdy_sta : 1; 112 RK_U32 rkvdec_strm_error_sta : 1; 113 RK_U32 rkvdec_core_timeout_sta : 1; 114 RK_U32 rkvdec_ip_timeout_sta : 1; 115 RK_U32 rkvdec_bus_error_sta : 1; 116 RK_U32 rkvdec_buffer_empty_sta : 1; 117 RK_U32 rkvdec_colmv_ref_error_sta : 1; 118 RK_U32 rkvdec_error_spread_sta : 1; 119 RK_U32 create_core_timeout_sta : 1; 120 RK_U32 wlast_miss_match_sta : 1; 121 RK_U32 rkvdec_core_rst_rdy_sta : 1; 122 RK_U32 rkvdec_ip_rst_rdy_sta : 1; 123 RK_U32 force_busidle_rdy_sta : 1; 124 RK_U32 ltb_pause_rdy_sta : 1; 125 RK_U32 ltb_end_flag : 1; 126 RK_U32 unsupport_decmode_error_sta : 1; 127 RK_U32 wmask_bits : 15; 128 RK_U32 reserve0 : 1; 129 } reg15; 130 131 struct SWREG16_ERROR_CTRL_SET { 132 RK_U32 error_proc_disable : 1; 133 RK_U32 reserve0 : 7; 134 RK_U32 error_spread_disable : 1; 135 RK_U32 reserve1 : 15; 136 RK_U32 roi_error_ctu_cal_en : 1; 137 RK_U32 reserve2 : 7; 138 } reg16; 139 140 struct SWREG17_ERR_ROI_CTU_OFFSET_START { 141 RK_U32 roi_x_ctu_offset_st : 12; 142 RK_U32 reserve0 : 4; 143 RK_U32 roi_y_ctu_offset_st : 12; 144 RK_U32 reserve1 : 4; 145 } reg17; 146 147 struct SWREG18_ERR_ROI_CTU_OFFSET_END { 148 RK_U32 roi_x_ctu_offset_end : 12; 149 RK_U32 reserve0 : 4; 150 RK_U32 roi_y_ctu_offset_end : 12; 151 RK_U32 reserve1 : 4; 152 } reg18; 153 154 struct SWREG19_ERROR_REF_INFO { 155 RK_U32 avs2_ref_error_field : 1; 156 RK_U32 avs2_ref_error_topfield : 1; 157 RK_U32 ref_error_topfield_used : 1; 158 RK_U32 ref_error_botfield_used : 1; 159 RK_U32 reserve0 : 28; 160 } reg19; 161 162 /* SWREG20_CABAC_ERROR_EN_LOWBITS */ 163 RK_U32 reg20_cabac_error_en_lowbits; 164 165 /* SWREG21_CABAC_ERROR_EN_HIGHBITS */ 166 RK_U32 reg21_cabac_error_en_highbits; 167 168 RK_U32 reserve_reg22; 169 170 struct SWREG23_INVALID_PIXEL_FILL { 171 RK_U32 fill_y : 10; 172 RK_U32 fill_u : 10; 173 RK_U32 fill_v : 10; 174 RK_U32 reserve0 : 2; 175 } reg23; 176 177 RK_U32 reserve_reg24_26[3]; 178 179 struct SWREG27_ALIGN_EN { 180 RK_U32 reserve0 : 4; 181 RK_U32 ctu_align_wr_en : 1; 182 RK_U32 reserve1 : 27; 183 } reg27; 184 185 struct SWREG28_DEBUG_PERF_LATENCY_CTRL0 { 186 RK_U32 axi_perf_work_e : 1; 187 RK_U32 reserve0 : 2; 188 RK_U32 axi_cnt_type : 1; 189 RK_U32 rd_latency_id : 8; 190 RK_U32 reserve1 : 4; 191 RK_U32 rd_latency_thr : 12; 192 RK_U32 reserve2 : 4; 193 } reg28; 194 195 struct SWREG29_DEBUG_PERF_LATENCY_CTRL1 { 196 RK_U32 addr_align_type : 2; 197 RK_U32 ar_cnt_id_type : 1; 198 RK_U32 aw_cnt_id_type : 1; 199 RK_U32 ar_count_id : 8; 200 RK_U32 reserve0 : 4; 201 RK_U32 aw_count_id : 8; 202 RK_U32 rd_band_width_mode : 1; 203 RK_U32 reserve1 : 7; 204 } reg29; 205 206 struct SWREG30_QOS_CTRL { 207 RK_U32 axi_wr_qos_level : 4; 208 RK_U32 reserve0 : 4; 209 RK_U32 axi_wr_qos : 4; 210 RK_U32 reserve1 : 4; 211 RK_U32 axi_rd_qos_level : 4; 212 RK_U32 reserve2 : 4; 213 RK_U32 axi_rd_qos : 4; 214 RK_U32 reserve3 : 4; 215 } reg30; 216 } Vdpu383CtrlReg; 217 218 typedef struct Vdpu383RegCommonAddr_t { 219 /* SWREG128_STRM_BASE */ 220 RK_U32 reg128_strm_base; 221 222 /* SWREG129_RPS_BASE */ 223 RK_U32 reg129_rps_base; 224 225 /* SWREG130_CABACTBL_BASE */ 226 RK_U32 reg130_cabactbl_base; 227 228 /* SWREG131_GBL_BASE */ 229 RK_U32 reg131_gbl_base; 230 231 /* SWREG132_SCANLIST_ADDR */ 232 RK_U32 reg132_scanlist_addr; 233 234 /* SWREG133_SCL_BASE */ 235 RK_U32 reg133_scale_down_base; 236 237 /* SWREG134_FGS_BASE */ 238 RK_U32 reg134_fgs_base; 239 240 RK_U32 reserve_reg135_139[5]; 241 242 /* SWREG140_RCB_STRMD_ROW_OFFSET */ 243 RK_U32 reg140_rcb_strmd_row_offset; 244 245 /* SWREG141_RCB_STRMD_ROW_LEN */ 246 RK_U32 reg141_rcb_strmd_row_len; 247 248 /* SWREG142_RCB_STRMD_TILE_ROW_OFFSET */ 249 RK_U32 reg142_rcb_strmd_tile_row_offset; 250 251 /* SWREG143_RCB_STRMD_TILE_ROW_LEN */ 252 RK_U32 reg143_rcb_strmd_tile_row_len; 253 254 /* SWREG144_RCB_INTER_ROW_OFFSET */ 255 RK_U32 reg144_rcb_inter_row_offset; 256 257 /* SWREG145_RCB_INTER_ROW_LEN */ 258 RK_U32 reg145_rcb_inter_row_len; 259 260 /* SWREG146_RCB_INTER_TILE_ROW_OFFSET */ 261 RK_U32 reg146_rcb_inter_tile_row_offset; 262 263 /* SWREG147_RCB_INTER_TILE_ROW_LEN */ 264 RK_U32 reg147_rcb_inter_tile_row_len; 265 266 /* SWREG148_RCB_INTRA_ROW_OFFSET */ 267 RK_U32 reg148_rcb_intra_row_offset; 268 269 /* SWREG149_RCB_INTRA_ROW_LEN */ 270 RK_U32 reg149_rcb_intra_row_len; 271 272 /* SWREG150_RCB_INTRA_TILE_ROW_OFFSET */ 273 RK_U32 reg150_rcb_intra_tile_row_offset; 274 275 /* SWREG151_RCB_INTRA_TILE_ROW_LEN */ 276 RK_U32 reg151_rcb_intra_tile_row_len; 277 278 /* SWREG152_RCB_FILTERD_ROW_OFFSET */ 279 RK_U32 reg152_rcb_filterd_row_offset; 280 281 /* SWREG153_RCB_FILTERD_ROW_LEN */ 282 RK_U32 reg153_rcb_filterd_row_len; 283 284 /* SWREG154_RCB_FILTERD_PROTECT_ROW_OFFSET */ 285 RK_U32 reg154_rcb_filterd_protect_row_offset; 286 287 /* SWREG155_RCB_FILTERD_PROTECT_ROW_LEN */ 288 RK_U32 reg155_rcb_filterd_protect_row_len; 289 290 /* SWREG156_RCB_FILTERD_TILE_ROW_OFFSET */ 291 RK_U32 reg156_rcb_filterd_tile_row_offset; 292 293 /* SWREG157_RCB_FILTERD_TILE_ROW_LEN */ 294 RK_U32 reg157_rcb_filterd_tile_row_len; 295 296 /* SWREG158_RCB_FILTERD_TILE_COL_OFFSET */ 297 RK_U32 reg158_rcb_filterd_tile_col_offset; 298 299 /* SWREG159_RCB_FILTERD_TILE_COL_LEN */ 300 RK_U32 reg159_rcb_filterd_tile_col_len; 301 302 /* SWREG160_RCB_FILTERD_AV1_UPSCALE_TILE_COL_OFFSET */ 303 RK_U32 reg160_rcb_filterd_av1_upscale_tile_col_offset; 304 305 /* SWREG161_RCB_FILTERD_AV1_UPSCALE_TILE_COL_LEN */ 306 RK_U32 reg161_rcb_filterd_av1_upscale_tile_col_len; 307 308 } Vdpu383RegCommonAddr; 309 310 typedef struct Vdpu383RegCommParas_t { 311 /* SWREG64_H26X_PARA */ 312 RK_U32 reg64_unused_bits; 313 314 /* SWREG65_STREAM_PARAM_SET */ 315 RK_U32 reg65_strm_start_bit; 316 317 /* SWREG66_STREAM_LEN */ 318 RK_U32 reg66_stream_len; 319 320 /* SWREG67_GLOBAL_LEN */ 321 RK_U32 reg67_global_len; 322 323 /* SWREG68_HOR_STRIDE */ 324 RK_U32 reg68_hor_virstride; 325 326 /* SWREG69_RASTER_UV_HOR_STRIDE */ 327 RK_U32 reg69_raster_uv_hor_virstride; 328 329 /* SWREG70_Y_STRIDE */ 330 RK_U32 reg70_y_virstride; 331 332 /* SWREG71_SCL_Y_HOR_VIRSTRIDE */ 333 RK_U32 reg71_scl_ref_hor_virstride; 334 335 /* SWREG72_SCL_UV_HOR_VIRSTRIDE */ 336 RK_U32 reg72_scl_ref_raster_uv_hor_virstride; 337 338 /* SWREG73_SCL_Y_VIRSTRIDE */ 339 RK_U32 reg73_scl_ref_virstride; 340 341 /* SWREG74_FGS_Y_HOR_VIRSTRIDE */ 342 RK_U32 reg74_fgs_ref_hor_virstride; 343 344 RK_U32 reserve_reg75_79[5]; 345 346 /* SWREG80_ERROR_REF_Y_HOR_VIRSTRIDE */ 347 RK_U32 reg80_error_ref_hor_virstride; 348 349 /* SWREG81_ERROR_REF_UV_HOR_VIRSTRIDE */ 350 RK_U32 reg81_error_ref_raster_uv_hor_virstride; 351 352 /* SWREG82_ERROR_REF_Y_VIRSTRIDE */ 353 RK_U32 reg82_error_ref_virstride; 354 355 /* SWREG83_REF0_Y_HOR_VIRSTRIDE */ 356 RK_U32 reg83_ref0_hor_virstride; 357 358 /* SWREG84_REF0_UV_HOR_VIRSTRIDE */ 359 RK_U32 reg84_ref0_raster_uv_hor_virstride; 360 361 /* SWREG85_REF0_Y_VIRSTRIDE */ 362 RK_U32 reg85_ref0_virstride; 363 364 /* SWREG86_REF1_Y_HOR_VIRSTRIDE */ 365 RK_U32 reg86_ref1_hor_virstride; 366 367 /* SWREG87_REF1_UV_HOR_VIRSTRIDE */ 368 RK_U32 reg87_ref1_raster_uv_hor_virstride; 369 370 /* SWREG88_REF1_Y_VIRSTRIDE */ 371 RK_U32 reg88_ref1_virstride; 372 373 /* SWREG89_REF2_Y_HOR_VIRSTRIDE */ 374 RK_U32 reg89_ref2_hor_virstride; 375 376 /* SWREG90_REF2_UV_HOR_VIRSTRIDE */ 377 RK_U32 reg90_ref2_raster_uv_hor_virstride; 378 379 /* SWREG91_REF2_Y_VIRSTRIDE */ 380 RK_U32 reg91_ref2_virstride; 381 382 /* SWREG92_REF3_Y_HOR_VIRSTRIDE */ 383 RK_U32 reg92_ref3_hor_virstride; 384 385 /* SWREG93_REF3_UV_HOR_VIRSTRIDE */ 386 RK_U32 reg93_ref3_raster_uv_hor_virstride; 387 388 /* SWREG94_REF3_Y_VIRSTRIDE */ 389 RK_U32 reg94_ref3_virstride; 390 391 /* SWREG95_REF4_Y_HOR_VIRSTRIDE */ 392 RK_U32 reg95_ref4_hor_virstride; 393 394 /* SWREG96_REF4_UV_HOR_VIRSTRIDE */ 395 RK_U32 reg96_ref4_raster_uv_hor_virstride; 396 397 /* SWREG97_REF4_Y_VIRSTRIDE */ 398 RK_U32 reg97_ref4_virstride; 399 400 /* SWREG98_REF5_Y_HOR_VIRSTRIDE */ 401 RK_U32 reg98_ref5_hor_virstride; 402 403 /* SWREG99_REF5_UV_HOR_VIRSTRIDE */ 404 RK_U32 reg99_ref5_raster_uv_hor_virstride; 405 406 /* SWREG100_REF5_Y_VIRSTRIDE */ 407 RK_U32 reg100_ref5_virstride; 408 409 /* SWREG101_REF6_Y_HOR_VIRSTRIDE */ 410 RK_U32 reg101_ref6_hor_virstride; 411 412 /* SWREG102_REF6_UV_HOR_VIRSTRIDE */ 413 RK_U32 reg102_ref6_raster_uv_hor_virstride; 414 415 /* SWREG103_REF6_Y_VIRSTRIDE */ 416 RK_U32 reg103_ref6_virstride; 417 418 /* SWREG104_REF7_Y_HOR_VIRSTRIDE */ 419 RK_U32 reg104_ref7_hor_virstride; 420 421 /* SWREG105_REF7_UV_HOR_VIRSTRIDE */ 422 RK_U32 reg105_ref7_raster_uv_hor_virstride; 423 424 /* SWREG106_REF7_Y_VIRSTRIDE */ 425 RK_U32 reg106_ref7_virstride; 426 427 } Vdpu383RegCommParas; 428 429 typedef struct Vdpu383RegNew_t { 430 struct SWREG320_IDLE_FLAG { 431 RK_U32 reserve0 : 24; 432 RK_U32 rkvdec_bus_idle_flag : 1; 433 RK_U32 reserve1 : 7; 434 } reg320; 435 436 RK_U32 reserve_reg321; 437 438 /* SWREG322_PERF_MONITOR */ 439 RK_U32 reg322_perf_rd_max_latency_num; 440 441 /* SWREG323_PERF_MONITOR */ 442 RK_U32 reg323_perf_rd_latency_samp_num; 443 444 /* SWREG324_PERF_MONITOR */ 445 RK_U32 reg324_perf_rd_latency_acc_sum; 446 447 /* SWREG325_PERF_MONITOR */ 448 RK_U32 reg325_perf_rd_axi_total_byte; 449 450 /* SWREG326_PERF_MONITOR */ 451 RK_U32 reg326_perf_wr_axi_total_bytes; 452 453 /* SWREG327_PERF_MONITOR */ 454 RK_U32 reg327_perf_working_cnt; 455 456 RK_U32 reserve_reg328_336[9]; 457 458 /* SWREG337_REFLIST_IDX_USED */ 459 RK_U32 reg337_inter_sw_reflst_idx_use; 460 461 RK_U32 reserve_reg338_348[11]; 462 463 /* SWREG349_PAYLOAD_CNT */ 464 RK_U32 reg349_filterd_payload_total_cnt; 465 466 struct SWREG350_WR_OFFSET { 467 RK_U32 filterd_report_offsety : 16; 468 RK_U32 filterd_report_offsetx : 16; 469 } reg350; 470 471 struct SWREG351_MAX_PIX { 472 RK_U32 filterd_max_y : 10; 473 RK_U32 filterd_max_u : 10; 474 RK_U32 filterd_max_v : 10; 475 RK_U32 reserve0 : 2; 476 } reg351; 477 478 struct SWREG352_MIN_PIX { 479 RK_U32 filterd_min_y : 10; 480 RK_U32 filterd_min_u : 10; 481 RK_U32 filterd_min_v : 10; 482 RK_U32 reserve0 : 2; 483 } reg352; 484 485 /* SWREG353_WR_LINE_NUM */ 486 RK_U32 reg353_filterd_line_irq_offsety; 487 488 RK_U32 reserve_reg354_355[2]; 489 490 struct SWREG356_RCB_RW_SUM { 491 RK_U32 rcb_rd_sum_chk : 8; 492 RK_U32 rcb_wr_sum_chk : 8; 493 RK_U32 reserve0 : 16; 494 } reg356; 495 496 RK_U32 reserve_reg357; 497 498 struct SWREG358_ERR_CTU_NUM0 { 499 RK_U32 error_ctu_num : 24; 500 RK_U32 roi_error_ctu_num_lowbit : 8; 501 } reg358; 502 503 /* SWREG359_ERR_CTU_NUM1 */ 504 RK_U32 reg359_roi_error_ctu_num_highbit; 505 506 } Vdpu383RegNew; 507 508 typedef struct Vdpu383RegLlp_t { 509 struct SWREG0_LINK_MODE { 510 RK_U32 llp_mmu_zap_cache_dis : 1; 511 RK_U32 reserve0 : 15; 512 RK_U32 core_work_mode : 1; 513 RK_U32 ccu_core_work_mode : 1; 514 RK_U32 reserve1 : 3; 515 RK_U32 ltb_pause_flag : 1; 516 RK_U32 reserve2 : 10; 517 } reg0; 518 519 struct SWREG1_CFG_START_ADDR { 520 RK_U32 reserve0 : 4; 521 RK_U32 reg_cfg_addr : 28; 522 } reg1; 523 524 struct SWREG2_LINK_MODE { 525 RK_U32 pre_frame_num : 30; 526 RK_U32 reserve0 : 1; 527 RK_U32 link_mode : 1; 528 } reg2; 529 530 /* SWREG3_CONFIG_DONE */ 531 RK_U32 reg3_done; 532 533 /* SWREG4_DECODERED_NUM */ 534 RK_U32 reg4_num; 535 536 /* SWREG5_DEC_TOTAL_NUM */ 537 RK_U32 reg5_total_num; 538 539 /* SWREG6_LINK_MODE_EN */ 540 RK_U32 reg6_mode_en; 541 542 /* SWREG7_SKIP_NUM */ 543 RK_U32 reg7_num; 544 545 /* SWREG8_CUR_LTB_IDX */ 546 RK_U32 reg8_ltb_idx; 547 548 RK_U32 reserve_reg9_15[7]; 549 550 /* SWREG16_DEC_E */ 551 RK_U32 reg16_dec_e; 552 553 /* SWREG17_SOFT_RST */ 554 RK_U32 reg17_rkvdec_ip_rst_p; 555 556 struct SWREG18_IRQ { 557 RK_U32 rkvdec_irq : 1; 558 RK_U32 rkvdec_line_irq : 1; 559 RK_U32 reserve0 : 14; 560 RK_U32 wmask : 2; 561 RK_U32 reserve1 : 14; 562 } reg18; 563 564 struct SWREG19_STA { 565 RK_U32 rkvdec_frame_rdy_sta : 1; 566 RK_U32 rkvdec_strm_error_sta : 1; 567 RK_U32 rkvdec_core_timeout_sta : 1; 568 RK_U32 rkvdec_ip_timeout_sta : 1; 569 RK_U32 rkvdec_bus_error_sta : 1; 570 RK_U32 rkvdec_buffer_empty_sta : 1; 571 RK_U32 rkvdec_colmv_ref_error_sta : 1; 572 RK_U32 rkvdec_error_spread_sta : 1; 573 RK_U32 create_core_timeout_sta : 1; 574 RK_U32 wlast_miss_match_sta : 1; 575 RK_U32 rkvdec_core_rst_rdy_sta : 1; 576 RK_U32 rkvdec_ip_rst_rdy_sta : 1; 577 RK_U32 force_busidle_rdy_sta : 1; 578 RK_U32 ltb_pause_rdy_sta : 1; 579 RK_U32 ltb_end_flag : 1; 580 RK_U32 unsupport_decmode_error_sta : 1; 581 RK_U32 wmask_bits : 15; 582 RK_U32 reserve0 : 1; 583 } reg19; 584 585 RK_U32 reserve_reg20; 586 587 /* SWREG21_IP_TIMEOUT_THRESHOD */ 588 RK_U32 reg21_ip_timeout_threshold; 589 590 struct SWREG22_IP_EN { 591 RK_U32 ip_timeout_pause_flag : 1; 592 RK_U32 reserve0 : 3; 593 RK_U32 auto_reset_dis : 1; 594 RK_U32 reserve1 : 3; 595 RK_U32 force_busidle_req_flag : 1; 596 RK_U32 reserve2 : 3; 597 RK_U32 bus_clkgate_dis : 1; 598 RK_U32 ctrl_clkgate_dis : 1; 599 RK_U32 reserve3 : 1; 600 RK_U32 irq_dis : 1; 601 RK_U32 wid_reorder_dis : 1; 602 RK_U32 reserve4 : 7; 603 RK_U32 clk_cru_mode : 2; 604 RK_U32 reserve5 : 5; 605 RK_U32 mmu_sel : 1; 606 } reg22; 607 608 struct SWREG23_IN_OUT { 609 RK_U32 endian : 1; 610 RK_U32 swap32_e : 1; 611 RK_U32 swap64_e : 1; 612 RK_U32 str_endian : 1; 613 RK_U32 str_swap32_e : 1; 614 RK_U32 str_swap64_e : 1; 615 RK_U32 reserve0 : 26; 616 } reg23; 617 618 /* SWREG24_EXTRA_STRM_BASE */ 619 RK_U32 reg24_extra_stream_base; 620 621 /* SWREG25_EXTRA_STRM_LEN */ 622 RK_U32 reg25_extra_stream_len; 623 624 /* SWREG26_EXTRA_STRM_PARA_SET */ 625 RK_U32 reg26_extra_strm_start_bit; 626 627 /* SWREG27_BUF_EMPTY_RESTART */ 628 RK_U32 reg27_buf_emtpy_restart_p; 629 630 /* SWREG28_RCB_BASE */ 631 RK_U32 reg28_rcb_base; 632 633 } Vdpu383RegLlp; 634 635 typedef struct Vdpu383RcbInfo_t { 636 RK_U32 reg_idx; 637 RK_S32 size; 638 RK_S32 offset; 639 } Vdpu383RcbInfo; 640 641 #ifdef __cplusplus 642 extern "C" { 643 #endif 644 645 RK_S32 vdpu383_get_rcb_buf_size(Vdpu383RcbInfo *info, RK_S32 width, RK_S32 height); 646 void vdpu383_setup_rcb(Vdpu383RegCommonAddr *reg, MppDev dev, MppBuffer buf, Vdpu383RcbInfo *info); 647 RK_S32 vdpu383_compare_rcb_size(const void *a, const void *b); 648 void vdpu383_setup_statistic(Vdpu383CtrlReg *com); 649 void vdpu383_afbc_align_calc(MppBufSlots slots, MppFrame frame, RK_U32 expand); 650 RK_S32 vdpu383_set_rcbinfo(MppDev dev, Vdpu383RcbInfo *rcb_info); 651 void vdpu383_setup_down_scale(MppFrame frame, MppDev dev, Vdpu383CtrlReg *com, void* comParas); 652 void vdpu383_update_thumbnail_frame_info(MppFrame frame); 653 654 #ifdef DUMP_VDPU383_DATAS 655 extern RK_U32 dump_cur_frame; 656 extern char dump_cur_dir[128]; 657 extern char dump_cur_fname_path[512]; 658 659 MPP_RET flip_string(char *str); 660 MPP_RET dump_data_to_file(char *fname_path, void *data, RK_U32 data_bit_size, 661 RK_U32 line_bits, RK_U32 big_end); 662 #endif 663 664 #ifdef __cplusplus 665 } 666 #endif 667 668 #endif /* __VDPU383_COM_H__ */ 669