1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2 /*
3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4 */
5
6 #define MODULE_TAG "hal_h264d_vdpu383"
7
8 #include <string.h>
9
10 #include "mpp_env.h"
11 #include "mpp_mem.h"
12 #include "mpp_common.h"
13 #include "mpp_bitput.h"
14 #include "mpp_buffer_impl.h"
15
16 #include "hal_h264d_global.h"
17 #include "hal_h264d_vdpu383.h"
18 #include "vdpu383_h264d.h"
19 #include "mpp_dec_cb_param.h"
20
21 /* Number registers for the decoder */
22 #define DEC_VDPU383_REGISTERS 276
23
24 #define VDPU383_CABAC_TAB_SIZE (928*4 + 128) /* bytes */
25 #define VDPU383_SPSPPS_SIZE (168 + 128) /* bytes */
26 #define VDPU383_RPS_SIZE (128 + 128 + 128) /* bytes */
27 #define VDPU383_SCALING_LIST_SIZE (6*16+2*64 + 128) /* bytes */
28 #define VDPU383_ERROR_INFO_SIZE (256*144*4) /* bytes */
29 #define H264_CTU_SIZE 16
30
31 #define VDPU383_CABAC_TAB_ALIGNED_SIZE (MPP_ALIGN(VDPU383_CABAC_TAB_SIZE, SZ_4K))
32 #define VDPU383_ERROR_INFO_ALIGNED_SIZE (0)
33 #define VDPU383_SPSPPS_ALIGNED_SIZE (MPP_ALIGN(VDPU383_SPSPPS_SIZE, SZ_4K))
34 #define VDPU383_RPS_ALIGNED_SIZE (MPP_ALIGN(VDPU383_RPS_SIZE, SZ_4K))
35 #define VDPU383_SCALING_LIST_ALIGNED_SIZE (MPP_ALIGN(VDPU383_SCALING_LIST_SIZE, SZ_4K))
36 #define VDPU383_STREAM_INFO_SET_SIZE (VDPU383_SPSPPS_ALIGNED_SIZE + \
37 VDPU383_RPS_ALIGNED_SIZE + \
38 VDPU383_SCALING_LIST_ALIGNED_SIZE)
39
40 #define VDPU383_CABAC_TAB_OFFSET (0)
41 #define VDPU383_ERROR_INFO_OFFSET (VDPU383_CABAC_TAB_OFFSET + VDPU383_CABAC_TAB_ALIGNED_SIZE)
42 #define VDPU383_STREAM_INFO_OFFSET_BASE (VDPU383_ERROR_INFO_OFFSET + VDPU383_ERROR_INFO_ALIGNED_SIZE)
43 #define VDPU383_SPSPPS_OFFSET(pos) (VDPU383_STREAM_INFO_OFFSET_BASE + (VDPU383_STREAM_INFO_SET_SIZE * pos))
44 #define VDPU383_RPS_OFFSET(pos) (VDPU383_SPSPPS_OFFSET(pos) + VDPU383_SPSPPS_ALIGNED_SIZE)
45 #define VDPU383_SCALING_LIST_OFFSET(pos) (VDPU383_RPS_OFFSET(pos) + VDPU383_RPS_ALIGNED_SIZE)
46 #define VDPU383_INFO_BUFFER_SIZE(cnt) (VDPU383_STREAM_INFO_OFFSET_BASE + (VDPU383_STREAM_INFO_SET_SIZE * cnt))
47
48 #define VDPU383_SPS_PPS_LEN (MPP_ALIGN(1338, 128) / 8) // byte, 1338 bit
49
50 #define SET_REF_INFO(regs, index, field, value)\
51 do{ \
52 switch(index){\
53 case 0: regs.reg99.ref0_##field = value; break;\
54 case 1: regs.reg99.ref1_##field = value; break;\
55 case 2: regs.reg99.ref2_##field = value; break;\
56 case 3: regs.reg99.ref3_##field = value; break;\
57 case 4: regs.reg100.ref4_##field = value; break;\
58 case 5: regs.reg100.ref5_##field = value; break;\
59 case 6: regs.reg100.ref6_##field = value; break;\
60 case 7: regs.reg100.ref7_##field = value; break;\
61 case 8: regs.reg101.ref8_##field = value; break;\
62 case 9: regs.reg101.ref9_##field = value; break;\
63 case 10: regs.reg101.ref10_##field = value; break;\
64 case 11: regs.reg101.ref11_##field = value; break;\
65 case 12: regs.reg102.ref12_##field = value; break;\
66 case 13: regs.reg102.ref13_##field = value; break;\
67 case 14: regs.reg102.ref14_##field = value; break;\
68 case 15: regs.reg102.ref15_##field = value; break;\
69 default: break;}\
70 }while(0)
71
72 #define VDPU383_FAST_REG_SET_CNT 3
73
74 typedef struct h264d_rkv_buf_t {
75 RK_U32 valid;
76 Vdpu383H264dRegSet *regs;
77 } H264dRkvBuf_t;
78
79 typedef struct Vdpu383H264dRegCtx_t {
80 RK_U8 spspps[VDPU383_SPS_PPS_LEN];
81 RK_U8 rps[VDPU383_RPS_SIZE];
82 RK_U8 sclst[VDPU383_SCALING_LIST_SIZE];
83
84 MppBuffer bufs;
85 RK_S32 bufs_fd;
86 void *bufs_ptr;
87 RK_U32 offset_cabac;
88 RK_U32 offset_errinfo;
89 RK_U32 offset_spspps[VDPU383_FAST_REG_SET_CNT];
90 RK_U32 offset_rps[VDPU383_FAST_REG_SET_CNT];
91 RK_U32 offset_sclst[VDPU383_FAST_REG_SET_CNT];
92
93 H264dRkvBuf_t reg_buf[VDPU383_FAST_REG_SET_CNT];
94
95 RK_U32 spspps_offset;
96 RK_U32 rps_offset;
97 RK_U32 sclst_offset;
98
99 RK_S32 width;
100 RK_S32 height;
101 /* rcb buffers info */
102 RK_U32 bit_depth;
103 RK_U32 mbaff;
104 RK_U32 chroma_format_idc;
105
106 RK_S32 rcb_buf_size;
107 Vdpu383RcbInfo rcb_info[RCB_BUF_COUNT];
108 MppBuffer rcb_buf[VDPU383_FAST_REG_SET_CNT];
109
110 Vdpu383H264dRegSet *regs;
111 HalBufs origin_bufs;
112 } Vdpu383H264dRegCtx;
113
114 MPP_RET vdpu383_h264d_deinit(void *hal);
rkv_ver_align(RK_U32 val)115 static RK_U32 rkv_ver_align(RK_U32 val)
116 {
117 return MPP_ALIGN(val, 16);
118 }
119
rkv_len_align(RK_U32 val)120 static RK_U32 rkv_len_align(RK_U32 val)
121 {
122 return (2 * MPP_ALIGN(val, 16));
123 }
124
rkv_len_align_422(RK_U32 val)125 static RK_U32 rkv_len_align_422(RK_U32 val)
126 {
127 return ((5 * MPP_ALIGN(val, 16)) / 2);
128 }
129
vdpu383_setup_scale_origin_bufs(H264dHalCtx_t * p_hal,MppFrame mframe)130 static MPP_RET vdpu383_setup_scale_origin_bufs(H264dHalCtx_t *p_hal, MppFrame mframe)
131 {
132 Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
133 /* for 8K FrameBuf scale mode */
134 size_t origin_buf_size = 0;
135
136 origin_buf_size = mpp_frame_get_buf_size(mframe);
137
138 if (!origin_buf_size) {
139 mpp_err_f("origin_bufs get buf size failed\n");
140 return MPP_NOK;
141 }
142 if (ctx->origin_bufs) {
143 hal_bufs_deinit(ctx->origin_bufs);
144 ctx->origin_bufs = NULL;
145 }
146 hal_bufs_init(&ctx->origin_bufs);
147 if (!ctx->origin_bufs) {
148 mpp_err_f("origin_bufs init fail\n");
149 return MPP_ERR_NOMEM;
150 }
151 hal_bufs_setup(ctx->origin_bufs, 16, 1, &origin_buf_size);
152
153 return MPP_OK;
154 }
155
prepare_spspps(H264dHalCtx_t * p_hal,RK_U64 * data,RK_U32 len)156 static MPP_RET prepare_spspps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
157 {
158 RK_S32 i = 0;
159 RK_S32 is_long_term = 0, voidx = 0;
160 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
161 RK_U32 tmp = 0;
162 BitputCtx_t bp;
163
164 mpp_set_bitput_ctx(&bp, data, len);
165
166 if (!p_hal->fast_mode && !pp->spspps_update) {
167 bp.index = 2;
168 bp.bitpos = 24;
169 bp.bvalue = bp.pbuf[bp.index] & 0xFFFFFF;
170 } else {
171 RK_U32 pic_width, pic_height;
172
173 //!< sps syntax
174 pic_width = 16 * (pp->wFrameWidthInMbsMinus1 + 1);
175 pic_height = 16 * (pp->wFrameHeightInMbsMinus1 + 1);
176 pic_height *= (2 - pp->frame_mbs_only_flag);
177 pic_height /= (1 + pp->field_pic_flag);
178 mpp_put_bits(&bp, pp->seq_parameter_set_id, 4);
179 mpp_put_bits(&bp, pp->profile_idc, 8);
180 mpp_put_bits(&bp, pp->constraint_set3_flag, 1);
181 mpp_put_bits(&bp, pp->chroma_format_idc, 2);
182 mpp_put_bits(&bp, pp->bit_depth_luma_minus8, 3);
183 mpp_put_bits(&bp, pp->bit_depth_chroma_minus8, 3);
184 mpp_put_bits(&bp, 0, 1); // set 0
185 mpp_put_bits(&bp, pp->log2_max_frame_num_minus4, 4);
186 mpp_put_bits(&bp, pp->num_ref_frames, 5);
187 mpp_put_bits(&bp, pp->pic_order_cnt_type, 2);
188 mpp_put_bits(&bp, pp->log2_max_pic_order_cnt_lsb_minus4, 4);
189 mpp_put_bits(&bp, pp->delta_pic_order_always_zero_flag, 1);
190 mpp_put_bits(&bp, pic_width, 16);
191 mpp_put_bits(&bp, pic_height, 16);
192 mpp_put_bits(&bp, pp->frame_mbs_only_flag, 1);
193 mpp_put_bits(&bp, pp->MbaffFrameFlag, 1);
194 mpp_put_bits(&bp, pp->direct_8x8_inference_flag, 1);
195 /* multi-view */
196 mpp_put_bits(&bp, pp->mvc_extension_enable, 1);
197 if (pp->mvc_extension_enable) {
198 mpp_put_bits(&bp, (pp->num_views_minus1 + 1), 2);
199 mpp_put_bits(&bp, pp->view_id[0], 10);
200 mpp_put_bits(&bp, pp->view_id[1], 10);
201 } else {
202 mpp_put_bits(&bp, 0, 22);
203 }
204 // hw_fifo_align_bits(&bp, 128);
205 //!< pps syntax
206 mpp_put_bits(&bp, pp->pps_pic_parameter_set_id, 8);
207 mpp_put_bits(&bp, pp->pps_seq_parameter_set_id, 5);
208 mpp_put_bits(&bp, pp->entropy_coding_mode_flag, 1);
209 mpp_put_bits(&bp, pp->pic_order_present_flag, 1);
210
211 mpp_put_bits(&bp, pp->num_ref_idx_l0_active_minus1, 5);
212 mpp_put_bits(&bp, pp->num_ref_idx_l1_active_minus1, 5);
213 mpp_put_bits(&bp, pp->weighted_pred_flag, 1);
214 mpp_put_bits(&bp, pp->weighted_bipred_idc, 2);
215 mpp_put_bits(&bp, pp->pic_init_qp_minus26, 7);
216 mpp_put_bits(&bp, pp->pic_init_qs_minus26, 6);
217 mpp_put_bits(&bp, pp->chroma_qp_index_offset, 5);
218 mpp_put_bits(&bp, pp->deblocking_filter_control_present_flag, 1);
219 mpp_put_bits(&bp, pp->constrained_intra_pred_flag, 1);
220 mpp_put_bits(&bp, pp->redundant_pic_cnt_present_flag, 1);
221 mpp_put_bits(&bp, pp->transform_8x8_mode_flag, 1);
222 mpp_put_bits(&bp, pp->second_chroma_qp_index_offset, 5);
223 mpp_put_bits(&bp, pp->scaleing_list_enable_flag, 1);
224 }
225
226 //!< set dpb
227 for (i = 0; i < 16; i++) {
228 is_long_term = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefFrameList[i].AssociatedFlag : 0;
229 tmp |= (RK_U32)(is_long_term & 0x1) << i;
230 }
231 for (i = 0; i < 16; i++) {
232 voidx = (pp->RefFrameList[i].bPicEntry != 0xff) ? pp->RefPicLayerIdList[i] : 0;
233 tmp |= (RK_U32)(voidx & 0x1) << (i + 16);
234 }
235 mpp_put_bits(&bp, tmp, 32);
236 /* set current frame */
237 mpp_put_bits(&bp, pp->field_pic_flag, 1);
238 mpp_put_bits(&bp, (pp->field_pic_flag && pp->CurrPic.AssociatedFlag), 1);
239
240 mpp_put_bits(&bp, pp->CurrFieldOrderCnt[0], 32);
241 mpp_put_bits(&bp, pp->CurrFieldOrderCnt[1], 32);
242
243 /* refer poc */
244 for (i = 0; i < 16; i++) {
245 mpp_put_bits(&bp, pp->FieldOrderCntList[i][0], 32);
246 mpp_put_bits(&bp, pp->FieldOrderCntList[i][1], 32);
247 }
248
249 tmp = 0;
250 for (i = 0; i < 16; i++) {
251 RK_U32 field_flag = (pp->RefPicFiledFlags >> i) & 0x01;
252
253 tmp |= field_flag << i;
254 }
255 for (i = 0; i < 16; i++) {
256 RK_U32 top_used = (pp->UsedForReferenceFlags >> (2 * i + 0)) & 0x01;
257
258 tmp |= top_used << (i + 16);
259 }
260 mpp_put_bits(&bp, tmp, 32);
261
262 tmp = 0;
263 for (i = 0; i < 16; i++) {
264 RK_U32 bot_used = (pp->UsedForReferenceFlags >> (2 * i + 1)) & 0x01;
265
266 tmp |= bot_used << i;
267 }
268 for (i = 0; i < 16; i++) {
269 RK_U32 ref_colmv_used = (pp->RefPicColmvUsedFlags >> i) & 0x01;
270
271 tmp |= ref_colmv_used << (i + 16);
272 }
273 mpp_put_bits(&bp, tmp, 32);
274 mpp_put_align(&bp, 64, 0);//128
275
276 #ifdef DUMP_VDPU383_DATAS
277 {
278 char *cur_fname = "global_cfg.dat";
279 memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
280 sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
281 dump_data_to_file(dump_cur_fname_path, (void *)bp.pbuf, 64 * bp.index + bp.bitpos, 64, 0);
282 }
283 #endif
284
285 return MPP_OK;
286 }
287
prepare_framerps(H264dHalCtx_t * p_hal,RK_U64 * data,RK_U32 len)288 static MPP_RET prepare_framerps(H264dHalCtx_t *p_hal, RK_U64 *data, RK_U32 len)
289 {
290 RK_S32 i = 0, j = 0;
291 RK_S32 dpb_idx = 0, voidx = 0;
292 RK_S32 dpb_valid = 0, bottom_flag = 0;
293 RK_U32 max_frame_num = 0;
294 RK_U16 frame_num_wrap = 0;
295 RK_U32 tmp = 0;
296
297 BitputCtx_t bp;
298 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
299
300 mpp_set_bitput_ctx(&bp, data, len);
301
302 max_frame_num = 1 << (pp->log2_max_frame_num_minus4 + 4);
303 for (i = 0; i < 16; i++) {
304 if ((pp->NonExistingFrameFlags >> i) & 0x01) {
305 frame_num_wrap = 0;
306 } else {
307 if (pp->RefFrameList[i].AssociatedFlag) {
308 frame_num_wrap = pp->FrameNumList[i];
309 } else {
310 frame_num_wrap = (pp->FrameNumList[i] > pp->frame_num) ?
311 (pp->FrameNumList[i] - max_frame_num) : pp->FrameNumList[i];
312 }
313 }
314 mpp_put_bits(&bp, frame_num_wrap, 16);
315 }
316
317 tmp = 0;
318 for (i = 0; i < 16; i++) {
319 tmp |= (RK_U32)pp->RefPicLayerIdList[i] << (i + 16);
320 }
321 mpp_put_bits(&bp, tmp, 32);
322
323 for (i = 0; i < 32; i++) {
324 tmp = 0;
325 dpb_valid = (p_hal->slice_long[0].RefPicList[0][i].bPicEntry == 0xff) ? 0 : 1;
326 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].Index7Bits : 0;
327 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[0][i].AssociatedFlag : 0;
328 voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
329
330 tmp |= (RK_U32)(dpb_idx | (dpb_valid << 4)) & 0x1f;
331 tmp |= (RK_U32)(bottom_flag & 0x1) << 5;
332 if (dpb_valid)
333 tmp |= (RK_U32)(voidx & 0x1) << 6;
334 mpp_put_bits(&bp, tmp, 7);
335 }
336
337 for (j = 1; j < 3; j++) {
338 for (i = 0; i < 32; i++) {
339 tmp = 0;
340 dpb_valid = (p_hal->slice_long[0].RefPicList[j][i].bPicEntry == 0xff) ? 0 : 1;
341 dpb_idx = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].Index7Bits : 0;
342 bottom_flag = dpb_valid ? p_hal->slice_long[0].RefPicList[j][i].AssociatedFlag : 0;
343 voidx = dpb_valid ? pp->RefPicLayerIdList[dpb_idx] : 0;
344 tmp |= (RK_U32)(dpb_idx | (dpb_valid << 4)) & 0x1f;
345 tmp |= (RK_U32)(bottom_flag & 0x1) << 5;
346 if (dpb_valid)
347 tmp |= (RK_U32)(voidx & 0x1) << 6;
348 mpp_put_bits(&bp, tmp, 7);
349 }
350 }
351
352 mpp_put_align(&bp, 128, 0);
353
354 #ifdef DUMP_VDPU383_DATAS
355 {
356 char *cur_fname = "rps.dat";
357 memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
358 sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
359 dump_data_to_file(dump_cur_fname_path, (void *)bp.pbuf, 64 * bp.index + bp.bitpos, 64, 0);
360 }
361 #endif
362
363 return MPP_OK;
364 }
365
prepare_scanlist(H264dHalCtx_t * p_hal,RK_U8 * data,RK_U32 len)366 static MPP_RET prepare_scanlist(H264dHalCtx_t *p_hal, RK_U8 *data, RK_U32 len)
367 {
368 RK_U32 i = 0, j = 0, n = 0;
369
370 if (!p_hal->pp->scaleing_list_enable_flag)
371 return MPP_OK;
372
373 for (i = 0; i < 6; i++) { //4x4, 6 lists
374 /* dump by block4x4, vectial direction */
375 for (j = 0; j < 4; j++) {
376 data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 0];
377 data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 1];
378 data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 2];
379 data[n++] = p_hal->qm->bScalingLists4x4[i][j * 4 + 3];
380 }
381 }
382
383 for (i = 0; i < 2; i++) { //8x8, 2 lists
384 RK_U32 blk4_x = 0, blk4_y = 0;
385
386 /* dump by block4x4, vectial direction */
387 for (blk4_y = 0; blk4_y < 8; blk4_y += 4) {
388 for (blk4_x = 0; blk4_x < 8; blk4_x += 4) {
389 RK_U32 pos = blk4_y * 8 + blk4_x;
390
391 for (j = 0; j < 4; j++) {
392 data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 0];
393 data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 1];
394 data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 2];
395 data[n++] = p_hal->qm->bScalingLists8x8[i][pos + j * 8 + 3];
396 }
397 }
398 }
399 }
400
401 mpp_assert(n <= len);
402
403 #ifdef DUMP_VDPU383_DATAS
404 {
405 char *cur_fname = "scanlist.dat";
406 memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
407 sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
408 dump_data_to_file(dump_cur_fname_path, (void *)data, 8 * n, 128, 0);
409 }
410 #endif
411
412 return MPP_OK;
413 }
414
set_registers(H264dHalCtx_t * p_hal,Vdpu383H264dRegSet * regs,HalTaskInfo * task)415 static MPP_RET set_registers(H264dHalCtx_t *p_hal, Vdpu383H264dRegSet *regs, HalTaskInfo *task)
416 {
417 DXVA_PicParams_H264_MVC *pp = p_hal->pp;
418 HalBuf *mv_buf = NULL;
419 HalBuf *origin_buf = NULL;
420 Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
421
422 // memset(regs, 0, sizeof(Vdpu383H264dRegSet));
423 regs->h264d_paras.reg66_stream_len = p_hal->strm_len;
424
425 //!< caculate the yuv_frame_size
426 {
427 MppFrame mframe = NULL;
428 RK_U32 hor_virstride = 0;
429 RK_U32 ver_virstride = 0;
430 RK_U32 y_virstride = 0;
431 RK_U32 uv_virstride = 0;
432
433 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
434 hor_virstride = mpp_frame_get_hor_stride(mframe);
435 ver_virstride = mpp_frame_get_ver_stride(mframe);
436 y_virstride = hor_virstride * ver_virstride;
437 uv_virstride = hor_virstride * ver_virstride / 2;
438
439 if (MPP_FRAME_FMT_IS_FBC(mpp_frame_get_fmt(mframe))) {
440 RK_U32 fbc_hdr_stride = mpp_frame_get_fbc_hdr_stride(mframe);
441 RK_U32 fbd_offset;
442
443 fbd_offset = fbc_hdr_stride * MPP_ALIGN(ver_virstride, 64) / 16;
444
445 regs->ctrl_regs.reg9.fbc_e = 1;
446 regs->h264d_paras.reg68_hor_virstride = fbc_hdr_stride / 64;
447 regs->h264d_addrs.reg193_fbc_payload_offset = fbd_offset;
448 } else if (MPP_FRAME_FMT_IS_TILE(mpp_frame_get_fmt(mframe))) {
449 regs->ctrl_regs.reg9.tile_e = 1;
450 regs->h264d_paras.reg68_hor_virstride = hor_virstride * 6 / 16;
451 regs->h264d_paras.reg70_y_virstride = (y_virstride + uv_virstride) / 16;
452 } else {
453 regs->ctrl_regs.reg9.fbc_e = 0;
454 regs->h264d_paras.reg68_hor_virstride = hor_virstride / 16;
455 regs->h264d_paras.reg69_raster_uv_hor_virstride = hor_virstride / 16;
456 regs->h264d_paras.reg70_y_virstride = y_virstride / 16;
457 }
458 }
459 //!< set current
460 {
461 MppBuffer mbuffer = NULL;
462 RK_S32 fd = -1;
463
464 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);
465 fd = mpp_buffer_get_fd(mbuffer);
466 regs->h264d_addrs.reg168_decout_base = fd;
467 regs->h264d_addrs.reg192_payload_st_cur_base = fd;
468
469 //colmv_cur_base
470 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, pp->CurrPic.Index7Bits);
471 regs->h264d_addrs.reg216_colmv_cur_base = mpp_buffer_get_fd(mv_buf->buf[0]);
472 regs->h264d_addrs.reg169_error_ref_base = fd;
473 }
474 //!< set reference
475 {
476 RK_S32 i = 0;
477 RK_S32 fd = -1;
478 RK_S32 ref_index = -1;
479 RK_S32 near_index = -1;
480 MppBuffer mbuffer = NULL;
481 RK_U32 min_frame_num = 0;
482 MppFrame mframe = NULL;
483
484 for (i = 0; i < 15; i++) {
485 if (pp->RefFrameList[i].bPicEntry != 0xff) {
486 ref_index = pp->RefFrameList[i].Index7Bits;
487 near_index = pp->RefFrameList[i].Index7Bits;
488 } else {
489 ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
490 }
491 /* mark 3 to differ from current frame */
492 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
493 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_FRAME_PTR, &mframe);
494 if (ctx->origin_bufs && mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY) {
495 origin_buf = hal_bufs_get_buf(ctx->origin_bufs, ref_index);
496 mbuffer = origin_buf->buf[0];
497 }
498
499 if (pp->FrameNumList[i] < pp->frame_num &&
500 pp->FrameNumList[i] > min_frame_num &&
501 (!mpp_frame_get_errinfo(mframe))) {
502 min_frame_num = pp->FrameNumList[i];
503 regs->h264d_addrs.reg169_error_ref_base = mpp_buffer_get_fd(mbuffer);
504 }
505
506 fd = mpp_buffer_get_fd(mbuffer);
507 regs->h264d_addrs.reg170_185_ref_base[i] = fd;
508 regs->h264d_addrs.reg195_210_payload_st_ref_base[i] = fd;
509 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index);
510 regs->h264d_addrs.reg217_232_colmv_ref_base[i] = mpp_buffer_get_fd(mv_buf->buf[0]);
511 }
512
513 if (pp->RefFrameList[15].bPicEntry != 0xff) {
514 ref_index = pp->RefFrameList[15].Index7Bits;
515 } else {
516 ref_index = (near_index < 0) ? pp->CurrPic.Index7Bits : near_index;
517 }
518
519 mpp_buf_slot_get_prop(p_hal->frame_slots, ref_index, SLOT_BUFFER, &mbuffer);
520 fd = mpp_buffer_get_fd(mbuffer);
521 if (mpp_frame_get_thumbnail_en(mframe) == 2) {
522 origin_buf = hal_bufs_get_buf(ctx->origin_bufs, ref_index);
523 fd = mpp_buffer_get_fd(origin_buf->buf[0]);
524 }
525 regs->h264d_addrs.reg170_185_ref_base[15] = fd;
526 regs->h264d_addrs.reg195_210_payload_st_ref_base[15] = fd;
527 mv_buf = hal_bufs_get_buf(p_hal->cmv_bufs, ref_index);
528 regs->h264d_addrs.reg217_232_colmv_ref_base[15] = mpp_buffer_get_fd(mv_buf->buf[0]);
529 }
530 {
531 MppBuffer mbuffer = NULL;
532 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
533
534 mpp_buf_slot_get_prop(p_hal->packet_slots, task->dec.input, SLOT_BUFFER, &mbuffer);
535 regs->common_addr.reg128_strm_base = mpp_buffer_get_fd(mbuffer);
536 // regs->h264d_paras.reg65_strm_start_bit = 2 * 8;
537 #ifdef DUMP_VDPU383_DATAS
538 {
539 char *cur_fname = "stream_in.dat";
540 memset(dump_cur_fname_path, 0, sizeof(dump_cur_fname_path));
541 sprintf(dump_cur_fname_path, "%s/%s", dump_cur_dir, cur_fname);
542 dump_data_to_file(dump_cur_fname_path, (void *)mpp_buffer_get_ptr(mbuffer),
543 8 * p_hal->strm_len, 128, 0);
544 }
545 #endif
546
547 regs->common_addr.reg130_cabactbl_base = reg_ctx->bufs_fd;
548 mpp_dev_set_reg_offset(p_hal->dev, 130, reg_ctx->offset_cabac);
549 }
550
551 {
552 //scale down config
553 MppFrame mframe = NULL;
554 MppBuffer mbuffer = NULL;
555 RK_S32 fd = -1;
556 MppFrameThumbnailMode thumbnail_mode;
557
558 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits, SLOT_BUFFER, &mbuffer);
559 mpp_buf_slot_get_prop(p_hal->frame_slots, pp->CurrPic.Index7Bits,
560 SLOT_FRAME_PTR, &mframe);
561 fd = mpp_buffer_get_fd(mbuffer);
562 thumbnail_mode = mpp_frame_get_thumbnail_en(mframe);
563 switch (thumbnail_mode) {
564 case MPP_FRAME_THUMBNAIL_ONLY:
565 regs->common_addr.reg133_scale_down_base = fd;
566 origin_buf = hal_bufs_get_buf(ctx->origin_bufs, pp->CurrPic.Index7Bits);
567 fd = mpp_buffer_get_fd(origin_buf->buf[0]);
568 regs->h264d_addrs.reg168_decout_base = fd;
569 regs->h264d_addrs.reg192_payload_st_cur_base = fd;
570 regs->h264d_addrs.reg169_error_ref_base = fd;
571 vdpu383_setup_down_scale(mframe, p_hal->dev, ®s->ctrl_regs, (void*)®s->h264d_paras);
572 break;
573 case MPP_FRAME_THUMBNAIL_MIXED:
574 regs->common_addr.reg133_scale_down_base = fd;
575 vdpu383_setup_down_scale(mframe, p_hal->dev, ®s->ctrl_regs, (void*)®s->h264d_paras);
576 break;
577 case MPP_FRAME_THUMBNAIL_NONE:
578 default:
579 regs->ctrl_regs.reg9.scale_down_en = 0;
580 break;
581 }
582 }
583
584 return MPP_OK;
585 }
586
init_ctrl_regs(Vdpu383H264dRegSet * regs)587 static MPP_RET init_ctrl_regs(Vdpu383H264dRegSet *regs)
588 {
589 Vdpu383CtrlReg *ctrl_regs = ®s->ctrl_regs;
590
591 ctrl_regs->reg8_dec_mode = 1; //!< h264
592 ctrl_regs->reg9.buf_empty_en = 0;
593
594 ctrl_regs->reg10.strmd_auto_gating_e = 1;
595 ctrl_regs->reg10.inter_auto_gating_e = 1;
596 ctrl_regs->reg10.intra_auto_gating_e = 1;
597 ctrl_regs->reg10.transd_auto_gating_e = 1;
598 ctrl_regs->reg10.recon_auto_gating_e = 1;
599 ctrl_regs->reg10.filterd_auto_gating_e = 1;
600 ctrl_regs->reg10.bus_auto_gating_e = 1;
601 ctrl_regs->reg10.ctrl_auto_gating_e = 1;
602 ctrl_regs->reg10.rcb_auto_gating_e = 1;
603 ctrl_regs->reg10.err_prc_auto_gating_e = 1;
604
605 ctrl_regs->reg13_core_timeout_threshold = 0xffffff;
606
607 ctrl_regs->reg16.error_proc_disable = 1;
608 ctrl_regs->reg16.error_spread_disable = 0;
609 ctrl_regs->reg16.roi_error_ctu_cal_en = 0;
610
611 ctrl_regs->reg20_cabac_error_en_lowbits = 0xfffedfff;
612 ctrl_regs->reg21_cabac_error_en_highbits = 0x0ffbf9ff;
613
614 /* performance */
615 ctrl_regs->reg28.axi_perf_work_e = 1;
616 ctrl_regs->reg28.axi_cnt_type = 1;
617 ctrl_regs->reg28.rd_latency_id = 11;
618
619 ctrl_regs->reg29.addr_align_type = 2;
620 ctrl_regs->reg29.ar_cnt_id_type = 0;
621 ctrl_regs->reg29.aw_cnt_id_type = 0;
622 ctrl_regs->reg29.ar_count_id = 0xa;
623 ctrl_regs->reg29.aw_count_id = 0;
624 ctrl_regs->reg29.rd_band_width_mode = 0;
625
626 return MPP_OK;
627 }
628
vdpu383_h264d_init(void * hal,MppHalCfg * cfg)629 MPP_RET vdpu383_h264d_init(void *hal, MppHalCfg *cfg)
630 {
631 MPP_RET ret = MPP_ERR_UNKNOW;
632 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
633
634 INP_CHECK(ret, NULL == p_hal);
635 (void) cfg;
636
637 MEM_CHECK(ret, p_hal->reg_ctx = mpp_calloc_size(void, sizeof(Vdpu383H264dRegCtx)));
638 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
639 RK_U32 max_cnt = p_hal->fast_mode ? VDPU383_FAST_REG_SET_CNT : 1;
640 RK_U32 i = 0;
641
642 //!< malloc buffers
643 FUN_CHECK(ret = mpp_buffer_get(p_hal->buf_group, ®_ctx->bufs,
644 VDPU383_INFO_BUFFER_SIZE(max_cnt)));
645 reg_ctx->bufs_fd = mpp_buffer_get_fd(reg_ctx->bufs);
646 reg_ctx->bufs_ptr = mpp_buffer_get_ptr(reg_ctx->bufs);
647 reg_ctx->offset_cabac = VDPU383_CABAC_TAB_OFFSET;
648 reg_ctx->offset_errinfo = VDPU383_ERROR_INFO_OFFSET;
649 for (i = 0; i < max_cnt; i++) {
650 reg_ctx->reg_buf[i].regs = mpp_calloc(Vdpu383H264dRegSet, 1);
651 init_ctrl_regs(reg_ctx->reg_buf[i].regs);
652 reg_ctx->offset_spspps[i] = VDPU383_SPSPPS_OFFSET(i);
653 reg_ctx->offset_rps[i] = VDPU383_RPS_OFFSET(i);
654 reg_ctx->offset_sclst[i] = VDPU383_SCALING_LIST_OFFSET(i);
655 }
656
657 mpp_buffer_attach_dev(reg_ctx->bufs, p_hal->dev);
658
659 if (!p_hal->fast_mode) {
660 reg_ctx->regs = reg_ctx->reg_buf[0].regs;
661 reg_ctx->spspps_offset = reg_ctx->offset_spspps[0];
662 reg_ctx->rps_offset = reg_ctx->offset_rps[0];
663 reg_ctx->sclst_offset = reg_ctx->offset_sclst[0];
664 }
665
666 //!< copy cabac table bytes
667 memcpy((char *)reg_ctx->bufs_ptr + reg_ctx->offset_cabac,
668 (void *)h264_cabac_table, sizeof(h264_cabac_table));
669
670 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
671 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_VER_ALIGN, rkv_ver_align);
672 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align);
673
674 if (cfg->hal_fbc_adj_cfg) {
675 cfg->hal_fbc_adj_cfg->func = vdpu383_afbc_align_calc;
676 cfg->hal_fbc_adj_cfg->expand = 16;
677 }
678
679 __RETURN:
680 return MPP_OK;
681 __FAILED:
682 vdpu383_h264d_deinit(hal);
683
684 return ret;
685 }
686
vdpu383_h264d_deinit(void * hal)687 MPP_RET vdpu383_h264d_deinit(void *hal)
688 {
689 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
690 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
691
692 RK_U32 i = 0;
693 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->reg_buf) : 1;
694
695 if (reg_ctx->bufs) {
696 mpp_buffer_put(reg_ctx->bufs);
697 reg_ctx->bufs = NULL;
698 }
699
700 for (i = 0; i < loop; i++)
701 MPP_FREE(reg_ctx->reg_buf[i].regs);
702
703 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(reg_ctx->rcb_buf) : 1;
704 for (i = 0; i < loop; i++) {
705 if (reg_ctx->rcb_buf[i]) {
706 mpp_buffer_put(reg_ctx->rcb_buf[i]);
707 reg_ctx->rcb_buf[i] = NULL;
708 }
709 }
710
711 if (p_hal->cmv_bufs) {
712 hal_bufs_deinit(p_hal->cmv_bufs);
713 p_hal->cmv_bufs = NULL;
714 }
715
716 if (reg_ctx->origin_bufs) {
717 hal_bufs_deinit(reg_ctx->origin_bufs);
718 reg_ctx->origin_bufs = NULL;
719 }
720
721 MPP_FREE(p_hal->reg_ctx);
722
723 return MPP_OK;
724 }
725
h264d_refine_rcb_size(H264dHalCtx_t * p_hal,Vdpu383RcbInfo * rcb_info,RK_S32 width,RK_S32 height)726 static void h264d_refine_rcb_size(H264dHalCtx_t *p_hal, Vdpu383RcbInfo *rcb_info,
727 RK_S32 width, RK_S32 height)
728 {
729 RK_U32 rcb_bits = 0;
730 RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;
731 RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;
732 RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;
733 RK_U32 row_uv_para = 1; // for yuv420/yuv422
734 RK_U32 filterd_row_append = 8192;
735
736 // vdpu383 h264d support yuv400/yuv420/yuv422
737 if (chroma_format_idc == 0)
738 row_uv_para = 0;
739
740 width = MPP_ALIGN(width, H264_CTU_SIZE);
741 height = MPP_ALIGN(height, H264_CTU_SIZE);
742 /* RCB_STRMD_ROW && RCB_STRMD_TILE_ROW*/
743 if (width > 4096)
744 rcb_bits = ((width + 15) / 16) * 154 * (mbaff ? 2 : 1);
745 else
746 rcb_bits = 0;
747 rcb_info[RCB_STRMD_ROW].size = MPP_RCB_BYTES(rcb_bits);
748 rcb_info[RCB_STRMD_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
749 /* RCB_INTER_ROW && RCB_INTER_TILE_ROW*/
750 rcb_bits = ((width + 3) / 4) * 92 * (mbaff ? 2 : 1);
751 rcb_info[RCB_INTER_ROW].size = MPP_RCB_BYTES(rcb_bits);
752 rcb_info[RCB_INTER_TILE_ROW].size = MPP_RCB_BYTES(rcb_bits);
753 /* RCB_INTRA_ROW && RCB_INTRA_TILE_ROW*/
754 rcb_bits = MPP_ALIGN(width, 512) * (bit_depth + 2) * (mbaff ? 2 : 1);
755 if (chroma_format_idc == 1 || chroma_format_idc == 2)
756 rcb_bits = rcb_bits * 5 / 2; //TODO:
757
758 rcb_info[RCB_INTRA_ROW].size = MPP_RCB_BYTES(rcb_bits);
759 rcb_info[RCB_INTRA_TILE_ROW].size = 0;
760 /* RCB_FILTERD_ROW && RCB_FILTERD_PROTECT_ROW*/
761 // save space mode : half for RCB_FILTERD_ROW, half for RCB_FILTERD_PROTECT_ROW
762 rcb_bits = width * 17 * ((6 + 3 * row_uv_para) * (mbaff ? 2 : 1) + 2 * row_uv_para + 1.5);
763 if (width > 4096)
764 filterd_row_append = 27648;
765 rcb_info[RCB_FILTERD_ROW].size = filterd_row_append + MPP_RCB_BYTES(rcb_bits / 2);
766 rcb_info[RCB_FILTERD_PROTECT_ROW].size = filterd_row_append + MPP_RCB_BYTES(rcb_bits / 2);
767
768 rcb_info[RCB_FILTERD_TILE_ROW].size = 0;
769 /* RCB_FILTERD_TILE_COL */
770 rcb_info[RCB_FILTERD_TILE_COL].size = 0;
771
772 }
773
hal_h264d_rcb_info_update(void * hal)774 static void hal_h264d_rcb_info_update(void *hal)
775 {
776 H264dHalCtx_t *p_hal = (H264dHalCtx_t*)hal;
777 RK_U32 mbaff = p_hal->pp->MbaffFrameFlag;
778 RK_U32 bit_depth = p_hal->pp->bit_depth_luma_minus8 + 8;
779 RK_U32 chroma_format_idc = p_hal->pp->chroma_format_idc;
780 Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
781 RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
782 RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
783
784 if ( ctx->bit_depth != bit_depth ||
785 ctx->chroma_format_idc != chroma_format_idc ||
786 ctx->mbaff != mbaff ||
787 ctx->width != width ||
788 ctx->height != height) {
789 RK_U32 i;
790 RK_U32 loop = p_hal->fast_mode ? MPP_ARRAY_ELEMS(ctx->reg_buf) : 1;
791
792 ctx->rcb_buf_size = vdpu383_get_rcb_buf_size(ctx->rcb_info, width, height);
793 h264d_refine_rcb_size(hal, ctx->rcb_info, width, height);
794 for (i = 0; i < loop; i++) {
795 MppBuffer rcb_buf = ctx->rcb_buf[i];
796
797 if (rcb_buf) {
798 mpp_buffer_put(rcb_buf);
799 ctx->rcb_buf[i] = NULL;
800 }
801 mpp_buffer_get(p_hal->buf_group, &rcb_buf, ctx->rcb_buf_size);
802 ctx->rcb_buf[i] = rcb_buf;
803 }
804 ctx->bit_depth = bit_depth;
805 ctx->width = width;
806 ctx->height = height;
807 ctx->mbaff = mbaff;
808 ctx->chroma_format_idc = chroma_format_idc;
809 }
810 }
811
vdpu383_h264d_gen_regs(void * hal,HalTaskInfo * task)812 MPP_RET vdpu383_h264d_gen_regs(void *hal, HalTaskInfo *task)
813 {
814 MPP_RET ret = MPP_ERR_UNKNOW;
815 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
816 RK_S32 width = MPP_ALIGN((p_hal->pp->wFrameWidthInMbsMinus1 + 1) << 4, 64);
817 RK_S32 height = MPP_ALIGN((p_hal->pp->wFrameHeightInMbsMinus1 + 1) << 4, 64);
818 Vdpu383H264dRegCtx *ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
819 Vdpu383H264dRegSet *regs = ctx->regs;
820 MppFrame mframe;
821 RK_S32 mv_size = MPP_ALIGN(width, 64) * MPP_ALIGN(height, 16); // 16 byte unit
822
823 INP_CHECK(ret, NULL == p_hal);
824
825 if (task->dec.flags.parse_err ||
826 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
827 goto __RETURN;
828 }
829
830 /* if is field mode is enabled enlarge colmv buffer and disable colmv compression */
831 if (!p_hal->pp->frame_mbs_only_flag)
832 mv_size *= 2;
833
834 if (p_hal->cmv_bufs == NULL || p_hal->mv_size < mv_size) {
835 size_t size = mv_size;
836
837 if (p_hal->cmv_bufs) {
838 hal_bufs_deinit(p_hal->cmv_bufs);
839 p_hal->cmv_bufs = NULL;
840 }
841
842 hal_bufs_init(&p_hal->cmv_bufs);
843 if (p_hal->cmv_bufs == NULL) {
844 mpp_err_f("colmv bufs init fail");
845 goto __RETURN;
846 }
847 p_hal->mv_size = mv_size;
848 p_hal->mv_count = mpp_buf_slot_get_count(p_hal->frame_slots);
849 hal_bufs_setup(p_hal->cmv_bufs, p_hal->mv_count, 1, &size);
850 }
851
852 mpp_buf_slot_get_prop(p_hal->frame_slots, p_hal->pp->CurrPic.Index7Bits, SLOT_FRAME_PTR, &mframe);
853 if (mpp_frame_get_thumbnail_en(mframe) == MPP_FRAME_THUMBNAIL_ONLY &&
854 ctx->origin_bufs == NULL) {
855 vdpu383_setup_scale_origin_bufs(p_hal, mframe);
856 }
857
858 if (p_hal->fast_mode) {
859 RK_U32 i = 0;
860 for (i = 0; i < MPP_ARRAY_ELEMS(ctx->reg_buf); i++) {
861 if (!ctx->reg_buf[i].valid) {
862 task->dec.reg_index = i;
863 regs = ctx->reg_buf[i].regs;
864
865 ctx->spspps_offset = ctx->offset_spspps[i];
866 ctx->rps_offset = ctx->offset_rps[i];
867 ctx->sclst_offset = ctx->offset_sclst[i];
868 ctx->reg_buf[i].valid = 1;
869 break;
870 }
871 }
872 }
873
874 #ifdef DUMP_VDPU383_DATAS
875 {
876 memset(dump_cur_dir, 0, sizeof(dump_cur_dir));
877 sprintf(dump_cur_dir, "avc/Frame%04d", dump_cur_frame);
878 if (access(dump_cur_dir, 0)) {
879 if (mkdir(dump_cur_dir))
880 mpp_err_f("error: mkdir %s\n", dump_cur_dir);
881 }
882 dump_cur_frame++;
883 }
884 #endif
885
886 prepare_spspps(p_hal, (RK_U64 *)&ctx->spspps, sizeof(ctx->spspps) / 8);
887 prepare_framerps(p_hal, (RK_U64 *)&ctx->rps, sizeof(ctx->rps) / 8);
888 prepare_scanlist(p_hal, ctx->sclst, sizeof(ctx->sclst));
889 set_registers(p_hal, regs, task);
890
891 //!< copy spspps datas
892 memcpy((char *)ctx->bufs_ptr + ctx->spspps_offset, (char *)ctx->spspps, sizeof(ctx->spspps));
893
894 regs->common_addr.reg131_gbl_base = ctx->bufs_fd;
895 regs->h264d_paras.reg67_global_len = VDPU383_SPS_PPS_LEN / 16; // 128 bit as unit
896 mpp_dev_set_reg_offset(p_hal->dev, 131, ctx->spspps_offset);
897
898 memcpy((char *)ctx->bufs_ptr + ctx->rps_offset, (void *)ctx->rps, sizeof(ctx->rps));
899 regs->common_addr.reg129_rps_base = ctx->bufs_fd;
900 mpp_dev_set_reg_offset(p_hal->dev, 129, ctx->rps_offset);
901
902 if (p_hal->pp->scaleing_list_enable_flag) {
903 memcpy((char *)ctx->bufs_ptr + ctx->sclst_offset, (void *)ctx->sclst, sizeof(ctx->sclst));
904 regs->common_addr.reg132_scanlist_addr = ctx->bufs_fd;
905 mpp_dev_set_reg_offset(p_hal->dev, 132, ctx->sclst_offset);
906 } else {
907 regs->common_addr.reg132_scanlist_addr = 0;
908 }
909
910 hal_h264d_rcb_info_update(p_hal);
911 vdpu383_setup_rcb(®s->common_addr, p_hal->dev, p_hal->fast_mode ?
912 ctx->rcb_buf[task->dec.reg_index] : ctx->rcb_buf[0],
913 ctx->rcb_info);
914 vdpu383_setup_statistic(®s->ctrl_regs);
915 mpp_buffer_sync_end(ctx->bufs);
916
917 __RETURN:
918 return ret = MPP_OK;
919 }
920
vdpu383_h264d_start(void * hal,HalTaskInfo * task)921 MPP_RET vdpu383_h264d_start(void *hal, HalTaskInfo *task)
922 {
923 MPP_RET ret = MPP_ERR_UNKNOW;
924 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
925 INP_CHECK(ret, NULL == p_hal);
926
927 if (task->dec.flags.parse_err ||
928 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
929 goto __RETURN;
930 }
931
932 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
933 Vdpu383H264dRegSet *regs = p_hal->fast_mode ?
934 reg_ctx->reg_buf[task->dec.reg_index].regs :
935 reg_ctx->regs;
936 MppDev dev = p_hal->dev;
937
938 do {
939 MppDevRegWrCfg wr_cfg;
940 MppDevRegRdCfg rd_cfg;
941
942 wr_cfg.reg = ®s->ctrl_regs;
943 wr_cfg.size = sizeof(regs->ctrl_regs);
944 wr_cfg.offset = OFFSET_CTRL_REGS;
945 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
946 if (ret) {
947 mpp_err_f("set register write failed %d\n", ret);
948 break;
949 }
950
951 wr_cfg.reg = ®s->common_addr;
952 wr_cfg.size = sizeof(regs->common_addr);
953 wr_cfg.offset = OFFSET_COMMON_ADDR_REGS;
954 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
955 if (ret) {
956 mpp_err_f("set register write failed %d\n", ret);
957 break;
958 }
959
960 wr_cfg.reg = ®s->h264d_paras;
961 wr_cfg.size = sizeof(regs->h264d_paras);
962 wr_cfg.offset = OFFSET_CODEC_PARAS_REGS;
963 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
964 if (ret) {
965 mpp_err_f("set register write failed %d\n", ret);
966 break;
967 }
968
969 wr_cfg.reg = ®s->h264d_addrs;
970 wr_cfg.size = sizeof(regs->h264d_addrs);
971 wr_cfg.offset = OFFSET_CODEC_ADDR_REGS;
972 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_WR, &wr_cfg);
973 if (ret) {
974 mpp_err_f("set register write failed %d\n", ret);
975 break;
976 }
977
978 rd_cfg.reg = ®s->ctrl_regs.reg15;
979 rd_cfg.size = sizeof(regs->ctrl_regs.reg15);
980 rd_cfg.offset = OFFSET_INTERRUPT_REGS;
981 ret = mpp_dev_ioctl(dev, MPP_DEV_REG_RD, &rd_cfg);
982 if (ret) {
983 mpp_err_f("set register read failed %d\n", ret);
984 break;
985 }
986
987 /* rcb info for sram */
988 vdpu383_set_rcbinfo(dev, (Vdpu383RcbInfo*)reg_ctx->rcb_info);
989
990 /* send request to hardware */
991 ret = mpp_dev_ioctl(dev, MPP_DEV_CMD_SEND, NULL);
992 if (ret) {
993 mpp_err_f("send cmd failed %d\n", ret);
994 break;
995 }
996 } while (0);
997
998 __RETURN:
999 return ret = MPP_OK;
1000 }
1001
vdpu383_h264d_wait(void * hal,HalTaskInfo * task)1002 MPP_RET vdpu383_h264d_wait(void *hal, HalTaskInfo *task)
1003 {
1004 MPP_RET ret = MPP_ERR_UNKNOW;
1005 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1006
1007 INP_CHECK(ret, NULL == p_hal);
1008 Vdpu383H264dRegCtx *reg_ctx = (Vdpu383H264dRegCtx *)p_hal->reg_ctx;
1009 Vdpu383H264dRegSet *p_regs = p_hal->fast_mode ?
1010 reg_ctx->reg_buf[task->dec.reg_index].regs :
1011 reg_ctx->regs;
1012
1013 if (task->dec.flags.parse_err ||
1014 (task->dec.flags.ref_err && !p_hal->cfg->base.disable_error)) {
1015 goto __SKIP_HARD;
1016 }
1017
1018 ret = mpp_dev_ioctl(p_hal->dev, MPP_DEV_CMD_POLL, NULL);
1019 if (ret)
1020 mpp_err_f("poll cmd failed %d\n", ret);
1021
1022 __SKIP_HARD:
1023 if (p_hal->dec_cb) {
1024 DecCbHalDone param;
1025
1026 param.task = (void *)&task->dec;
1027 param.regs = (RK_U32 *)p_regs;
1028
1029 if ((!p_regs->ctrl_regs.reg15.rkvdec_frame_rdy_sta) ||
1030 p_regs->ctrl_regs.reg15.rkvdec_strm_error_sta ||
1031 p_regs->ctrl_regs.reg15.rkvdec_core_timeout_sta ||
1032 p_regs->ctrl_regs.reg15.rkvdec_ip_timeout_sta ||
1033 p_regs->ctrl_regs.reg15.rkvdec_bus_error_sta ||
1034 p_regs->ctrl_regs.reg15.rkvdec_buffer_empty_sta ||
1035 p_regs->ctrl_regs.reg15.rkvdec_colmv_ref_error_sta)
1036 param.hard_err = 1;
1037 else
1038 param.hard_err = 0;
1039
1040 mpp_callback(p_hal->dec_cb, ¶m);
1041 }
1042 memset(&p_regs->ctrl_regs.reg19, 0, sizeof(RK_U32));
1043 if (p_hal->fast_mode) {
1044 reg_ctx->reg_buf[task->dec.reg_index].valid = 0;
1045 }
1046
1047 (void)task;
1048 __RETURN:
1049 return ret = MPP_OK;
1050 }
1051
vdpu383_h264d_reset(void * hal)1052 MPP_RET vdpu383_h264d_reset(void *hal)
1053 {
1054 MPP_RET ret = MPP_ERR_UNKNOW;
1055 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1056
1057 INP_CHECK(ret, NULL == p_hal);
1058
1059
1060 __RETURN:
1061 return ret = MPP_OK;
1062 }
1063
vdpu383_h264d_flush(void * hal)1064 MPP_RET vdpu383_h264d_flush(void *hal)
1065 {
1066 MPP_RET ret = MPP_ERR_UNKNOW;
1067 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1068
1069 INP_CHECK(ret, NULL == p_hal);
1070
1071 __RETURN:
1072 return ret = MPP_OK;
1073 }
1074
vdpu383_h264d_control(void * hal,MpiCmd cmd_type,void * param)1075 MPP_RET vdpu383_h264d_control(void *hal, MpiCmd cmd_type, void *param)
1076 {
1077 MPP_RET ret = MPP_ERR_UNKNOW;
1078 H264dHalCtx_t *p_hal = (H264dHalCtx_t *)hal;
1079
1080 INP_CHECK(ret, NULL == p_hal);
1081
1082 switch ((MpiCmd)cmd_type) {
1083 case MPP_DEC_SET_FRAME_INFO: {
1084 MppFrameFormat fmt = mpp_frame_get_fmt((MppFrame)param);
1085 RK_U32 imgwidth = mpp_frame_get_width((MppFrame)param);
1086 RK_U32 imgheight = mpp_frame_get_height((MppFrame)param);
1087
1088 mpp_log("control info: fmt %d, w %d, h %d\n", fmt, imgwidth, imgheight);
1089 if (fmt == MPP_FMT_YUV422SP) {
1090 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_LEN_ALIGN, rkv_len_align_422);
1091 }
1092 if (MPP_FRAME_FMT_IS_FBC(fmt)) {
1093 vdpu383_afbc_align_calc(p_hal->frame_slots, (MppFrame)param, 16);
1094 } else if (imgwidth > 1920 || imgheight > 1088) {
1095 mpp_slots_set_prop(p_hal->frame_slots, SLOTS_HOR_ALIGN, mpp_align_128_odd_plus_64);
1096 }
1097 } break;
1098 case MPP_DEC_GET_THUMBNAIL_FRAME_INFO: {
1099 vdpu383_update_thumbnail_frame_info((MppFrame)param);
1100 } break;
1101 case MPP_DEC_SET_OUTPUT_FORMAT: {
1102 } break;
1103 default : {
1104 } break;
1105 }
1106
1107 __RETURN:
1108 return ret = MPP_OK;
1109 }
1110
1111 const MppHalApi hal_h264d_vdpu383 = {
1112 .name = "h264d_vdpu383",
1113 .type = MPP_CTX_DEC,
1114 .coding = MPP_VIDEO_CodingAVC,
1115 .ctx_size = sizeof(Vdpu383H264dRegCtx),
1116 .flag = 0,
1117 .init = vdpu383_h264d_init,
1118 .deinit = vdpu383_h264d_deinit,
1119 .reg_gen = vdpu383_h264d_gen_regs,
1120 .start = vdpu383_h264d_start,
1121 .wait = vdpu383_h264d_wait,
1122 .reset = vdpu383_h264d_reset,
1123 .flush = vdpu383_h264d_flush,
1124 .control = vdpu383_h264d_control,
1125 };
1126