1*437bfbebSnyanmisaka /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2*437bfbebSnyanmisaka /* 3*437bfbebSnyanmisaka * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4*437bfbebSnyanmisaka */ 5*437bfbebSnyanmisaka 6*437bfbebSnyanmisaka #ifndef __HAL_AVS2D_GLOBAL_H__ 7*437bfbebSnyanmisaka #define __HAL_AVS2D_GLOBAL_H__ 8*437bfbebSnyanmisaka 9*437bfbebSnyanmisaka #include "mpp_device.h" 10*437bfbebSnyanmisaka #include "hal_bufs.h" 11*437bfbebSnyanmisaka 12*437bfbebSnyanmisaka #include "parser_api.h" 13*437bfbebSnyanmisaka #include "hal_avs2d_api.h" 14*437bfbebSnyanmisaka #include "avs2d_syntax.h" 15*437bfbebSnyanmisaka 16*437bfbebSnyanmisaka #define AVS2D_HAL_DBG_ERROR (0x00000001) 17*437bfbebSnyanmisaka #define AVS2D_HAL_DBG_ASSERT (0x00000002) 18*437bfbebSnyanmisaka #define AVS2D_HAL_DBG_WARNNING (0x00000004) 19*437bfbebSnyanmisaka #define AVS2D_HAL_DBG_TRACE (0x00000100) 20*437bfbebSnyanmisaka #define AVS2D_HAL_DBG_REG (0x00000200) 21*437bfbebSnyanmisaka #define AVS2D_HAL_DBG_IN (0x00000400) 22*437bfbebSnyanmisaka #define AVS2D_HAL_DBG_OUT (0x00000800) 23*437bfbebSnyanmisaka 24*437bfbebSnyanmisaka #define AVS2D_HAL_DBG_OFFSET (0x00010000) 25*437bfbebSnyanmisaka 26*437bfbebSnyanmisaka extern RK_U32 avs2d_hal_debug; 27*437bfbebSnyanmisaka 28*437bfbebSnyanmisaka #define AVS2D_HAL_DBG(level, fmt, ...)\ 29*437bfbebSnyanmisaka do {\ 30*437bfbebSnyanmisaka if (level & avs2d_hal_debug)\ 31*437bfbebSnyanmisaka { mpp_log(fmt, ## __VA_ARGS__); }\ 32*437bfbebSnyanmisaka } while (0) 33*437bfbebSnyanmisaka 34*437bfbebSnyanmisaka #define AVS2D_HAL_TRACE(fmt, ...)\ 35*437bfbebSnyanmisaka do {\ 36*437bfbebSnyanmisaka if (AVS2D_HAL_DBG_TRACE & avs2d_hal_debug)\ 37*437bfbebSnyanmisaka { mpp_log_f(fmt, ## __VA_ARGS__); }\ 38*437bfbebSnyanmisaka } while (0) 39*437bfbebSnyanmisaka 40*437bfbebSnyanmisaka 41*437bfbebSnyanmisaka #define INP_CHECK(ret, val, ...)\ 42*437bfbebSnyanmisaka do{\ 43*437bfbebSnyanmisaka if ((val)) { \ 44*437bfbebSnyanmisaka ret = MPP_ERR_INIT; \ 45*437bfbebSnyanmisaka AVS2D_HAL_DBG(AVS2D_HAL_DBG_WARNNING, "input empty(%d).\n", __LINE__); \ 46*437bfbebSnyanmisaka goto __RETURN; \ 47*437bfbebSnyanmisaka }\ 48*437bfbebSnyanmisaka } while (0) 49*437bfbebSnyanmisaka 50*437bfbebSnyanmisaka 51*437bfbebSnyanmisaka #define FUN_CHECK(val)\ 52*437bfbebSnyanmisaka do{\ 53*437bfbebSnyanmisaka if ((val) < 0) {\ 54*437bfbebSnyanmisaka AVS2D_HAL_DBG(AVS2D_HAL_DBG_WARNNING, "Function error(%d).\n", __LINE__); \ 55*437bfbebSnyanmisaka goto __FAILED; \ 56*437bfbebSnyanmisaka }\ 57*437bfbebSnyanmisaka } while (0) 58*437bfbebSnyanmisaka 59*437bfbebSnyanmisaka 60*437bfbebSnyanmisaka //!< memory malloc check 61*437bfbebSnyanmisaka #define MEM_CHECK(ret, val, ...)\ 62*437bfbebSnyanmisaka do{\ 63*437bfbebSnyanmisaka if (!(val)) {\ 64*437bfbebSnyanmisaka ret = MPP_ERR_MALLOC; \ 65*437bfbebSnyanmisaka mpp_err_f("malloc buffer error(%d).\n", __LINE__); \ 66*437bfbebSnyanmisaka goto __FAILED; \ 67*437bfbebSnyanmisaka }\ 68*437bfbebSnyanmisaka } while (0) 69*437bfbebSnyanmisaka 70*437bfbebSnyanmisaka 71*437bfbebSnyanmisaka #define FIELDPICTURE 0 72*437bfbebSnyanmisaka #define FRAMEPICTURE 1 73*437bfbebSnyanmisaka 74*437bfbebSnyanmisaka enum { 75*437bfbebSnyanmisaka IFRAME = 0, 76*437bfbebSnyanmisaka PFRAME = 1, 77*437bfbebSnyanmisaka BFRAME = 2 78*437bfbebSnyanmisaka }; 79*437bfbebSnyanmisaka 80*437bfbebSnyanmisaka typedef struct avs2d_hal_ctx_t { 81*437bfbebSnyanmisaka const MppHalApi *hal_api; 82*437bfbebSnyanmisaka MppDecCfgSet *cfg; 83*437bfbebSnyanmisaka MppBufSlots frame_slots; 84*437bfbebSnyanmisaka MppBufSlots packet_slots; 85*437bfbebSnyanmisaka MppBufferGroup buf_group; 86*437bfbebSnyanmisaka HalBufs cmv_bufs; 87*437bfbebSnyanmisaka RK_U32 mv_size; 88*437bfbebSnyanmisaka RK_U32 mv_count; 89*437bfbebSnyanmisaka MppCbCtx *dec_cb; 90*437bfbebSnyanmisaka MppDev dev; 91*437bfbebSnyanmisaka Avs2dSyntax_t syntax; 92*437bfbebSnyanmisaka RK_U32 fast_mode; 93*437bfbebSnyanmisaka 94*437bfbebSnyanmisaka void *reg_ctx; 95*437bfbebSnyanmisaka MppBuffer shph_buf; 96*437bfbebSnyanmisaka MppBuffer scalist_buf; 97*437bfbebSnyanmisaka 98*437bfbebSnyanmisaka RK_U32 frame_no; 99*437bfbebSnyanmisaka const MppDecHwCap *hw_info; 100*437bfbebSnyanmisaka } Avs2dHalCtx_t; 101*437bfbebSnyanmisaka 102*437bfbebSnyanmisaka #endif /*__HAL_AVS2D_GLOBAL_H__*/ 103