1*437bfbebSnyanmisaka /* 2*437bfbebSnyanmisaka * Copyright 2020 Rockchip Electronics Co. LTD 3*437bfbebSnyanmisaka * 4*437bfbebSnyanmisaka * Licensed under the Apache License, Version 2.0 (the "License"); 5*437bfbebSnyanmisaka * you may not use this file except in compliance with the License. 6*437bfbebSnyanmisaka * You may obtain a copy of the License at 7*437bfbebSnyanmisaka * 8*437bfbebSnyanmisaka * http://www.apache.org/licenses/LICENSE-2.0 9*437bfbebSnyanmisaka * 10*437bfbebSnyanmisaka * Unless required by applicable law or agreed to in writing, software 11*437bfbebSnyanmisaka * distributed under the License is distributed on an "AS IS" BASIS, 12*437bfbebSnyanmisaka * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13*437bfbebSnyanmisaka * See the License for the specific language governing permissions and 14*437bfbebSnyanmisaka * limitations under the License. 15*437bfbebSnyanmisaka */ 16*437bfbebSnyanmisaka 17*437bfbebSnyanmisaka #ifndef __HAL_H265E_DEBUG_H__ 18*437bfbebSnyanmisaka #define __HAL_H265E_DEBUG_H__ 19*437bfbebSnyanmisaka 20*437bfbebSnyanmisaka #include "mpp_debug.h" 21*437bfbebSnyanmisaka 22*437bfbebSnyanmisaka #define HAL_H265E_DBG_FUNCTION (0x00000001) 23*437bfbebSnyanmisaka #define HAL_H265E_DBG_SIMPLE (0x00000002) 24*437bfbebSnyanmisaka #define HAL_H265E_DBG_FLOW (0x00000004) 25*437bfbebSnyanmisaka #define HAL_H265E_DBG_DETAIL (0x00000008) 26*437bfbebSnyanmisaka 27*437bfbebSnyanmisaka #define HAL_H265E_DBG_REGS (0x00000010) 28*437bfbebSnyanmisaka #define HAL_H265E_DBG_CTL_REGS (0x00000020) 29*437bfbebSnyanmisaka #define HAL_H265E_DBG_RCKUT_REGS (0x00000040) 30*437bfbebSnyanmisaka #define HAL_H265E_DBG_WGT_REGS (0x00000080) 31*437bfbebSnyanmisaka #define HAL_H265E_DBG_RDO_REGS (0x000000C0) 32*437bfbebSnyanmisaka #define HAL_H265E_DBG_ST_REGS (0x00000100) /* status registers */ 33*437bfbebSnyanmisaka #define HAL_H265E_DBG_SMART_V3 (0x00000200) 34*437bfbebSnyanmisaka 35*437bfbebSnyanmisaka #define HAL_H265E_DBG_INPUT (0x00020000) 36*437bfbebSnyanmisaka #define HAL_H265E_DBG_OUTPUT (0x00040000) 37*437bfbebSnyanmisaka #define HAL_H265E_DBG_WRITE_IN_STREAM (0x00080000) 38*437bfbebSnyanmisaka #define HAL_H265E_DBG_WRITE_OUT_STREAM (0x00100000) 39*437bfbebSnyanmisaka 40*437bfbebSnyanmisaka #define hal_h265e_dbg(flag, fmt, ...) _mpp_dbg(hal_h265e_debug, flag, fmt, ## __VA_ARGS__) 41*437bfbebSnyanmisaka #define hal_h265e_dbg_f(flag, fmt, ...) _mpp_dbg_f(hal_h265e_debug, flag, fmt, ## __VA_ARGS__) 42*437bfbebSnyanmisaka 43*437bfbebSnyanmisaka #define hal_h265e_dbg_func(fmt, ...) hal_h265e_dbg_f(HAL_H265E_DBG_FUNCTION, fmt, ## __VA_ARGS__) 44*437bfbebSnyanmisaka #define hal_h265e_dbg_simple(fmt, ...) hal_h265e_dbg_f(HAL_H265E_DBG_SIMPLE, fmt, ## __VA_ARGS__) 45*437bfbebSnyanmisaka #define hal_h265e_dbg_flow(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_FLOW, fmt, ## __VA_ARGS__) 46*437bfbebSnyanmisaka #define hal_h265e_dbg_detail(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_DETAIL, fmt, ## __VA_ARGS__) 47*437bfbebSnyanmisaka 48*437bfbebSnyanmisaka #define hal_h265e_dbg_regs(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_REGS, fmt, ## __VA_ARGS__) 49*437bfbebSnyanmisaka #define hal_h265e_dbg_ctl(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_CTL_REGS, fmt, ## __VA_ARGS__) 50*437bfbebSnyanmisaka #define hal_h265e_dbg_rckut(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_RCKUT_REGS, fmt, ## __VA_ARGS__) 51*437bfbebSnyanmisaka #define hal_h265e_dbg_wgt(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_WGT_REGS, fmt, ## __VA_ARGS__) 52*437bfbebSnyanmisaka #define hal_h265e_dbg_rdo(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_RDO_REGS, fmt, ## __VA_ARGS__) 53*437bfbebSnyanmisaka #define hal_h265e_dbg_st(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_ST_REGS, fmt, ## __VA_ARGS__) 54*437bfbebSnyanmisaka #define hal_h265e_dbg_smartv3(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_SMART_V3, fmt, ## __VA_ARGS__) 55*437bfbebSnyanmisaka 56*437bfbebSnyanmisaka #define hal_h265e_dbg_input(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_INPUT, fmt, ## __VA_ARGS__) 57*437bfbebSnyanmisaka #define hal_h265e_dbg_output(fmt, ...) hal_h265e_dbg(HAL_H265E_DBG_OUTPUT, fmt, ## __VA_ARGS__) 58*437bfbebSnyanmisaka 59*437bfbebSnyanmisaka #define hal_h265e_enter() hal_h265e_dbg_flow("(%d) enter\n", __LINE__); 60*437bfbebSnyanmisaka #define hal_h265e_leave() hal_h265e_dbg_flow("(%d) leave\n", __LINE__); 61*437bfbebSnyanmisaka 62*437bfbebSnyanmisaka extern RK_U32 hal_h265e_debug; 63*437bfbebSnyanmisaka 64*437bfbebSnyanmisaka #endif 65