1 /* 2 * Copyright 2021 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __AV1D_COMMON_H__ 18 #define __AV1D_COMMON_H__ 19 20 #include "mpp_common.h" 21 #include "hal_av1d_common.h" 22 #define AV1_REF_SCALE_SHIFT 14 23 24 #define NUM_REF_FRAMES 8 25 #define NUM_REF_FRAMES_LG2 3 26 27 // Max tiles for AV1 (custom size) for Level <= 6.x 28 #define AV1_MAX_TILES 128 29 #define AV1_MAX_TILE_COL 64 30 #define AV1_MAX_TILE_ROW 64 31 32 // Pixels per Mode Info (MI) unit 33 #define MI_SIZE_LOG2 2 34 #define MI_SIZE (1 << MI_SIZE_LOG2) 35 36 #define AV1_MIN_COMP_BASIS 8 37 #define AV1_MAX_CODED_FRAME_SIZE \ 38 (8192 * 4352 * 10 * 6 / 32 / AV1_MIN_COMP_BASIS) /* approx 8 MB */ 39 40 #define ALLOWED_REFS_PER_FRAME_EX 7 41 42 #define NUM_FRAME_CONTEXTS_LG2_EX 3 43 #define NUM_FRAME_CONTEXTS_EX (1 << NUM_FRAME_CONTEXTS_LG2_EX) 44 45 #define MIN_TILE_WIDTH 256 46 #define MAX_TILE_WIDTH 4096 47 #define MIN_TILE_WIDTH_SBS (MIN_TILE_WIDTH >> 6) 48 #define MAX_TILE_WIDTH_SBS (MAX_TILE_WIDTH >> 6) 49 #define FRAME_OFFSET_BITS 5 50 #define MAX_TILE_AREA (4096 * 2304) 51 #define AV1_MAX_TILE_COLS 64 52 #define AV1_MAX_TILE_ROWS 64 53 54 #define ALLOWED_REFS_PER_FRAME 3 55 56 #define NUM_FRAME_CONTEXTS_LG2 2 57 #define NUM_FRAME_CONTEXTS (1 << NUM_FRAME_CONTEXTS_LG2) 58 59 #define DCPREDSIMTHRESH 0 60 #define DCPREDCNTTHRESH 3 61 62 #define PREDICTION_PROBS 3 63 64 #define DEFAULT_PRED_PROB_0 120 65 #define DEFAULT_PRED_PROB_1 80 66 #define DEFAULT_PRED_PROB_2 40 67 68 #define AV1_DEF_UPDATE_PROB 252 69 70 #define MBSKIP_CONTEXTS 3 71 72 #define MAX_MB_SEGMENTS 8 73 #define MB_SEG_TREE_PROBS (MAX_MB_SEGMENTS - 1) 74 75 #define MAX_REF_LF_DELTAS_EX 8 76 77 #define MAX_REF_LF_DELTAS 4 78 #define MAX_MODE_LF_DELTAS 2 79 80 /* Segment Feature Masks */ 81 #define SEGMENT_DELTADATA 0 82 #define SEGMENT_ABSDATA 1 83 #define MAX_MV_REFS 9 84 85 #define AV1_SWITCHABLE_FILTERS 3 /* number of switchable filters */ 86 #define SWITCHABLE_FILTER_CONTEXTS ((AV1_SWITCHABLE_FILTERS + 1) * 4) 87 #ifdef DUAL_FILTER 88 #define AV1_SWITCHABLE_EXT_FILTERS 4 /* number of switchable filters */ 89 #endif 90 91 #define COMP_PRED_CONTEXTS 2 92 93 #define COEF_UPDATE_PROB 252 94 #define AV1_PROB_HALF 128 95 #define AV1_NMV_UPDATE_PROB 252 96 #define AV1_MV_UPDATE_PRECISION 7 97 #define MV_JOINTS 4 98 #define MV_FP_SIZE 4 99 #define MV_CLASSES 11 100 #define CLASS0_BITS 1 101 #define CLASS0_SIZE (1 << CLASS0_BITS) 102 #define MV_OFFSET_BITS (MV_CLASSES + CLASS0_BITS - 2) 103 104 #define MV_MAX_BITS (MV_CLASSES + CLASS0_BITS + 2) 105 #define MV_MAX ((1 << MV_MAX_BITS) - 1) 106 #define MV_VALS ((MV_MAX << 1) + 1) 107 108 #define MAX_ENTROPY_TOKENS 12 109 #define ENTROPY_NODES 11 110 111 /* The first nodes of the entropy probs are unconstrained, the rest are 112 * modeled with statistic distribution. */ 113 #define UNCONSTRAINED_NODES 3 114 #define MODEL_NODES (ENTROPY_NODES - UNCONSTRAINED_NODES) 115 #define PIVOT_NODE 2 // which node is pivot 116 #define COEFPROB_MODELS 128 117 118 /* Entropy nodes above is divided in two parts, first three probs in part1 119 * and the modeled probs in part2. Part1 is padded so that tables align with 120 * 32 byte addresses, so there is four bytes for each table. */ 121 #define ENTROPY_NODES_PART1 4 122 #define ENTROPY_NODES_PART2 8 123 #define INTER_MODE_CONTEXTS 7 124 #define AV1_INTER_MODE_CONTEXTS 15 125 126 #define CFL_JOINT_SIGNS 8 127 #define CFL_ALPHA_CONTEXTS 6 128 #define CFL_ALPHABET_SIZE 16 129 130 #define NEWMV_MODE_CONTEXTS 6 131 #define ZEROMV_MODE_CONTEXTS 2 132 #define GLOBALMV_MODE_CONTEXTS 2 133 #define REFMV_MODE_CONTEXTS 9 134 #define DRL_MODE_CONTEXTS 3 135 #define NMV_CONTEXTS 3 136 137 #define INTRA_INTER_CONTEXTS 4 138 #define COMP_INTER_CONTEXTS 5 139 #define REF_CONTEXTS 5 140 #define AV1_REF_CONTEXTS 3 141 #define FWD_REFS 4 142 #define BWD_REFS 3 143 #define SINGLE_REFS 7 144 145 #define BLOCK_TYPES 2 146 #define REF_TYPES 2 // intra=0, inter=1 147 #define COEF_BANDS 6 148 #define PREV_COEF_CONTEXTS 6 149 150 #define MODULUS_PARAM 13 /* Modulus parameter */ 151 152 #define ACTIVE_HT 110 // quantization stepsize threshold 153 154 #define MAX_MV_REF_CANDIDATES 2 155 156 /* Coefficient token alphabet */ 157 158 #define ZERO_TOKEN 0 /* 0 Extra Bits 0+0 */ 159 #define ONE_TOKEN 1 /* 1 Extra Bits 0+1 */ 160 #define TWO_TOKEN 2 /* 2 Extra Bits 0+1 */ 161 #define THREE_TOKEN 3 /* 3 Extra Bits 0+1 */ 162 #define FOUR_TOKEN 4 /* 4 Extra Bits 0+1 */ 163 #define DCT_VAL_CATEGORY1 5 /* 5-6 Extra Bits 1+1 */ 164 #define DCT_VAL_CATEGORY2 6 /* 7-10 Extra Bits 2+1 */ 165 #define DCT_VAL_CATEGORY3 7 /* 11-18 Extra Bits 3+1 */ 166 #define DCT_VAL_CATEGORY4 8 /* 19-34 Extra Bits 4+1 */ 167 #define DCT_VAL_CATEGORY5 9 /* 35-66 Extra Bits 5+1 */ 168 #define DCT_VAL_CATEGORY6 10 /* 67+ Extra Bits 13+1 */ 169 #define DCT_EOB_TOKEN 11 /* EOB Extra Bits 0+0 */ 170 #define MAX_ENTROPY_TOKENS 12 171 172 #define INTERINTRA_MODES 4 173 #define INTER_COMPOUND_MODES 8 174 #define COMPOUND_TYPES 3 175 #define HEAD_TOKENS 5 176 #define TAIL_TOKENS 9 177 #define ONE_TOKEN_EOB 1 178 #define ONE_TOKEN_NEOB 2 179 180 #define MULTICORE_LEFT_TILE 1 181 #define MULTICORE_INNER_TILE 2 182 #define MULTICORE_RIGHT_TILE 3 183 184 #define DCT_EOB_MODEL_TOKEN 3 /* EOB Extra Bits 0+0 */ 185 186 typedef RK_U32 av1_coeff_count[REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] 187 [UNCONSTRAINED_NODES + 1]; 188 typedef RK_U8 av1_coeff_probs[REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] 189 [UNCONSTRAINED_NODES]; 190 191 #define BLOCK_SIZE_GROUPS 4 192 193 // AV1 extended transforms (ext_tx) 194 #define EXT_TX_SETS_INTER 4 // Sets of transform selections for INTER 195 #define EXT_TX_SETS_INTRA 3 // Sets of transform selections for INTRA 196 #define EXTTX_SIZES 4 // ext_tx experiment tx sizes 197 #define EXT_TX_TYPES 16 198 199 #define EXT_TX_SIZES 3 200 201 #define TX_TYPES 4 202 203 #define ROUND_POWER_OF_TWO(value, n) (((value) + (1 << ((n)-1))) >> (n)) 204 205 /* Shift down with rounding for use when n >= 0, value >= 0 for (64 bit) */ 206 #define ROUND_POWER_OF_TWO_64(value, n) \ 207 (((value) + ((((int64)1 << (n)) >> 1))) >> (n)) 208 209 /* Shift down with rounding for signed integers, for use when n >= 0 (64 bit) */ 210 #define ROUND_POWER_OF_TWO_SIGNED_64(value, n) \ 211 (((value) < 0) ? -ROUND_POWER_OF_TWO_64(-(value), (n)) \ 212 : ROUND_POWER_OF_TWO_64((value), (n))) 213 214 /* Shift down with rounding for signed integers, for use when n >= 0 */ 215 #define ROUND_POWER_OF_TWO_SIGNED(value, n) \ 216 (((value) < 0) ? -ROUND_POWER_OF_TWO(-(value), (n)) \ 217 : ROUND_POWER_OF_TWO((value), (n))) 218 219 typedef RK_U16 av1_cdf; 220 221 // Frame Restoration types (section 6.10.15) 222 enum { 223 AV1_RESTORE_NONE = 0, 224 AV1_RESTORE_WIENER = 1, 225 AV1_RESTORE_SGRPROJ = 2, 226 AV1_RESTORE_SWITCHABLE = 3, 227 }; 228 229 enum BlockSizeType { 230 BLOCK_SIZE_AB4X4, 231 BLOCK_SIZE_SB4X8, 232 BLOCK_SIZE_SB8X4, 233 BLOCK_SIZE_SB8X8, 234 BLOCK_SIZE_SB8X16, 235 BLOCK_SIZE_SB16X8, 236 BLOCK_SIZE_MB16X16, 237 BLOCK_SIZE_SB16X32, 238 BLOCK_SIZE_SB32X16, 239 BLOCK_SIZE_SB32X32, 240 BLOCK_SIZE_SB32X64, 241 BLOCK_SIZE_SB64X32, 242 BLOCK_SIZE_SB64X64, 243 BLOCK_SIZE_SB64X128, 244 BLOCK_SIZE_SB128X64, 245 BLOCK_SIZE_SB128X128, 246 BLOCK_SIZE_SB4X16, 247 BLOCK_SIZE_SB16X4, 248 BLOCK_SIZE_SB8X32, 249 BLOCK_SIZE_SB32X8, 250 BLOCK_SIZE_SB16X64, 251 BLOCK_SIZE_SB64X16, 252 BLOCK_SIZE_TYPES, 253 BLOCK_SIZES_ALL = BLOCK_SIZE_TYPES 254 }; 255 256 enum PartitionType { 257 PARTITION_NONE, 258 PARTITION_HORZ, 259 PARTITION_VERT, 260 PARTITION_SPLIT, 261 /* 262 PARTITION_HORZ_A, 263 PARTITION_HORZ_B, 264 PARTITION_VERT_A, 265 PARTITION_VERT_B, 266 PARTITION_HORZ_4, 267 PARTITION_VERT_4, 268 */ 269 PARTITION_TYPES 270 }; 271 272 #define PARTITION_PLOFFSET 4 // number of probability models per block size 273 #define NUM_PARTITION_CONTEXTS (4 * PARTITION_PLOFFSET) 274 275 enum FrameType { 276 KEY_FRAME = 0, 277 INTER_FRAME = 1, 278 INTRA_ONLY_FRAME = 2, // replaces intra-only 279 S_FRAME = 3, 280 NUM_FRAME_TYPES, 281 }; 282 283 enum MbPredictionMode { 284 DC_PRED, /* average of above and left pixels */ 285 V_PRED, /* vertical prediction */ 286 H_PRED, /* horizontal prediction */ 287 D45_PRED, /* Directional 45 deg prediction [anti-clockwise from 0 deg hor] */ 288 D135_PRED, /* Directional 135 deg prediction [anti-clockwise from 0 deg hor] 289 */ 290 D117_PRED, /* Directional 112 deg prediction [anti-clockwise from 0 deg hor] 291 */ 292 D153_PRED, /* Directional 157 deg prediction [anti-clockwise from 0 deg hor] 293 */ 294 D27_PRED, /* Directional 22 deg prediction [anti-clockwise from 0 deg hor] */ 295 D63_PRED, /* Directional 67 deg prediction [anti-clockwise from 0 deg hor] */ 296 SMOOTH_PRED, 297 TM_PRED_AV1 = SMOOTH_PRED, 298 SMOOTH_V_PRED, // Vertical interpolation 299 SMOOTH_H_PRED, // Horizontal interpolation 300 TM_PRED, /* Truemotion prediction */ 301 PAETH_PRED = TM_PRED, 302 NEARESTMV, 303 NEARMV, 304 ZEROMV, 305 NEWMV, 306 NEAREST_NEARESTMV, 307 NEAR_NEARMV, 308 NEAREST_NEWMV, 309 NEW_NEARESTMV, 310 NEAR_NEWMV, 311 NEW_NEARMV, 312 ZERO_ZEROMV, 313 NEW_NEWMV, 314 SPLITMV, 315 MB_MODE_COUNT 316 }; 317 318 // Must match hardware/src/include/common_defs.h 319 #define AV1_INTRA_MODES 13 320 321 #define MAX_INTRA_MODES AV1_INTRA_MODES 322 323 #define MAX_INTRA_MODES_DRAM_ALIGNED ((MAX_INTRA_MODES + 15) & (~15)) 324 325 #define AV1_INTER_MODES (1 + NEWMV - NEARESTMV) 326 327 #define MOTION_MODE_CONTEXTS 10 328 329 #define DIRECTIONAL_MODES 8 330 #define MAX_ANGLE_DELTA 3 331 332 enum FilterIntraModeType { 333 FILTER_DC_PRED, 334 FILTER_V_PRED, 335 FILTER_H_PRED, 336 FILTER_D153_PRED, 337 FILTER_PAETH_PRED, 338 FILTER_INTRA_MODES, 339 FILTER_INTRA_UNUSED = 7 340 }; 341 342 #define FILTER_INTRA_SIZES 19 343 344 enum { SIMPLE_TRANSLATION, OBMC_CAUSAL, MOTION_MODE_COUNT }; 345 346 #define SUBMVREF_COUNT 5 347 348 /* Integer pel reference mv threshold for use of high-precision 1/8 mv */ 349 #define COMPANDED_MVREF_THRESH 8 350 351 #define TX_SIZE_CONTEXTS 2 352 #define AV1_TX_SIZE_CONTEXTS 3 353 #define VARTX_PART_CONTEXTS 22 354 #define TXFM_PARTITION_CONTEXTS 22 355 356 enum InterpolationFilterType { 357 EIGHTTAP_SMOOTH, 358 EIGHTTAP, 359 EIGHTTAP_SHARP, 360 #ifdef DUAL_FILTER 361 EIGHTTAP_SMOOTH2, 362 BILINEAR, 363 SWITCHABLE, /* should be the last one */ 364 #else 365 BILINEAR, 366 SWITCHABLE, /* should be the last one */ 367 #endif 368 MULTITAP_SHARP = EIGHTTAP_SHARP 369 }; 370 371 static const int av1_literal_to_filter[4] = { 372 EIGHTTAP_SMOOTH, EIGHTTAP, 373 EIGHTTAP_SHARP, BILINEAR 374 }; 375 376 extern const enum InterpolationFilterType 377 av1hwd_switchable_interp[AV1_SWITCHABLE_FILTERS]; 378 379 enum CompPredModeType { 380 SINGLE_PREDICTION_ONLY = 0, 381 COMP_PREDICTION_ONLY = 1, 382 HYBRID_PREDICTION = 2, 383 NB_PREDICTION_TYPES = 3, 384 }; 385 386 enum TxfmMode { 387 ONLY_4X4 = 0, 388 TX_MODE_LARGEST, 389 TX_MODE_SELECT, 390 NB_TXFM_MODES, 391 }; 392 393 enum SegLevelFeatures { 394 SEG_LVL_ALT_Q = 0, 395 SEG_LVL_ALT_LF = 1, 396 SEG_LVL_REF_FRAME = 2, 397 SEG_LVL_SKIP = 3, 398 SEG_LVL_MAX = 4 399 }; 400 401 enum { AV1_SEG_FEATURE_DELTA, AV1_SEG_FEATURE_ABS }; 402 403 static const int av1_seg_feature_data_signed[SEG_AV1_LVL_MAX] = { 404 1, 1, 1, 1, 405 1, 0, 0 406 }; 407 408 static const int av1_seg_feature_data_max[SEG_AV1_LVL_MAX] = { 409 255, 63, 63, 63, 410 63, 7, 0 411 }; 412 413 static const int av1_seg_feature_data_bits[SEG_AV1_LVL_MAX] = { 414 8, 6, 6, 6, 415 6, 3, 0 416 }; 417 418 enum TxSize { 419 TX_4X4 = 0, 420 TX_8X8 = 1, 421 TX_16X16 = 2, 422 TX_32X32 = 3, 423 TX_SIZE_MAX_SB, 424 }; 425 #define MAX_TX_DEPTH 2 426 427 enum TxType { DCT_DCT = 0, ADST_DCT = 1, DCT_ADST = 2, ADST_ADST = 3 }; 428 429 enum SplitMvPartitioningType { 430 PARTITIONING_16X8 = 0, 431 PARTITIONING_8X16, 432 PARTITIONING_8X8, 433 PARTITIONING_4X4, 434 NB_PARTITIONINGS, 435 }; 436 437 enum PredId { 438 PRED_SEG_ID = 0, 439 PRED_MBSKIP = 1, 440 PRED_SWITCHABLE_INTERP = 2, 441 PRED_INTRA_INTER = 3, 442 PRED_COMP_INTER_INTER = 4, 443 PRED_SINGLE_REF_P1 = 5, 444 PRED_SINGLE_REF_P2 = 6, 445 PRED_COMP_REF_P = 7, 446 PRED_TX_SIZE = 8 447 }; 448 449 /* Symbols for coding which components are zero jointly */ 450 enum MvJointType { 451 MV_JOINT_ZERO = 0, /* Zero vector */ 452 MV_JOINT_HNZVZ = 1, /* Vert zero, hor nonzero */ 453 MV_JOINT_HZVNZ = 2, /* Hor zero, vert nonzero */ 454 MV_JOINT_HNZVNZ = 3, /* Both components nonzero */ 455 }; 456 457 /* Symbols for coding magnitude class of nonzero components */ 458 enum MvClassType { 459 MV_CLASS_0 = 0, /* (0, 2] integer pel */ 460 MV_CLASS_1 = 1, /* (2, 4] integer pel */ 461 MV_CLASS_2 = 2, /* (4, 8] integer pel */ 462 MV_CLASS_3 = 3, /* (8, 16] integer pel */ 463 MV_CLASS_4 = 4, /* (16, 32] integer pel */ 464 MV_CLASS_5 = 5, /* (32, 64] integer pel */ 465 MV_CLASS_6 = 6, /* (64, 128] integer pel */ 466 MV_CLASS_7 = 7, /* (128, 256] integer pel */ 467 MV_CLASS_8 = 8, /* (256, 512] integer pel */ 468 MV_CLASS_9 = 9, /* (512, 1024] integer pel */ 469 MV_CLASS_10 = 10, /* (1024,2048] integer pel */ 470 }; 471 472 enum RefreshFrameContextModeAv1 { 473 /** 474 * AV1 Only, no refresh 475 */ 476 AV1_REFRESH_FRAME_CONTEXT_NONE, 477 /** 478 * Update frame context to values resulting from backward probability 479 * updates based on entropy/counts in the decoded frame 480 */ 481 AV1_REFRESH_FRAME_CONTEXT_BACKWARD 482 }; 483 484 // 75B 485 struct NmvContext { 486 // Start at +27B offset 487 RK_U8 joints[MV_JOINTS - 1]; // 3B 488 RK_U8 sign[2]; // 2B 489 490 // A+1 491 RK_U8 class0[2][CLASS0_SIZE - 1]; // 2B 492 RK_U8 fp[2][MV_FP_SIZE - 1]; // 6B 493 RK_U8 class0_hp[2]; // 2B 494 RK_U8 hp[2]; // 2B 495 RK_U8 classes[2][MV_CLASSES - 1]; // 20B 496 497 // A+2 498 RK_U8 class0_fp[2][CLASS0_SIZE][MV_FP_SIZE - 1]; // 12B 499 RK_U8 bits[2][MV_OFFSET_BITS]; // 20B 500 }; 501 502 struct NmvContextCounts { 503 // 8dw (u32) / DRAM word (u256) 504 RK_U32 joints[MV_JOINTS]; 505 RK_U32 sign[2][2]; 506 RK_U32 classes[2][MV_CLASSES]; 507 RK_U32 class0[2][CLASS0_SIZE]; 508 RK_U32 bits[2][MV_OFFSET_BITS][2]; 509 RK_U32 class0_fp[2][CLASS0_SIZE][4]; 510 RK_U32 fp[2][4]; 511 RK_U32 class0_hp[2][2]; 512 RK_U32 hp[2][2]; 513 }; 514 515 typedef RK_U8 av1_prob; 516 517 #define ICDF(x) (32768U - (x)) 518 #define CDF_SIZE(x) ((x)-1) 519 520 #define AV1HWPAD(x, y) RK_U8 x[y] 521 522 struct NmvJointSign { 523 RK_U8 joints[MV_JOINTS - 1]; // 3B 524 RK_U8 sign[2]; // 2B 525 }; 526 527 struct NmvMagnitude { 528 RK_U8 class0[2][CLASS0_SIZE - 1]; 529 RK_U8 fp[2][MV_FP_SIZE - 1]; 530 RK_U8 class0_hp[2]; 531 RK_U8 hp[2]; 532 RK_U8 classes[2][MV_CLASSES - 1]; 533 RK_U8 class0_fp[2][CLASS0_SIZE][MV_FP_SIZE - 1]; 534 RK_U8 bits[2][MV_OFFSET_BITS]; 535 }; 536 537 struct RefMvNmvContext { 538 // Starts at +4B offset (for mbskip) 539 struct NmvJointSign joints_sign[NMV_CONTEXTS]; // 15B 540 AV1HWPAD(pad1, 13); 541 542 // A+1 543 struct NmvMagnitude magnitude[NMV_CONTEXTS]; 544 }; 545 546 /* Adaptive entropy contexts, padding elements are added to have 547 * 256 bit aligned tables for HW access. 548 * Compile with TRACE_PROB_TABLES to print bases for each table. */ 549 struct Av1AdaptiveEntropyProbs { 550 // address A (56) 551 552 // Address A+0 553 RK_U8 inter_mode_prob[INTER_MODE_CONTEXTS][4]; // 7*4 = 28B 554 RK_U8 intra_inter_prob[INTRA_INTER_CONTEXTS]; // 4B 555 556 // Address A+1 557 RK_U8 uv_mode_prob[MAX_INTRA_MODES] 558 [MAX_INTRA_MODES_DRAM_ALIGNED]; // 10*16/32 = 5 addrs 559 560 #if ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32) 561 AV1HWPAD(pad1, 562 ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32 == 0) 563 ? 0 564 : 32 - (MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32); 565 #endif 566 567 // Address A+6 568 RK_U8 tx8x8_prob[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 3]; // 2*(4-3) = 2B 569 RK_U8 tx16x16_prob[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 2]; // 2*(4-2) = 4B 570 RK_U8 tx32x32_prob[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 1]; // 2*(4-1) = 6B 571 572 RK_U8 switchable_interp_prob[AV1_SWITCHABLE_FILTERS + 1] 573 [AV1_SWITCHABLE_FILTERS - 1]; // 8B 574 RK_U8 comp_inter_prob[COMP_INTER_CONTEXTS]; // 5B 575 576 AV1HWPAD(pad6, 7); 577 578 // Address A+7 579 RK_U8 sb_ymode_prob[BLOCK_SIZE_GROUPS] 580 [MAX_INTRA_MODES_DRAM_ALIGNED]; // 4*16/32 = 2 addrs 581 582 // Address A+9 583 RK_U8 partition_prob[NUM_FRAME_TYPES][NUM_PARTITION_CONTEXTS] 584 [PARTITION_TYPES]; // 2*16*4 = 4 addrs 585 586 // Address A+13 587 AV1HWPAD(pad13, 24); 588 RK_U8 mbskip_probs[MBSKIP_CONTEXTS]; // 3B 589 struct NmvContext nmvc; 590 591 // Address A+16 592 RK_U8 single_ref_prob[REF_CONTEXTS][2]; // 10B 593 RK_U8 comp_ref_prob[REF_CONTEXTS]; // 5B 594 RK_U8 mb_segment_tree_probs[MB_SEG_TREE_PROBS]; // 7B 595 RK_U8 segment_pred_probs[PREDICTION_PROBS]; // 3B 596 AV1HWPAD(pad16, 7); 597 598 // Address A+17 599 RK_U8 prob_coeffs[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] 600 [ENTROPY_NODES_PART1]; // 18 addrs 601 RK_U8 prob_coeffs8x8[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] 602 [ENTROPY_NODES_PART1]; 603 RK_U8 prob_coeffs16x16[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] 604 [ENTROPY_NODES_PART1]; 605 RK_U8 prob_coeffs32x32[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS] 606 [ENTROPY_NODES_PART1]; 607 }; 608 609 /* Entropy contexts */ 610 struct Av1EntropyProbs { 611 /* Default keyframe probs */ 612 /* Table formatted for 256b memory, probs 0to7 for all tables followed by 613 * probs 8toN for all tables. 614 * Compile with TRACE_PROB_TABLES to print bases for each table. */ 615 616 // In AOM code, this table is [M][M][M-1]; we pad to 16B so each entry is 1/2 617 // DRAM word. 618 RK_U8 kf_bmode_prob[MAX_INTRA_MODES][MAX_INTRA_MODES] 619 [MAX_INTRA_MODES_DRAM_ALIGNED]; 620 621 #if ((MAX_INTRA_MODES * MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32) 622 AV1HWPAD(pad0, (((MAX_INTRA_MODES * MAX_INTRA_MODES * 623 MAX_INTRA_MODES_DRAM_ALIGNED) % 624 32) == 0) 625 ? 0 626 : 32 - ((MAX_INTRA_MODES * MAX_INTRA_MODES * 627 MAX_INTRA_MODES_DRAM_ALIGNED) % 628 32)); 629 #endif 630 631 // Address 50 632 AV1HWPAD(unused_bytes, 4); // 4B of padding to maintain the old alignments. 633 RK_U8 ref_pred_probs[PREDICTION_PROBS]; // 3B 634 RK_U8 ref_scores[MAX_REF_FRAMES]; // 4B 635 RK_U8 prob_comppred[COMP_PRED_CONTEXTS]; // 2B 636 637 AV1HWPAD(pad1, 19); 638 639 // Address 51 640 RK_U8 kf_uv_mode_prob[MAX_INTRA_MODES][MAX_INTRA_MODES_DRAM_ALIGNED]; 641 642 #if ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32) 643 AV1HWPAD(pad51, 644 ((MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32 == 0) 645 ? 0 646 : 32 - (MAX_INTRA_MODES * MAX_INTRA_MODES_DRAM_ALIGNED) % 32); 647 #endif 648 649 // Address 56 650 struct Av1AdaptiveEntropyProbs a; // Probs with backward adaptation 651 }; 652 653 /* Counters for adaptive entropy contexts */ 654 struct Av1EntropyCounts { 655 RK_U32 inter_mode_counts[INTER_MODE_CONTEXTS][AV1_INTER_MODES - 1][2]; 656 RK_U32 sb_ymode_counts[BLOCK_SIZE_GROUPS][MAX_INTRA_MODES]; 657 RK_U32 uv_mode_counts[MAX_INTRA_MODES][MAX_INTRA_MODES]; 658 RK_U32 partition_counts[NUM_PARTITION_CONTEXTS][PARTITION_TYPES]; 659 RK_U32 switchable_interp_counts[AV1_SWITCHABLE_FILTERS + 1] 660 [AV1_SWITCHABLE_FILTERS]; 661 RK_U32 intra_inter_count[INTRA_INTER_CONTEXTS][2]; 662 RK_U32 comp_inter_count[COMP_INTER_CONTEXTS][2]; 663 RK_U32 single_ref_count[REF_CONTEXTS][2][2]; 664 RK_U32 comp_ref_count[REF_CONTEXTS][2]; 665 RK_U32 tx32x32_count[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB]; 666 RK_U32 tx16x16_count[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 1]; 667 RK_U32 tx8x8_count[TX_SIZE_CONTEXTS][TX_SIZE_MAX_SB - 2]; 668 RK_U32 mbskip_count[MBSKIP_CONTEXTS][2]; 669 670 struct NmvContextCounts nmvcount; 671 672 RK_U32 count_coeffs[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1]; 673 RK_U32 count_coeffs8x8[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1]; 674 RK_U32 count_coeffs16x16[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1]; 675 RK_U32 count_coeffs32x32[BLOCK_TYPES][REF_TYPES][COEF_BANDS][PREV_COEF_CONTEXTS][UNCONSTRAINED_NODES + 1]; 676 677 RK_U32 count_eobs[TX_SIZE_MAX_SB][BLOCK_TYPES][REF_TYPES][COEF_BANDS] 678 [PREV_COEF_CONTEXTS]; 679 }; 680 681 struct CoeffHeadCDFModel { 682 RK_U16 band0[3][5]; 683 RK_U16 bands[5][6][4]; 684 }; 685 686 struct CoeffTailCDFModel { 687 RK_U16 band0[3][9]; 688 RK_U16 bands[5][6][9]; 689 }; 690 691 // 135 692 typedef struct CoeffHeadCDFModel coeff_head_cdf_model[BLOCK_TYPES][REF_TYPES]; 693 // 297 694 typedef struct CoeffTailCDFModel coeff_tail_cdf_model[BLOCK_TYPES][REF_TYPES]; 695 696 //#define PALETTE_BLOCK_SIZES (BLOCK_SIZE_SB64X64 - BLOCK_SIZE_SB8X8 + 1) 697 #define PALETTE_BLOCK_SIZES 7 698 #define PALETTE_SIZES 7 699 #define PALETTE_Y_MODE_CONTEXTS 3 700 #define PALETTE_UV_MODE_CONTEXTS 2 701 #define PALETTE_COLOR_INDEX_CONTEXTS 5 702 #define PALETTE_IDX_CONTEXTS 18 703 #define PALETTE_COLORS 8 704 #define KF_MODE_CONTEXTS 5 705 706 #define PLANE_TYPES 2 707 #define TX_SIZES 5 708 #define TXB_SKIP_CONTEXTS 13 709 #define DC_SIGN_CONTEXTS 3 710 #define SIG_COEF_CONTEXTS_EOB 4 711 #define SIG_COEF_CONTEXTS 42 712 #define COEFF_BASE_CONTEXTS 42 713 #define EOB_COEF_CONTEXTS 9 714 #define LEVEL_CONTEXTS 21 715 #define NUM_BASE_LEVELS 2 716 #define BR_CDF_SIZE 4 717 #define MOTION_MODES 3 718 #define DELTA_Q_PROBS 3 719 #define COMP_REF_TYPE_CONTEXTS 5 720 #define UNI_COMP_REF_CONTEXTS 3 721 #define UNIDIR_COMP_REFS 4 722 //#define FILTER_INTRA_MODES 5 723 #define SKIP_MODE_CONTEXTS 3 724 #define SKIP_CONTEXTS 3 725 #define COMP_INDEX_CONTEXTS 6 726 #define COMP_GROUP_IDX_CONTEXTS 7 727 #define MAX_TX_CATS 4 728 #define CFL_ALLOWED_TYPES 2 729 #define UV_INTRA_MODES 14 730 #define EXT_PARTITION_TYPES 10 731 #define AV1_PARTITION_CONTEXTS (5 * PARTITION_PLOFFSET) 732 733 #define RESTORE_SWITCHABLE_TYPES 3 734 #define DELTA_LF_PROBS 3 735 #define FRAME_LF_COUNT 4 736 #define MAX_SEGMENTS 8 737 #define TOKEN_CDF_Q_CTXS 4 738 #define SEG_TEMPORAL_PRED_CTXS 3 739 #define SPATIAL_PREDICTION_PROBS 3 740 741 typedef RK_U16 aom_cdf_prob; 742 743 typedef struct { 744 RK_U16 joint_cdf[3]; 745 RK_U16 sign_cdf[2]; 746 RK_U16 clsss_cdf[2][10]; 747 RK_U16 clsss0_fp_cdf[2][2][3]; 748 RK_U16 fp_cdf[2][3]; 749 RK_U16 class0_hp_cdf[2]; 750 RK_U16 hp_cdf[2]; 751 RK_U16 class0_cdf[2]; 752 RK_U16 bits_cdf[2][10]; 753 } MvCDFs; 754 755 typedef struct { 756 RK_U16 partition_cdf[13][16]; 757 // 64 758 RK_U16 kf_ymode_cdf[KF_MODE_CONTEXTS][KF_MODE_CONTEXTS][AV1_INTRA_MODES - 1]; 759 RK_U16 segment_pred_cdf[PREDICTION_PROBS]; 760 RK_U16 spatial_pred_seg_tree_cdf[SPATIAL_PREDICTION_PROBS][MAX_MB_SEGMENTS - 1]; 761 RK_U16 mbskip_cdf[MBSKIP_CONTEXTS]; 762 RK_U16 delta_q_cdf[DELTA_Q_PROBS]; 763 RK_U16 delta_lf_multi_cdf[FRAME_LF_COUNT][DELTA_LF_PROBS]; 764 RK_U16 delta_lf_cdf[DELTA_LF_PROBS]; 765 RK_U16 skip_mode_cdf[SKIP_MODE_CONTEXTS]; 766 RK_U16 vartx_part_cdf[VARTX_PART_CONTEXTS][1]; 767 RK_U16 tx_size_cdf[MAX_TX_CATS][AV1_TX_SIZE_CONTEXTS][MAX_TX_DEPTH]; 768 RK_U16 if_ymode_cdf[BLOCK_SIZE_GROUPS][AV1_INTRA_MODES - 1]; 769 RK_U16 uv_mode_cdf[2][AV1_INTRA_MODES][AV1_INTRA_MODES - 1 + 1]; 770 RK_U16 intra_inter_cdf[INTRA_INTER_CONTEXTS]; 771 RK_U16 comp_inter_cdf[COMP_INTER_CONTEXTS]; 772 RK_U16 single_ref_cdf[AV1_REF_CONTEXTS][SINGLE_REFS - 1]; 773 RK_U16 comp_ref_type_cdf[COMP_REF_TYPE_CONTEXTS][1]; 774 RK_U16 uni_comp_ref_cdf[UNI_COMP_REF_CONTEXTS][UNIDIR_COMP_REFS - 1][1]; 775 RK_U16 comp_ref_cdf[AV1_REF_CONTEXTS][FWD_REFS - 1]; 776 RK_U16 comp_bwdref_cdf[AV1_REF_CONTEXTS][BWD_REFS - 1]; 777 RK_U16 newmv_cdf[NEWMV_MODE_CONTEXTS]; 778 RK_U16 zeromv_cdf[ZEROMV_MODE_CONTEXTS]; 779 RK_U16 refmv_cdf[REFMV_MODE_CONTEXTS]; 780 RK_U16 drl_cdf[DRL_MODE_CONTEXTS]; 781 RK_U16 interp_filter_cdf[SWITCHABLE_FILTER_CONTEXTS][AV1_SWITCHABLE_FILTERS - 1]; 782 783 MvCDFs mv_cdf; 784 785 RK_U16 obmc_cdf[BLOCK_SIZE_TYPES]; 786 RK_U16 motion_mode_cdf[BLOCK_SIZE_TYPES][2]; 787 788 RK_U16 inter_compound_mode_cdf[AV1_INTER_MODE_CONTEXTS][INTER_COMPOUND_MODES - 1]; 789 RK_U16 compound_type_cdf[BLOCK_SIZE_TYPES][CDF_SIZE(COMPOUND_TYPES - 1)]; 790 RK_U16 interintra_cdf[BLOCK_SIZE_GROUPS]; 791 RK_U16 interintra_mode_cdf[BLOCK_SIZE_GROUPS][INTERINTRA_MODES - 1]; 792 RK_U16 wedge_interintra_cdf[BLOCK_SIZE_TYPES]; 793 RK_U16 wedge_idx_cdf[BLOCK_SIZE_TYPES][CDF_SIZE(16)]; 794 795 RK_U16 palette_y_mode_cdf[PALETTE_BLOCK_SIZES][PALETTE_Y_MODE_CONTEXTS][1]; 796 RK_U16 palette_uv_mode_cdf[PALETTE_UV_MODE_CONTEXTS][1]; 797 RK_U16 palette_y_size_cdf[PALETTE_BLOCK_SIZES][PALETTE_SIZES - 1]; 798 RK_U16 palette_uv_size_cdf[PALETTE_BLOCK_SIZES][PALETTE_SIZES - 1]; 799 800 RK_U16 cfl_sign_cdf[CFL_JOINT_SIGNS - 1]; 801 RK_U16 cfl_alpha_cdf[CFL_ALPHA_CONTEXTS][CFL_ALPHABET_SIZE - 1]; 802 803 RK_U16 intrabc_cdf[1]; 804 RK_U16 angle_delta_cdf[DIRECTIONAL_MODES][6]; 805 806 RK_U16 filter_intra_mode_cdf[FILTER_INTRA_MODES - 1]; 807 RK_U16 filter_intra_cdf[BLOCK_SIZES_ALL]; 808 RK_U16 comp_group_idx_cdf[COMP_GROUP_IDX_CONTEXTS][CDF_SIZE(2)]; 809 RK_U16 compound_idx_cdf[COMP_INDEX_CONTEXTS][CDF_SIZE(2)]; 810 811 RK_U16 dummy0[14]; 812 813 // Palette index contexts; sizes 1/7, 2/6, 3/5 packed together 814 RK_U16 palette_y_color_index_cdf[PALETTE_IDX_CONTEXTS][8]; 815 RK_U16 palette_uv_color_index_cdf[PALETTE_IDX_CONTEXTS][8]; 816 // RK_U16 dummy1[0]; 817 818 // Note: cdf space can be optimized (most sets have fewer than EXT_TX_TYPES 819 // symbols) 820 RK_U16 tx_type_intra0_cdf[EXTTX_SIZES][AV1_INTRA_MODES][8]; 821 RK_U16 tx_type_intra1_cdf[EXTTX_SIZES][AV1_INTRA_MODES][4]; 822 RK_U16 tx_type_inter_cdf[2][EXTTX_SIZES][EXT_TX_TYPES]; 823 824 aom_cdf_prob txb_skip_cdf[TX_SIZES][TXB_SKIP_CONTEXTS][CDF_SIZE(2)]; 825 aom_cdf_prob eob_extra_cdf[TX_SIZES][PLANE_TYPES][EOB_COEF_CONTEXTS][CDF_SIZE(2)]; 826 RK_U16 dummy_[5]; 827 828 aom_cdf_prob eob_flag_cdf16[PLANE_TYPES][2][4]; 829 aom_cdf_prob eob_flag_cdf32[PLANE_TYPES][2][8]; 830 aom_cdf_prob eob_flag_cdf64[PLANE_TYPES][2][8]; 831 aom_cdf_prob eob_flag_cdf128[PLANE_TYPES][2][8]; 832 aom_cdf_prob eob_flag_cdf256[PLANE_TYPES][2][8]; 833 aom_cdf_prob eob_flag_cdf512[PLANE_TYPES][2][16]; 834 aom_cdf_prob eob_flag_cdf1024[PLANE_TYPES][2][16]; 835 aom_cdf_prob coeff_base_eob_cdf[TX_SIZES][PLANE_TYPES][SIG_COEF_CONTEXTS_EOB][CDF_SIZE(3)]; 836 aom_cdf_prob coeff_base_cdf[TX_SIZES][PLANE_TYPES][SIG_COEF_CONTEXTS][CDF_SIZE(4) + 1]; 837 aom_cdf_prob dc_sign_cdf[PLANE_TYPES][DC_SIGN_CONTEXTS][CDF_SIZE(2)]; 838 RK_U16 dummy_2[2]; 839 aom_cdf_prob coeff_br_cdf[TX_SIZES][PLANE_TYPES][LEVEL_CONTEXTS][CDF_SIZE(BR_CDF_SIZE) + 1]; 840 RK_U16 dummy2[16]; 841 } AV1CDFs; 842 843 typedef struct { 844 RK_U8 scaling_lut_y[256]; 845 RK_U8 scaling_lut_cb[256]; 846 RK_U8 scaling_lut_cr[256]; 847 RK_S16 cropped_luma_grain_block[4096]; 848 RK_S16 cropped_chroma_grain_block[1024 * 2]; 849 } AV1FilmGrainMemory; 850 851 #endif // __AV1COMMONDEC_H__ 852