1*437bfbebSnyanmisaka /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2*437bfbebSnyanmisaka /* 3*437bfbebSnyanmisaka * Copyright (c) 2016 Rockchip Electronics Co., Ltd. 4*437bfbebSnyanmisaka */ 5*437bfbebSnyanmisaka 6*437bfbebSnyanmisaka #ifndef __RC_H__ 7*437bfbebSnyanmisaka #define __RC_H__ 8*437bfbebSnyanmisaka 9*437bfbebSnyanmisaka #include "mpp_err.h" 10*437bfbebSnyanmisaka 11*437bfbebSnyanmisaka #include "mpp_rc_api.h" 12*437bfbebSnyanmisaka 13*437bfbebSnyanmisaka /* 14*437bfbebSnyanmisaka * Mpp rate control principle 15*437bfbebSnyanmisaka * 16*437bfbebSnyanmisaka * 1. Rate control information is composed by these parts: 17*437bfbebSnyanmisaka * a. configuration from mpp user. 18*437bfbebSnyanmisaka * b. frame level target bitrate calculated by different RC model. 19*437bfbebSnyanmisaka * c. block level hardware related configuration to hardware. 20*437bfbebSnyanmisaka * d. statistic information from hardware after one frame is encoded. 21*437bfbebSnyanmisaka * 22*437bfbebSnyanmisaka * 2. All the above informatioin is storaged and managed by RcDataCtx in mpp 23*437bfbebSnyanmisaka * framework. All these information is shared in encoder and hal module. 24*437bfbebSnyanmisaka * 25*437bfbebSnyanmisaka * 3. User (no matter developer or end user) defined rate control should based 26*437bfbebSnyanmisaka * on these Rate control information and implement its own rate control 27*437bfbebSnyanmisaka * strategy module by providing their own RcImplApi. 28*437bfbebSnyanmisaka */ 29*437bfbebSnyanmisaka 30*437bfbebSnyanmisaka /* 31*437bfbebSnyanmisaka * Relation between mpp_enc / enc_impl / hal / RcApi / RcImplApi / RcData 32*437bfbebSnyanmisaka * 33*437bfbebSnyanmisaka * +-----------+ 34*437bfbebSnyanmisaka * | mpp_enc | 35*437bfbebSnyanmisaka * +-----+-----+ 36*437bfbebSnyanmisaka * | 37*437bfbebSnyanmisaka * +-----+-----+ +-----------+ +-----------+ 38*437bfbebSnyanmisaka * | enc_impl +---> RcApi +---> RcImplApi | 39*437bfbebSnyanmisaka * +-----+-----+ +-----+-----+ +-----+-----+ 40*437bfbebSnyanmisaka * | \ / | | 41*437bfbebSnyanmisaka * | + | | 42*437bfbebSnyanmisaka * | / \ | | 43*437bfbebSnyanmisaka * +-----v-----+ +-----v-----+ | 44*437bfbebSnyanmisaka * | hal +---> RcData <---------+ 45*437bfbebSnyanmisaka * +-----------+ +-----------+ 46*437bfbebSnyanmisaka */ 47*437bfbebSnyanmisaka 48*437bfbebSnyanmisaka typedef void* RcCtx; 49*437bfbebSnyanmisaka 50*437bfbebSnyanmisaka #ifdef __cplusplus 51*437bfbebSnyanmisaka extern "C" { 52*437bfbebSnyanmisaka #endif 53*437bfbebSnyanmisaka 54*437bfbebSnyanmisaka MPP_RET rc_init(RcCtx *ctx, MppCodingType type, const char **request_name); 55*437bfbebSnyanmisaka MPP_RET rc_deinit(RcCtx ctx); 56*437bfbebSnyanmisaka 57*437bfbebSnyanmisaka /* update rc control */ 58*437bfbebSnyanmisaka MPP_RET rc_update_usr_cfg(RcCtx ctx, RcCfg *cfg); 59*437bfbebSnyanmisaka 60*437bfbebSnyanmisaka /* Frame rate convertion */ 61*437bfbebSnyanmisaka MPP_RET rc_frm_check_drop(RcCtx ctx, EncRcTask *task); 62*437bfbebSnyanmisaka /* Frame reenc check */ 63*437bfbebSnyanmisaka MPP_RET rc_check_reenc(RcCtx ctx, EncRcTask *task); 64*437bfbebSnyanmisaka 65*437bfbebSnyanmisaka /* Frame level rate and quality control */ 66*437bfbebSnyanmisaka MPP_RET rc_frm_start(RcCtx ctx, EncRcTask *task); 67*437bfbebSnyanmisaka MPP_RET rc_frm_end(RcCtx ctx, EncRcTask *task); 68*437bfbebSnyanmisaka 69*437bfbebSnyanmisaka MPP_RET rc_hal_start(RcCtx ctx, EncRcTask *task); 70*437bfbebSnyanmisaka MPP_RET rc_hal_end(RcCtx ctx, EncRcTask *task); 71*437bfbebSnyanmisaka 72*437bfbebSnyanmisaka #ifdef __cplusplus 73*437bfbebSnyanmisaka } 74*437bfbebSnyanmisaka #endif 75*437bfbebSnyanmisaka 76*437bfbebSnyanmisaka #endif /* __RC_H__ */ 77