xref: /rockchip-linux_mpp/mpp/codec/inc/mpp_rc.h (revision 437bfbeb9567cca9cd9080e3f6954aa9d6a94f18)
1*437bfbebSnyanmisaka /*
2*437bfbebSnyanmisaka  * Copyright 2016 Rockchip Electronics Co. LTD
3*437bfbebSnyanmisaka  *
4*437bfbebSnyanmisaka  * Licensed under the Apache License, Version 2.0 (the "License");
5*437bfbebSnyanmisaka  * you may not use this file except in compliance with the License.
6*437bfbebSnyanmisaka  * You may obtain a copy of the License at
7*437bfbebSnyanmisaka  *
8*437bfbebSnyanmisaka  *      http://www.apache.org/licenses/LICENSE-2.0
9*437bfbebSnyanmisaka  *
10*437bfbebSnyanmisaka  * Unless required by applicable law or agreed to in writing, software
11*437bfbebSnyanmisaka  * distributed under the License is distributed on an "AS IS" BASIS,
12*437bfbebSnyanmisaka  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13*437bfbebSnyanmisaka  * See the License for the specific language governing permissions and
14*437bfbebSnyanmisaka  * limitations under the License.
15*437bfbebSnyanmisaka  */
16*437bfbebSnyanmisaka 
17*437bfbebSnyanmisaka #ifndef __MPP_RC__
18*437bfbebSnyanmisaka #define __MPP_RC__
19*437bfbebSnyanmisaka 
20*437bfbebSnyanmisaka #include "rk_venc_cmd.h"
21*437bfbebSnyanmisaka 
22*437bfbebSnyanmisaka #include "mpp_list.h"
23*437bfbebSnyanmisaka 
24*437bfbebSnyanmisaka /*
25*437bfbebSnyanmisaka  * mpp rate control contain common caculation methd
26*437bfbebSnyanmisaka  *
27*437bfbebSnyanmisaka  * 1. MppData - data statistic struct
28*437bfbebSnyanmisaka  *    size - max valid data number
29*437bfbebSnyanmisaka  *    len  - valid data number
30*437bfbebSnyanmisaka  *    pos  - current load/store position
31*437bfbebSnyanmisaka  *    val  - buffer array pointer
32*437bfbebSnyanmisaka  */
33*437bfbebSnyanmisaka typedef struct {
34*437bfbebSnyanmisaka     RK_S32  size;
35*437bfbebSnyanmisaka     RK_S32  len;
36*437bfbebSnyanmisaka     RK_S32  pos;
37*437bfbebSnyanmisaka     RK_S32  *val;
38*437bfbebSnyanmisaka } MppData;
39*437bfbebSnyanmisaka 
40*437bfbebSnyanmisaka /*
41*437bfbebSnyanmisaka  * 2. Proportion Integration Differentiation (PID) control
42*437bfbebSnyanmisaka  */
43*437bfbebSnyanmisaka typedef struct {
44*437bfbebSnyanmisaka     RK_S32  p;
45*437bfbebSnyanmisaka     RK_S32  i;
46*437bfbebSnyanmisaka     RK_S32  d;
47*437bfbebSnyanmisaka     RK_S32  coef_p;
48*437bfbebSnyanmisaka     RK_S32  coef_i;
49*437bfbebSnyanmisaka     RK_S32  coef_d;
50*437bfbebSnyanmisaka     RK_S32  div;
51*437bfbebSnyanmisaka     RK_S32  len;
52*437bfbebSnyanmisaka     RK_S32  count;
53*437bfbebSnyanmisaka } MppPIDCtx;
54*437bfbebSnyanmisaka 
55*437bfbebSnyanmisaka /*
56*437bfbebSnyanmisaka  * MppRateControl has three steps work:
57*437bfbebSnyanmisaka  *
58*437bfbebSnyanmisaka  * 1. translate user requirement to bit rate parameters
59*437bfbebSnyanmisaka  * 2. calculate target bit from bit parameters
60*437bfbebSnyanmisaka  * 3. calculate qstep from target bit
61*437bfbebSnyanmisaka  *
62*437bfbebSnyanmisaka  * That is user setting -> target bit -> qstep.
63*437bfbebSnyanmisaka  *
64*437bfbebSnyanmisaka  * This struct will be used in both controller and hal.
65*437bfbebSnyanmisaka  * EncImpl provide step 1 and step 2. Hal provide step 3.
66*437bfbebSnyanmisaka  *
67*437bfbebSnyanmisaka  */
68*437bfbebSnyanmisaka typedef enum MppEncGopMode_e {
69*437bfbebSnyanmisaka     /* gop == 0 */
70*437bfbebSnyanmisaka     MPP_GOP_ALL_INTER,
71*437bfbebSnyanmisaka     /* gop == 1 */
72*437bfbebSnyanmisaka     MPP_GOP_ALL_INTRA,
73*437bfbebSnyanmisaka     /* gop < fps */
74*437bfbebSnyanmisaka     MPP_GOP_SMALL,
75*437bfbebSnyanmisaka     /* gop >= fps */
76*437bfbebSnyanmisaka     MPP_GOP_LARGE,
77*437bfbebSnyanmisaka     MPP_GOP_MODE_BUTT,
78*437bfbebSnyanmisaka } MppEncGopMode;
79*437bfbebSnyanmisaka 
80*437bfbebSnyanmisaka typedef enum RC_PARAM_OPS {
81*437bfbebSnyanmisaka     RC_RECORD_REAL_BITS,
82*437bfbebSnyanmisaka     RC_RECORD_QP_SUM,
83*437bfbebSnyanmisaka     RC_RECORD_QP_MIN,
84*437bfbebSnyanmisaka     RC_RECORD_QP_MAX,
85*437bfbebSnyanmisaka     RC_RECORD_SET_QP,
86*437bfbebSnyanmisaka     RC_RECORD_REAL_QP,
87*437bfbebSnyanmisaka     RC_RECORD_SSE_SUM,
88*437bfbebSnyanmisaka     RC_RECORD_WIN_LEN
89*437bfbebSnyanmisaka } RC_PARAM_OPS;
90*437bfbebSnyanmisaka 
91*437bfbebSnyanmisaka typedef struct RecordNode_t {
92*437bfbebSnyanmisaka     struct list_head list;
93*437bfbebSnyanmisaka     /* @frm_cnt starts from ONE */
94*437bfbebSnyanmisaka     RK_U32           frm_cnt;
95*437bfbebSnyanmisaka     RK_U32           bps;
96*437bfbebSnyanmisaka     RK_U32           fps;
97*437bfbebSnyanmisaka     RK_S32           gop;
98*437bfbebSnyanmisaka     RK_S32           bits_per_pic;
99*437bfbebSnyanmisaka     RK_S32           bits_per_intra;
100*437bfbebSnyanmisaka     RK_S32           bits_per_inter;
101*437bfbebSnyanmisaka     RK_U32           tgt_bits;
102*437bfbebSnyanmisaka     RK_U32           bit_min;
103*437bfbebSnyanmisaka     RK_U32           bit_max;
104*437bfbebSnyanmisaka     RK_U32           real_bits;
105*437bfbebSnyanmisaka     RK_S32           acc_intra_bits_in_fps;
106*437bfbebSnyanmisaka     RK_S32           acc_inter_bits_in_fps;
107*437bfbebSnyanmisaka     RK_S32           last_fps_bits;
108*437bfbebSnyanmisaka     float            last_intra_percent;
109*437bfbebSnyanmisaka 
110*437bfbebSnyanmisaka     /* hardware result */
111*437bfbebSnyanmisaka     RK_S32           qp_sum;
112*437bfbebSnyanmisaka     RK_S64           sse_sum;
113*437bfbebSnyanmisaka     RK_S32           set_qp;
114*437bfbebSnyanmisaka     RK_S32           qp_min;
115*437bfbebSnyanmisaka     RK_S32           qp_max;
116*437bfbebSnyanmisaka     RK_S32           real_qp;
117*437bfbebSnyanmisaka     RK_S32           wlen;
118*437bfbebSnyanmisaka } RecordNode;
119*437bfbebSnyanmisaka 
120*437bfbebSnyanmisaka #ifdef __cplusplus
121*437bfbebSnyanmisaka extern "C" {
122*437bfbebSnyanmisaka #endif
123*437bfbebSnyanmisaka 
124*437bfbebSnyanmisaka MPP_RET mpp_data_init(MppData **p, RK_S32 len);
125*437bfbebSnyanmisaka void mpp_data_deinit(MppData *p);
126*437bfbebSnyanmisaka void mpp_data_update(MppData *p, RK_S32 val);
127*437bfbebSnyanmisaka RK_S32 mpp_data_avg(MppData *p, RK_S32 len, RK_S32 num, RK_S32 denom);
128*437bfbebSnyanmisaka 
129*437bfbebSnyanmisaka void mpp_pid_reset(MppPIDCtx *p);
130*437bfbebSnyanmisaka void mpp_pid_set_param(MppPIDCtx *p, RK_S32 coef_p, RK_S32 coef_i, RK_S32 coef_d, RK_S32 div, RK_S32 len);
131*437bfbebSnyanmisaka void mpp_pid_update(MppPIDCtx *p, RK_S32 val, RK_S32 is_reset);
132*437bfbebSnyanmisaka RK_S32 mpp_pid_calc(MppPIDCtx *ctx);
133*437bfbebSnyanmisaka 
134*437bfbebSnyanmisaka #ifdef __cplusplus
135*437bfbebSnyanmisaka }
136*437bfbebSnyanmisaka #endif
137*437bfbebSnyanmisaka 
138*437bfbebSnyanmisaka #endif /* __MPP_RC__ */
139