xref: /rockchip-linux_mpp/mpp/codec/enc/h265/h265e_codec.h (revision 437bfbeb9567cca9cd9080e3f6954aa9d6a94f18)
1*437bfbebSnyanmisaka /*
2*437bfbebSnyanmisaka  * Copyright 2015 Rockchip Electronics Co. LTD
3*437bfbebSnyanmisaka  *
4*437bfbebSnyanmisaka  * Licensed under the Apache License, Version 2.0 (the "License");
5*437bfbebSnyanmisaka  * you may not use this file except in compliance with the License.
6*437bfbebSnyanmisaka  * You may obtain a copy of the License at
7*437bfbebSnyanmisaka  *
8*437bfbebSnyanmisaka  *      http://www.apache.org/licenses/LICENSE-2.0
9*437bfbebSnyanmisaka  *
10*437bfbebSnyanmisaka  * Unless required by applicable law or agreed to in writing, software
11*437bfbebSnyanmisaka  * distributed under the License is distributed on an "AS IS" BASIS,
12*437bfbebSnyanmisaka  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13*437bfbebSnyanmisaka  * See the License for the specific language governing permissions and
14*437bfbebSnyanmisaka  * limitations under the License.
15*437bfbebSnyanmisaka  */
16*437bfbebSnyanmisaka #ifndef __H265E_CODEC_H__
17*437bfbebSnyanmisaka #define __H265E_CODEC_H__
18*437bfbebSnyanmisaka 
19*437bfbebSnyanmisaka #include "mpp_debug.h"
20*437bfbebSnyanmisaka 
21*437bfbebSnyanmisaka #include "mpp_common.h"
22*437bfbebSnyanmisaka #include "mpp_rc.h"
23*437bfbebSnyanmisaka 
24*437bfbebSnyanmisaka #include "h265e_syntax.h"
25*437bfbebSnyanmisaka #include "h265e_syntax_new.h"
26*437bfbebSnyanmisaka #include "h265e_dpb.h"
27*437bfbebSnyanmisaka #include "enc_impl_api.h"
28*437bfbebSnyanmisaka 
29*437bfbebSnyanmisaka #define H265E_DBG_FUNCTION          (0x00000001)
30*437bfbebSnyanmisaka #define H265E_DBG_INPUT             (0x00000010)
31*437bfbebSnyanmisaka #define H265E_DBG_OUTPUT            (0x00000020)
32*437bfbebSnyanmisaka #define H265E_DBG_PS                (0x00000040)
33*437bfbebSnyanmisaka #define H265E_DBG_DPB               (0x00000080)
34*437bfbebSnyanmisaka #define H265E_DBG_DPB_REF           (0x000000c0)
35*437bfbebSnyanmisaka 
36*437bfbebSnyanmisaka 
37*437bfbebSnyanmisaka #define H265E_DBG_SLICE             (0x00000100)
38*437bfbebSnyanmisaka #define H265E_DBG_HEADER            (0x00000200)
39*437bfbebSnyanmisaka #define H265E_DBG_API               (0x00000400)
40*437bfbebSnyanmisaka #define H265E_DBG_SKIP              (0x00000800)
41*437bfbebSnyanmisaka 
42*437bfbebSnyanmisaka 
43*437bfbebSnyanmisaka #define H265E_PS_BUF_SIZE           512
44*437bfbebSnyanmisaka #define H265E_SEI_BUF_SIZE          1024
45*437bfbebSnyanmisaka #define H265E_EXTRA_INFO_BUF_SIZE   (H265E_PS_BUF_SIZE + H265E_SEI_BUF_SIZE)
46*437bfbebSnyanmisaka 
47*437bfbebSnyanmisaka extern RK_U32 h265e_debug;
48*437bfbebSnyanmisaka 
49*437bfbebSnyanmisaka #define h265e_dbg(flag, fmt, ...)   _mpp_dbg(h265e_debug, flag, fmt, ## __VA_ARGS__)
50*437bfbebSnyanmisaka #define h265e_dbg_f(flag, fmt, ...) _mpp_dbg_f(h265e_debug, flag, fmt, ## __VA_ARGS__)
51*437bfbebSnyanmisaka 
52*437bfbebSnyanmisaka #define h265e_dbg_func(fmt, ...)    h265e_dbg_f(H265E_DBG_FUNCTION, fmt, ## __VA_ARGS__)
53*437bfbebSnyanmisaka #define h265e_dbg_input(fmt, ...)   h265e_dbg(H265E_DBG_INPUT, fmt, ## __VA_ARGS__)
54*437bfbebSnyanmisaka #define h265e_dbg_output(fmt, ...)  h265e_dbg(H265E_DBG_OUTPUT, fmt, ## __VA_ARGS__)
55*437bfbebSnyanmisaka 
56*437bfbebSnyanmisaka #define h265e_dbg_ps(fmt, ...)      h265e_dbg(H265E_DBG_PS, fmt, ## __VA_ARGS__)
57*437bfbebSnyanmisaka #define h265e_dbg_dpb(fmt, ...)     h265e_dbg(H265E_DBG_DPB, fmt, ## __VA_ARGS__)
58*437bfbebSnyanmisaka #define h265e_dbg_slice(fmt, ...)   h265e_dbg(H265E_DBG_SLICE, fmt, ## __VA_ARGS__)
59*437bfbebSnyanmisaka #define h265e_dbg_skip(fmt, ...)   h265e_dbg(H265E_DBG_SKIP, fmt, ## __VA_ARGS__)
60*437bfbebSnyanmisaka 
61*437bfbebSnyanmisaka #define h265e_dbg_dpb_ref(fmt, ...)  h265e_dbg(H265E_DBG_DPB_REF, fmt, ## __VA_ARGS__)
62*437bfbebSnyanmisaka 
63*437bfbebSnyanmisaka typedef struct H265eCtx_t {
64*437bfbebSnyanmisaka     MppEncCfgSet        *cfg;
65*437bfbebSnyanmisaka     RK_U32              rc_ready;
66*437bfbebSnyanmisaka     RK_S32              idr_request;
67*437bfbebSnyanmisaka 
68*437bfbebSnyanmisaka     H265eVps            vps;
69*437bfbebSnyanmisaka     H265eSps            sps;
70*437bfbebSnyanmisaka     H265ePps            pps;
71*437bfbebSnyanmisaka     H265eSlice          *slice;
72*437bfbebSnyanmisaka     H265eDpb            *dpb;
73*437bfbebSnyanmisaka     RK_U32              plt_flag;
74*437bfbebSnyanmisaka 
75*437bfbebSnyanmisaka     void                *extra_info;
76*437bfbebSnyanmisaka     H265eSyntax_new     syntax;
77*437bfbebSnyanmisaka     H265eFeedback       feedback;
78*437bfbebSnyanmisaka     struct list_head    rc_list;
79*437bfbebSnyanmisaka } H265eCtx;
80*437bfbebSnyanmisaka 
81*437bfbebSnyanmisaka #endif
82