1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2 /*
3 * Copyright (c) 2024 Rockchip Electronics Co., Ltd.
4 */
5
6 #define MODULE_TAG "mpp_sys_cfg_test"
7
8 #include "mpp_log.h"
9 #include "mpp_mem.h"
10 #include "mpp_time.h"
11 #include "mpp_common.h"
12
13 #include "rk_mpp_cfg.h"
14 #include "mpp_sys_cfg.h"
15
main()16 int main()
17 {
18 MPP_RET ret = MPP_OK;
19 MppSysCfg cfg;
20 RK_S64 end = 0;
21 RK_S64 start = 0;
22 MppCodingType type = MPP_VIDEO_CodingHEVC;
23 RK_U32 width = 4096;
24 RK_U32 height = 2304;
25 RK_U32 h_stride_by_byte;
26 RK_U32 h_stride_by_pixel;
27 RK_U32 v_stride;
28 RK_U32 size_total;
29 RK_U32 size_fbc_hdr;
30 RK_U32 size_fbc_bdy;
31
32 mpp_sys_cfg_show();
33
34 mpp_log("mpp_sys_cfg_test start\n");
35
36 start = mpp_time();
37
38 ret = mpp_sys_cfg_get(&cfg);
39 if (ret) {
40 mpp_err("mpp_sys_cfg_get failed\n");
41 goto DONE;
42 }
43
44 /* set correct parameter */
45 ret = mpp_sys_cfg_set_u32(cfg, "dec_buf_chk:type", 1);
46 ret = mpp_sys_cfg_set_u32(cfg, "dec_buf_chk:enable", 1);
47 ret = mpp_sys_cfg_set_u32(cfg, "dec_buf_chk:type", type);
48 ret = mpp_sys_cfg_set_u32(cfg, "dec_buf_chk:fmt_codec", MPP_FMT_YUV420SP);
49 ret = mpp_sys_cfg_set_u32(cfg, "dec_buf_chk:fmt_fbc", MPP_FRAME_FBC_AFBC_V1);
50 ret = mpp_sys_cfg_set_u32(cfg, "dec_buf_chk:width", width);
51 ret = mpp_sys_cfg_set_u32(cfg, "dec_buf_chk:height", height);
52 ret = mpp_sys_cfg_set_u32(cfg, "dec_buf_chk:h_stride_by_byte", 0);
53 ret = mpp_sys_cfg_set_u32(cfg, "dec_buf_chk:h_stride_by_pixel", 0);
54
55 /* try get readonly parameter */
56 ret = mpp_sys_cfg_set_u32(cfg, "dec_buf_chk:cap_fbc", 1);
57 if (!ret) {
58 mpp_log("set readonly success, should be a failure\n");
59 goto DONE;
60 }
61
62 /* get result */
63 mpp_sys_cfg_ioctl(cfg);
64
65 ret = mpp_sys_cfg_get_u32(cfg, "dec_buf_chk:h_stride_by_byte", &h_stride_by_byte);
66 ret = mpp_sys_cfg_get_u32(cfg, "dec_buf_chk:h_stride_by_pixel", &h_stride_by_pixel);
67 ret = mpp_sys_cfg_get_u32(cfg, "dec_buf_chk:v_stride", &v_stride);
68 ret = mpp_sys_cfg_get_u32(cfg, "dec_buf_chk:size_total", &size_total);
69 ret = mpp_sys_cfg_get_u32(cfg, "dec_buf_chk:size_fbc_hdr", &size_fbc_hdr);
70 ret = mpp_sys_cfg_get_u32(cfg, "dec_buf_chk:size_fbc_bdy", &size_fbc_bdy);
71
72 ret = mpp_sys_cfg_put(cfg);
73 if (ret) {
74 mpp_err("mpp_sys_cfg_put failed\n");
75 goto DONE;
76 }
77
78 end = mpp_time();
79 mpp_log("set u32 time %lld us\n", end - start);
80
81 DONE:
82 mpp_log("mpp_sys_cfg_test done %s\n", ret ? "failed" : "success");
83 return ret;
84 }
85