1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2 /* 3 * Copyright (c) 2015 Rockchip Electronics Co., Ltd. 4 */ 5 6 #ifndef __RK_VENC_CMD_H__ 7 #define __RK_VENC_CMD_H__ 8 9 #include "mpp_frame.h" 10 #include "rk_venc_rc.h" 11 12 /* 13 * Configure of encoder is very complicated. So we divide configures into 14 * four parts: 15 * 16 * 1. Rate control parameter 17 * This is quality and bitrate request from user. 18 * 19 * 2. Data source MppFrame parameter 20 * This is data source buffer information. 21 * Now it is PreP config 22 * PreP : Encoder Preprocess configuration 23 * 24 * 3. Video codec infomation 25 * This is user custormized stream information. 26 * including: 27 * H.264 / H.265 / vp8 / mjpeg 28 * 29 * 4. Misc parameter 30 * including: 31 * Split : Slice split configuration 32 * GopRef: Reference gop configuration 33 * ROI : Region Of Interest 34 * OSD : On Screen Display 35 * MD : Motion Detection 36 * 37 * The module transcation flow is as follows: 38 * 39 * + + 40 * User | Mpi/Mpp | EncImpl 41 * | | Hal 42 * | | 43 * +----------+ | +---------+ | +-----------+ 44 * | | | | +-----RcCfg-----> | 45 * | RcCfg +---------> | | | EncImpl | 46 * | | | | | +-Frame-----> | 47 * +----------+ | | | | | +--+-----^--+ 48 * | | | | | | | 49 * | | | | | | | 50 * +----------+ | | | | | syntax | 51 * | | | | | | | | | 52 * | MppFrame +---------> MppEnc +---+ | | result 53 * | | | | | | | | | 54 * +----------+ | | | | | | | 55 * | | | | | +--v-----+--+ 56 * | | | +-Frame-----> | 57 * +----------+ | | | | | | 58 * | | | | +---CodecCfg----> Hal | 59 * | CodecCfg +---------> | | | | 60 * | | | | <-----Extra-----> | 61 * +----------+ | +---------+ | +-----------+ 62 * | | 63 * | | 64 * + + 65 * 66 * The function call flow is shown below: 67 * 68 * mpi mpp_enc controller hal 69 * + + + + 70 * | | | | 71 * | | | | 72 * +----------init------------> | | 73 * | | | | 74 * | | | | 75 * | PrepCfg | | | 76 * +---------control----------> PrepCfg | | 77 * | +-----control-----> | 78 * | | | PrepCfg | 79 * | +--------------------------control--------> 80 * | | | allocate 81 * | | | buffer 82 * | | | | 83 * | RcCfg | | | 84 * +---------control----------> RcCfg | | 85 * | +-----control-----> | 86 * | | rc_init | 87 * | | | | 88 * | | | | 89 * | CodecCfg | | | 90 * +---------control----------> | CodecCfg | 91 * | +--------------------------control--------> 92 * | | | generate 93 * | | | sps/pps 94 * | | | Get extra info | 95 * | +--------------------------control--------> 96 * | Get extra info | | | 97 * +---------control----------> | | 98 * | | | | 99 * | | | | 100 * | ROICfg | | | 101 * +---------control----------> | ROICfg | 102 * | +--------------------------control--------> 103 * | | | | 104 * | OSDCfg | | | 105 * +---------control----------> | OSDCfg | 106 * | +--------------------------control--------> 107 * | | | | 108 * | MDCfg | | | 109 * +---------control----------> | MDCfg | 110 * | +--------------------------control--------> 111 * | | | | 112 * | Set extra info | | | 113 * +---------control----------> | Set extra info | 114 * | +--------------------------control--------> 115 * | | | | 116 * | task | | | 117 * +----------encode----------> task | | 118 * | +-----encode------> | 119 * | | encode | 120 * | | | syntax | 121 * | +--------------------------gen_reg--------> 122 * | | | | 123 * | | | | 124 * | +---------------------------start---------> 125 * | | | | 126 * | | | | 127 * | +---------------------------wait----------> 128 * | | | | 129 * | | callback | | 130 * | +-----------------> | 131 * +--OSD-MD--encode----------> | | 132 * | . | | | 133 * | . | | | 134 * | . | | | 135 * +--OSD-MD--encode----------> | | 136 * | | | | 137 * +----------deinit----------> | | 138 * + + + + 139 */ 140 141 /* 142 * encoder query interface is only for debug usage 143 */ 144 #define MPP_ENC_QUERY_STATUS (0x00000001) 145 #define MPP_ENC_QUERY_WAIT (0x00000002) 146 #define MPP_ENC_QUERY_FPS (0x00000004) 147 #define MPP_ENC_QUERY_BPS (0x00000008) 148 #define MPP_ENC_QUERY_ENC_IN_FRM (0x00000010) 149 #define MPP_ENC_QUERY_ENC_WORK (0x00000020) 150 #define MPP_ENC_QUERY_ENC_OUT_PKT (0x00000040) 151 152 #define MPP_ENC_QUERY_ALL (MPP_ENC_QUERY_STATUS | \ 153 MPP_ENC_QUERY_WAIT | \ 154 MPP_ENC_QUERY_FPS | \ 155 MPP_ENC_QUERY_BPS | \ 156 MPP_ENC_QUERY_ENC_IN_FRM | \ 157 MPP_ENC_QUERY_ENC_WORK | \ 158 MPP_ENC_QUERY_ENC_OUT_PKT) 159 160 typedef struct MppEncQueryCfg_t { 161 /* 162 * 32 bit query flag for query data check 163 * Each bit represent a query data switch. 164 * bit 0 - for querying encoder runtime status 165 * bit 1 - for querying encoder runtime waiting status 166 * bit 2 - for querying encoder realtime encode fps 167 * bit 3 - for querying encoder realtime output bps 168 * bit 4 - for querying encoder input frame count 169 * bit 5 - for querying encoder start hardware times 170 * bit 6 - for querying encoder output packet count 171 */ 172 RK_U32 query_flag; 173 174 /* 64 bit query data output */ 175 RK_U32 rt_status; 176 RK_U32 rt_wait; 177 RK_U32 rt_fps; 178 RK_U32 rt_bps; 179 RK_U32 enc_in_frm_cnt; 180 RK_U32 enc_hw_run_cnt; 181 RK_U32 enc_out_pkt_cnt; 182 } MppEncQueryCfg; 183 184 /* 185 * base working mode parameter 186 */ 187 typedef struct MppEncBaseCfg_t { 188 MppCodingType coding; 189 RK_S32 low_delay; 190 RK_S32 smart_en; 191 RK_S32 smt1_en; 192 RK_S32 smt3_en; 193 } MppEncBaseCfg; 194 195 /* 196 * Rate control parameter 197 */ 198 typedef enum MppEncRcQuality_e { 199 MPP_ENC_RC_QUALITY_WORST, 200 MPP_ENC_RC_QUALITY_WORSE, 201 MPP_ENC_RC_QUALITY_MEDIUM, 202 MPP_ENC_RC_QUALITY_BETTER, 203 MPP_ENC_RC_QUALITY_BEST, 204 MPP_ENC_RC_QUALITY_CQP, 205 MPP_ENC_RC_QUALITY_AQ_ONLY, 206 MPP_ENC_RC_QUALITY_BUTT 207 } MppEncRcQuality; 208 209 typedef struct MppEncRcCfg_t { 210 /* 211 * rc_mode - rate control mode 212 * 213 * mpp provide two rate control mode: 214 * 215 * Constant Bit Rate (CBR) mode 216 * - paramter 'bps*' define target bps 217 * - paramter quality and qp will not take effect 218 * 219 * Variable Bit Rate (VBR) mode 220 * - paramter 'quality' define 5 quality levels 221 * - paramter 'bps*' is used as reference but not strict condition 222 * - special Constant QP (CQP) mode is under VBR mode 223 * CQP mode will work with qp in CodecCfg. But only use for test 224 * 225 * default: CBR 226 */ 227 MppEncRcMode rc_mode; 228 229 /* 230 * quality - quality parameter, only takes effect in VBR mode 231 * 232 * Mpp does not give the direct parameter in different protocol. 233 * 234 * Mpp provide total 5 quality level: 235 * Worst - worse - Medium - better - best 236 * 237 * extra CQP level means special constant-qp (CQP) mode 238 * 239 * default value: Medium 240 */ 241 MppEncRcQuality quality; 242 243 /* 244 * bit rate parameters 245 * mpp gives three bit rate control parameter for control 246 * bps_target - target bit rate, unit: bit per second 247 * bps_max - maximun bit rate, unit: bit per second 248 * bps_min - minimun bit rate, unit: bit per second 249 * if user need constant bit rate set parameters to the similar value 250 * if user need variable bit rate set parameters as they need 251 */ 252 RK_S32 bps_target; 253 RK_S32 bps_max; 254 RK_S32 bps_min; 255 256 /* 257 * frame rate parameters have great effect on rate control 258 * 259 * fps_in_flex 260 * 0 - fix input frame rate 261 * 1 - variable input frame rate 262 * 263 * fps_in_num 264 * input frame rate numerator, if 0 then default 30 265 * 266 * fps_in_denom 267 * input frame rate denominator, if 0 then default 1 268 * 269 * fps_out_flex 270 * 0 - fix output frame rate 271 * 1 - variable output frame rate 272 * 273 * fps_out_num 274 * output frame rate numerator, if 0 then default 30 275 * 276 * fps_out_denom 277 * output frame rate denominator, if 0 then default 1 278 */ 279 RK_S32 fps_in_flex; 280 RK_S32 fps_in_num; 281 RK_S32 fps_in_denom; 282 RK_S32 fps_out_flex; 283 RK_S32 fps_out_num; 284 RK_S32 fps_out_denom; 285 /* 286 * Whether to encoder IDR when fps_out is changed. 287 * 0 -- default value, SPS, PPS headers and IDR will be added. 288 * 1 -- only SPS, PPS headers is added. 289 */ 290 RK_S32 fps_chg_no_idr; 291 292 /* 293 * gop - group of picture, gap between Intra frame 294 * 0 for only 1 I frame the rest are all P frames 295 * 1 for all I frame 296 * 2 for I P I P I P 297 * 3 for I P P I P P 298 * etc... 299 */ 300 RK_S32 gop; 301 /* internal gop mode: 0 - normal P; 1 - smart P */ 302 RK_S32 gop_mode; 303 void *ref_cfg; 304 305 /* 306 * skip_cnt - max continuous frame skip count 307 * 0 - frame skip is not allow 308 */ 309 RK_S32 skip_cnt; 310 311 /* 312 * max_reenc_times - max reencode time for one frame 313 * 0 - reencode is not allowed 314 * 1~3 max reencode time is limited to 3 315 */ 316 RK_U32 max_reenc_times; 317 318 /* 319 * stats_time - the time of bitrate statistics 320 */ 321 RK_S32 stats_time; 322 323 /* 324 * drop frame parameters 325 * used on bitrate is far over the max bitrate 326 * 327 * drop_mode 328 * 329 * MPP_ENC_RC_DROP_FRM_DISABLED 330 * - do not drop frame when bitrate overflow. 331 * MPP_ENC_RC_DROP_FRM_NORMAL 332 * - do not encode the dropped frame when bitrate overflow. 333 * MPP_ENC_RC_DROP_FRM_PSKIP 334 * - encode a all skip frame when bitrate overflow. 335 * 336 * drop_threshold 337 * 338 * The percentage threshold over max_bitrate for trigger frame drop. 339 * 340 * drop_gap 341 * The max continuous frame drop number 342 */ 343 MppEncRcDropFrmMode drop_mode; 344 RK_U32 drop_threshold; 345 RK_U32 drop_gap; 346 347 MppEncRcSuperFrameMode super_mode; 348 RK_U32 super_i_thd; 349 RK_U32 super_p_thd; 350 351 MppEncRcPriority rc_priority; 352 353 RK_U32 debreath_en; 354 RK_U32 debre_strength; 355 RK_S32 max_i_prop; 356 RK_S32 min_i_prop; 357 RK_S32 init_ip_ratio; 358 359 /* general qp control */ 360 RK_S32 qp_init; 361 RK_S32 qp_max; 362 RK_S32 qp_max_i; 363 RK_S32 qp_min; 364 RK_S32 qp_min_i; 365 RK_S32 qp_max_step; /* delta qp between each two P frame */ 366 RK_S32 qp_delta_ip; /* delta qp between I and P */ 367 RK_S32 qp_delta_vi; /* delta qp between vi and P */ 368 RK_S32 fqp_min_i; 369 RK_S32 fqp_min_p; 370 RK_S32 fqp_max_i; 371 RK_S32 fqp_max_p; 372 RK_S32 mt_st_swth_frm_qp; 373 374 RK_S32 hier_qp_en; 375 RK_S32 hier_qp_delta[4]; 376 RK_S32 hier_frame_num[4]; 377 378 RK_U32 refresh_en; 379 MppEncRcRefreshMode refresh_mode; 380 RK_U32 refresh_num; 381 RK_S32 refresh_length; 382 RK_S32 inst_br_lvl; 383 } MppEncRcCfg; 384 385 /* 386 * Hardware related rate control config 387 * 388 * This config will open some detail feature to external user to control 389 * hardware behavior directly. 390 */ 391 typedef struct MppEncHwCfg_t { 392 /* vepu541/vepu540 */ 393 RK_S32 qp_delta_row; /* delta qp between two row in P frame */ 394 RK_S32 qp_delta_row_i; /* delta qp between two row in I frame */ 395 RK_S32 qbias_i; 396 RK_S32 qbias_p; 397 RK_S32 qbias_en; 398 RK_S32 flt_str_i; 399 RK_S32 flt_str_p; 400 RK_U32 aq_thrd_i[16]; 401 RK_U32 aq_thrd_p[16]; 402 RK_S32 aq_step_i[16]; 403 RK_S32 aq_step_p[16]; 404 405 /* vepu1/2 */ 406 RK_S32 mb_rc_disable; 407 408 /* vepu580 */ 409 RK_S32 extra_buf; 410 411 /* 412 * block mode decision bias config 413 * 0 - intra32x32 414 * 1 - intra16x16 415 * 2 - intra8x8 416 * 3 - intra4x4 417 * 4 - inter64x64 418 * 5 - inter32x32 419 * 6 - inter16x16 420 * 7 - inter8x8 421 * value range 0 ~ 15, default : 8 422 * If the value is smaller then encoder will be more likely to encode corresponding block mode. 423 */ 424 RK_S32 mode_bias[8]; 425 426 /* 427 * skip mode bias config 428 * skip_bias_en - enable flag for skip bias config 429 * skip_sad - sad threshold for skip / non-skip 430 * skip_bias - tendency for skip, value range 0 ~ 15, default : 8 431 * If the value is smaller then encoder will be more likely to encode skip block. 432 */ 433 RK_S32 skip_bias_en; 434 RK_S32 skip_sad; 435 RK_S32 skip_bias; 436 437 /* vepu500 438 * 0-2: I frame thd; 3-6: I frame bias 439 * 7-9: P frame thd; 10-13: I block bias of P frame 440 * 14-17: P block bias of P frame 441 */ 442 RK_S32 qbias_arr[18]; 443 /* vepu500 444 * 0: aq16_range; 1: aq32_range; 2: aq8_range 445 * 3: aq16_diff0; 4: aq16_diff1 446 * 0 ~ 4 for I frame, 5 ~ 9 for P frame 447 */ 448 RK_S32 aq_rnge_arr[10]; 449 } MppEncHwCfg; 450 451 /* 452 * Mpp preprocess parameter 453 */ 454 /* 455 * Preprocess sharpen parameter 456 * 457 * 5x5 sharpen core 458 * 459 * enable_y - enable luma sharpen 460 * enable_uv - enable chroma sharpen 461 */ 462 typedef struct { 463 RK_U32 enable_y; 464 RK_U32 enable_uv; 465 RK_S32 coef[5]; 466 RK_S32 div; 467 RK_S32 threshold; 468 } MppEncPrepSharpenCfg; 469 470 /* 471 * input frame rotation parameter 472 * 0 - disable rotation 473 * 1 - 90 degree 474 * 2 - 180 degree 475 * 3 - 270 degree 476 */ 477 typedef enum MppEncRotationCfg_e { 478 MPP_ENC_ROT_0, 479 MPP_ENC_ROT_90, 480 MPP_ENC_ROT_180, 481 MPP_ENC_ROT_270, 482 MPP_ENC_ROT_BUTT 483 } MppEncRotationCfg; 484 485 typedef struct MppEncPrepCfg_t { 486 /* 487 * Mpp encoder input data dimension config 488 * 489 * width / height / hor_stride / ver_stride / format 490 * These information will be used for buffer allocation and rc config init 491 * The output format is always YUV420. So if input is RGB then color 492 * conversion will be done internally 493 */ 494 /* width / height set - user set value */ 495 RK_S32 width_set; 496 RK_S32 height_set; 497 /* width / height - final value in bitstream */ 498 RK_S32 width; 499 RK_S32 height; 500 RK_S32 hor_stride; 501 RK_S32 ver_stride; 502 RK_S32 max_width; 503 RK_S32 max_height; 504 505 /* resolution change flag */ 506 RK_S32 change_res; 507 508 /* 509 * Mpp encoder input/output color config 510 */ 511 MppFrameFormat format; 512 MppFrameColorSpace color; 513 MppFrameColorPrimaries colorprim; 514 MppFrameColorTransferCharacteristic colortrc; 515 MppFrameColorRange range; 516 MppFrameChromaFormat format_out; 517 MppFrameChromaDownSampleMode chroma_ds_mode; 518 MppFrameColorRange range_out; 519 RK_S32 fix_chroma_en; 520 RK_S32 fix_chroma_u; 521 RK_S32 fix_chroma_v; 522 523 /* suffix ext means the user set config externally */ 524 MppEncRotationCfg rotation; 525 MppEncRotationCfg rotation_ext; 526 527 /* 528 * input frame mirroring parameter 529 * 0 - disable mirroring 530 * 1 - horizontal mirroring 531 */ 532 RK_S32 mirroring; 533 RK_S32 mirroring_ext; 534 535 /* 536 * input frame flip parameter 537 * 0 - disable flip 538 * 1 - flip, vertical mirror transformation 539 */ 540 RK_S32 flip; 541 542 /* 543 * TODO: 544 */ 545 RK_S32 denoise; 546 547 MppEncPrepSharpenCfg sharpen; 548 } MppEncPrepCfg; 549 550 /* 551 * Mpp Motion Detection parameter 552 * 553 * Mpp can output Motion Detection infomation for each frame. 554 * If user euqueue a encode task with KEY_MOTION_INFO by following function 555 * then encoder will output Motion Detection information to the buffer. 556 * 557 * mpp_task_meta_set_buffer(task, KEY_MOTION_INFO, buffer); 558 * 559 * Motion Detection information will be organized in this way: 560 * 1. Each 16x16 block will have a 32 bit block information which contains 561 * 15 bit SAD(Sum of Abstract Difference value 562 * 9 bit signed horizontal motion vector 563 * 8 bit signed vertical motion vector 564 * 2. The sequence of MD information in the buffer is corresponding to the 565 * block position in the frame, left-to right, top-to-bottom. 566 * 3. If the width of the frame is not a multiple of 256 pixels (16 macro 567 * blocks), DMA would extend the frame to a multiple of 256 pixels and 568 * the extended blocks' MD information are 32'h0000_0000. 569 * 4. Buffer must be ion buffer and 1024 byte aligned. 570 */ 571 typedef struct MppEncMDBlkInfo_t { 572 RK_U32 sad : 15; /* bit 0~14 - SAD */ 573 RK_S32 mvx : 9; /* bit 15~23 - signed horizontal mv */ 574 RK_S32 mvy : 8; /* bit 24~31 - signed vertical mv */ 575 } MppEncMDBlkInfo; 576 577 typedef enum MppEncHeaderMode_e { 578 /* default mode: attach vps/sps/pps only on first frame */ 579 MPP_ENC_HEADER_MODE_DEFAULT, 580 /* IDR mode: attach vps/sps/pps on each IDR frame */ 581 MPP_ENC_HEADER_MODE_EACH_IDR, 582 MPP_ENC_HEADER_MODE_BUTT, 583 } MppEncHeaderMode; 584 585 typedef enum MppEncSeiMode_e { 586 MPP_ENC_SEI_MODE_DISABLE, /* default mode, SEI writing is disabled */ 587 MPP_ENC_SEI_MODE_ONE_SEQ, /* one sequence has only one SEI */ 588 MPP_ENC_SEI_MODE_ONE_FRAME /* one frame may have one SEI, if SEI info has changed */ 589 } MppEncSeiMode; 590 591 /* 592 * Mpp codec parameter 593 * parameter is defined from here 594 */ 595 typedef struct MppEncVuiCfg_t { 596 RK_U32 change; 597 RK_S32 vui_en; 598 RK_S32 vui_aspect_ratio; 599 RK_S32 vui_sar_size; 600 RK_S32 full_range; 601 RK_S32 time_scale; 602 } MppEncVuiCfg; 603 604 /* 605 * H.264 configurable parameter 606 */ 607 /* default H.264 hardware config */ 608 typedef struct MppEncH264HwCfg_t { 609 /* 610 * VEPU 1/2 : 2 611 * others : 0 612 */ 613 RK_U32 hw_poc_type; 614 /* 615 * VEPU 1/2 : fixed to 12 616 * others : changeable, default 12 617 */ 618 RK_U32 hw_log2_max_frame_num_minus4; 619 /* default 0, only RKVENC2 support split out */ 620 RK_U32 hw_split_out; 621 } MppEncH264HwCfg; 622 623 typedef struct MppEncH264Cfg_t { 624 /* 625 * H.264 stream format 626 * 0 - H.264 Annex B: NAL unit starts with '00 00 00 01' 627 * 1 - Plain NAL units without startcode 628 */ 629 RK_S32 stream_type; 630 631 /* 632 * H.264 codec syntax config 633 * 634 * do NOT setup the three option below unless you are familiar with encoder detail 635 * poc_type - picture order count type 0 ~ 2 636 * log2_max_poc_lsb - used in sps with poc_type 0, 637 * log2_max_frame_num - used in sps 638 */ 639 RK_U32 poc_type; 640 RK_U32 log2_max_poc_lsb; 641 RK_U32 log2_max_frame_num; /* actually log2_max_frame_num_minus4 */ 642 RK_U32 gaps_not_allowed; 643 644 MppEncH264HwCfg hw_cfg; 645 646 /* 647 * H.264 profile_idc parameter 648 * 66 - Baseline profile 649 * 77 - Main profile 650 * 100 - High profile 651 */ 652 RK_S32 profile; 653 654 /* 655 * H.264 level_idc parameter 656 * 10 / 11 / 12 / 13 - qcif@15fps / cif@7.5fps / cif@15fps / cif@30fps 657 * 20 / 21 / 22 - cif@30fps / half-D1@@25fps / D1@12.5fps 658 * 30 / 31 / 32 - D1@25fps / 720p@30fps / 720p@60fps 659 * 40 / 41 / 42 - 1080p@30fps / 1080p@30fps / 1080p@60fps 660 * 50 / 51 / 52 - 4K@30fps 661 */ 662 RK_S32 level; 663 664 /* 665 * H.264 entropy coding method 666 * 0 - CAVLC 667 * 1 - CABAC 668 * When CABAC is select cabac_init_idc can be range 0~2 669 */ 670 RK_S32 entropy_coding_mode; 671 RK_S32 entropy_coding_mode_ex; 672 RK_S32 cabac_init_idc; 673 RK_S32 cabac_init_idc_ex; 674 675 /* 676 * 8x8 intra prediction and 8x8 transform enable flag 677 * This flag can only be enable under High profile 678 * 0 : disable (BP/MP) 679 * 1 : enable (HP) 680 */ 681 RK_S32 transform8x8_mode; 682 RK_S32 transform8x8_mode_ex; 683 684 /* 685 * 0 : disable 686 * 1 : enable 687 */ 688 RK_S32 constrained_intra_pred_mode; 689 690 /* 691 * 0 : flat scaling list 692 * 1 : default scaling list for all cases 693 * 2 : customized scaling list (not supported) 694 */ 695 RK_S32 scaling_list_mode; 696 697 /* 698 * chroma qp offset (-12 - 12) 699 */ 700 RK_S32 chroma_cb_qp_offset; 701 RK_S32 chroma_cr_qp_offset; 702 703 /* 704 * H.264 deblock filter mode flag 705 * 0 : enable 706 * 1 : disable 707 * 2 : disable deblocking filter at slice boundaries 708 * 709 * deblock filter offset alpha (-6 - 6) 710 * deblock filter offset beta (-6 - 6) 711 */ 712 RK_S32 deblock_disable; 713 RK_S32 deblock_offset_alpha; 714 RK_S32 deblock_offset_beta; 715 716 /* 717 * H.264 long term reference picture enable flag 718 * 0 - disable 719 * 1 - enable 720 */ 721 RK_S32 use_longterm; 722 723 /* 724 * quality config 725 * qp_max - 8 ~ 51 726 * qp_max_i - 10 ~ 40 727 * qp_min - 8 ~ 48 728 * qp_min_i - 10 ~ 40 729 * qp_max_step - max delta qp step between two frames 730 */ 731 RK_S32 qp_init; 732 RK_S16 qp_max; 733 RK_S16 qp_max_i; 734 RK_S16 qp_min; 735 RK_S16 qp_min_i; 736 RK_S16 qp_max_step; 737 RK_S16 qp_delta_ip; 738 739 /* 740 * intra fresh config 741 * 742 * intra_refresh_mode 743 * 0 - no intra refresh 744 * 1 - intra refresh by MB row 745 * 2 - intra refresh by MB column 746 * 3 - intra refresh by MB gap 747 * 748 * intra_refresh_arg 749 * mode 0 - no effect 750 * mode 1 - refresh MB row number 751 * mode 2 - refresh MB colmn number 752 * mode 3 - refresh MB gap count 753 */ 754 RK_S32 intra_refresh_mode; 755 RK_S32 intra_refresh_arg; 756 757 /* extra mode config */ 758 RK_S32 max_ltr_frames; 759 RK_S32 max_tid; 760 RK_S32 prefix_mode; 761 RK_S32 base_layer_pid; 762 /* 763 * Mpp encoder constraint_set parameter 764 * Mpp encoder constraint_set controls constraint_setx_flag in AVC. 765 * Mpp encoder constraint_set uses type RK_U32 to store force_flag and constraint_force as followed. 766 * | 00 | force_flag | 00 | constraint_force | 767 * As for force_flag and constraint_force, only low 6 bits are valid, 768 * corresponding to constraint_setx_flag from 5 to 0. 769 * If force_flag bit is enabled, constraint_setx_flag will be set correspondingly. 770 * Otherwise, constraint_setx_flag will use default value. 771 */ 772 RK_U32 constraint_set; 773 774 /* extra info */ 775 MppEncVuiCfg vui; 776 } MppEncH264Cfg; 777 778 #define H265E_MAX_ROI_NUMBER 64 779 780 typedef struct H265eRect_t { 781 RK_S32 left; 782 RK_S32 right; 783 RK_S32 top; 784 RK_S32 bottom; 785 } H265eRect; 786 787 typedef struct H265eRoi_Region_t { 788 RK_U8 level; 789 H265eRect rect; 790 } H265eRoiRegion; 791 792 typedef struct H265eCtuQp_t { 793 /* the qp value using in ctu region */ 794 RK_U32 qp; 795 796 /* 797 * define the ctu region 798 * method = H265E_METHOD_CUT_SIZE, the value of rect is in ctu size 799 * method = H264E_METHOD_COORDINATE,the value of rect is in coordinates 800 */ 801 H265eRect rect; 802 } H265eCtu; 803 804 /* 805 * define the method when set CTU/ROI parameters 806 * this value is using by method in H265eCtuRegion or H265eRoi struct 807 */ 808 typedef enum { 809 H265E_METHOD_CTU_SIZE, 810 H264E_METHOD_COORDINATE, 811 } H265eCtuMethod; 812 813 /* 814 * H.265 configurable parameter 815 */ 816 typedef struct MppEncH265SliceCfg_t { 817 /* default value: 0, means no slice split*/ 818 RK_U32 split_enable; 819 820 /* 0: by bits number; 1: by lcu line number*/ 821 RK_U32 split_mode; 822 823 /* 824 * when splitmode is 0, this value presents bits number, 825 * when splitmode is 1, this value presents lcu line number 826 */ 827 RK_U32 slice_size; 828 RK_U32 slice_out; 829 } MppEncH265SliceCfg; 830 831 typedef struct MppEncH265CuCfg_t { 832 RK_U32 cu32x32_en; /*default: 1 */ 833 RK_U32 cu16x16_en; /*default: 1 */ 834 RK_U32 cu8x8_en; /*default: 1 */ 835 RK_U32 cu4x4_en; /*default: 1 */ 836 837 // intra pred 838 RK_U32 constrained_intra_pred_flag; /*default: 0 */ 839 RK_U32 strong_intra_smoothing_enabled_flag; /*INTRA_SMOOTH*/ 840 RK_U32 pcm_enabled_flag; /*default: 0, enable ipcm*/ 841 RK_U32 pcm_loop_filter_disabled_flag; 842 } MppEncH265CuCfg; 843 844 typedef struct MppEncH265DblkCfg_t { 845 RK_U32 slice_deblocking_filter_disabled_flag; /* default value: 0. {0,1} */ 846 RK_S32 slice_beta_offset_div2; /* default value: 0. [-6,+6] */ 847 RK_S32 slice_tc_offset_div2; /* default value: 0. [-6,+6] */ 848 } MppEncH265DblkCfg_t; 849 850 typedef struct MppEncH265SaoCfg_t { 851 RK_U32 slice_sao_luma_disable; 852 RK_U32 slice_sao_chroma_disable; 853 RK_U32 sao_bit_ratio; 854 } MppEncH265SaoCfg; 855 856 typedef struct MppEncH265TransCfg_t { 857 RK_U32 transquant_bypass_enabled_flag; 858 RK_U32 transform_skip_enabled_flag; 859 RK_U32 scaling_list_mode; /* default: 0 */ 860 RK_S32 cb_qp_offset; 861 RK_S32 cr_qp_offset; 862 RK_S32 diff_cu_qp_delta_depth; 863 } MppEncH265TransCfg; 864 865 typedef struct MppEncH265MergeCfg_t { 866 RK_U32 max_mrg_cnd; 867 RK_U32 merge_up_flag; 868 RK_U32 merge_left_flag; 869 } MppEncH265MergesCfg; 870 871 typedef struct MppEncH265EntropyCfg_t { 872 RK_U32 cabac_init_flag; /* default: 0 */ 873 } MppEncH265EntropyCfg; 874 875 typedef struct MppEncH265Cfg_t { 876 /* H.265 codec syntax config */ 877 RK_S32 profile; 878 RK_S32 level; 879 RK_S32 tier; 880 881 /* constraint intra prediction flag */ 882 RK_S32 const_intra_pred; 883 RK_S32 ctu_size; 884 RK_S32 max_cu_size; 885 RK_S32 tmvp_enable; 886 RK_S32 amp_enable; 887 RK_S32 wpp_enable; 888 RK_S32 merge_range; 889 RK_S32 sao_enable; 890 RK_U32 num_ref; 891 892 /* quality config */ 893 RK_S32 intra_qp; 894 RK_U8 qpmax_map[8]; 895 RK_U8 qpmin_map[8]; 896 RK_S32 qpmap_mode; 897 898 /* extra mode config */ 899 RK_S32 max_ltr_frames; 900 RK_S32 max_tid; 901 RK_S32 base_layer_pid; 902 903 MppEncH265CuCfg cu_cfg; 904 MppEncH265SliceCfg slice_cfg; 905 MppEncH265EntropyCfg entropy_cfg; 906 MppEncH265TransCfg trans_cfg; 907 MppEncH265SaoCfg sao_cfg; 908 MppEncH265DblkCfg_t dblk_cfg; 909 MppEncH265MergesCfg merge_cfg; 910 RK_S32 auto_tile; 911 RK_U32 lpf_acs_sli_en; 912 RK_U32 lpf_acs_tile_disable; 913 914 /* extra info */ 915 MppEncVuiCfg vui; 916 } MppEncH265Cfg; 917 918 /* 919 * motion jpeg configurable parameter 920 */ 921 typedef enum MppEncJpegQpMode_e { 922 JPEG_QP_NA = 0, 923 JPEG_QUANT = 1, 924 JPEG_QFACTOR = 2, 925 JPEG_QTABLE = 3, 926 } MppEncJpegQpMode; 927 928 typedef struct MppEncJpegCfg_t { 929 RK_S32 q_mode; 930 RK_S32 update; 931 932 RK_S32 quant; 933 RK_S32 quant_ext; 934 /* 935 * quality factor config 936 * 937 * q_factor - 1 ~ 99 938 * qf_max - 1 ~ 99 939 * qf_min - 1 ~ 99 940 * qtable_y: qtable for luma 941 * qtable_u: qtable for chroma 942 * qtable_v: default equal qtable_u 943 */ 944 RK_S32 q_factor; 945 RK_S32 q_factor_ext; 946 RK_S32 qf_max; 947 RK_S32 qf_max_ext; 948 RK_S32 qf_min; 949 RK_S32 qf_min_ext; 950 /* 951 * qtable_y: qtable for luma 952 * qtable_u: qtable for chroma u 953 * qtable_v: qtable for chroma v 954 * for most case u and v use the same table 955 */ 956 RK_U8 qtable_y[64]; 957 RK_U8 qtable_u[64]; 958 RK_U8 qtable_v[64]; 959 } MppEncJpegCfg; 960 961 /* 962 * vp8 configurable parameter 963 */ 964 typedef struct MppEncVp8Cfg_t { 965 RK_S32 quant; 966 RK_S32 disable_ivf; 967 } MppEncVp8Cfg; 968 969 typedef enum MppEncSliceSplit_e { 970 /* change on quant parameter */ 971 MPP_ENC_SPLIT_CFG_CHANGE_MODE = (1 << 0), 972 MPP_ENC_SPLIT_CFG_CHANGE_ARG = (1 << 1), 973 MPP_ENC_SPLIT_CFG_CHANGE_OUTPUT = (1 << 2), 974 MPP_ENC_SPLIT_CFG_CHANGE_ALL = (0xFFFFFFFF), 975 } MppEncSliceSplitChange; 976 977 typedef enum MppEncSplitMode_e { 978 MPP_ENC_SPLIT_NONE, 979 MPP_ENC_SPLIT_BY_BYTE, 980 MPP_ENC_SPLIT_BY_CTU, 981 MPP_ENC_SPLIT_MODE_BUTT, 982 } MppEncSplitMode; 983 984 typedef enum MppEncSplitOutMode_e { 985 MPP_ENC_SPLIT_OUT_LOWDELAY = (1 << 0), 986 MPP_ENC_SPLIT_OUT_SEGMENT = (1 << 1), 987 } MppEncSplitOutMode; 988 989 typedef struct MppEncSliceSplit_t { 990 RK_U32 change; 991 /* 992 * slice split mode 993 * 994 * MPP_ENC_SPLIT_NONE - No slice is split 995 * MPP_ENC_SPLIT_BY_BYTE - Slice is split by byte number 996 * MPP_ENC_SPLIT_BY_CTU - Slice is split by macroblock / ctu number 997 */ 998 RK_U32 split_mode; 999 1000 /* 1001 * slice split size parameter 1002 * 1003 * When split by byte number this value is the max byte number for each 1004 * slice. 1005 * When split by macroblock / ctu number this value is the MB/CTU number 1006 * for each slice. 1007 */ 1008 RK_U32 split_arg; 1009 1010 /* 1011 * slice split output mode 1012 * 1013 * MPP_ENC_SPLIT_OUT_LOWDELAY 1014 * - When enabled encoder will lowdelay output each slice in a single packet 1015 * MPP_ENC_SPLIT_OUT_SEGMENT 1016 * - When enabled encoder will packet with segment info for each slice 1017 */ 1018 RK_U32 split_out; 1019 } MppEncSliceSplit; 1020 1021 /** 1022 * @brief Mpp ROI parameter 1023 * Region configure define a rectangle as ROI 1024 * @note x, y, w, h are calculated in pixels, which had better be 16-pixel aligned. 1025 * These parameters MUST retain in memory when encoder is running. 1026 * Both absolute qp and relative qp are supported in vepu541. 1027 * Only absolute qp is supported in rv1108 1028 */ 1029 typedef struct MppEncROIRegion_t { 1030 RK_U16 x; /**< horizontal position of top left corner */ 1031 RK_U16 y; /**< vertical position of top left corner */ 1032 RK_U16 w; /**< width of ROI rectangle */ 1033 RK_U16 h; /**< height of ROI rectangle */ 1034 RK_U16 intra; /**< flag of forced intra macroblock */ 1035 RK_S16 quality; /**< absolute / relative qp of macroblock */ 1036 RK_U16 qp_area_idx; /**< qp min max area select*/ 1037 RK_U8 area_map_en; /**< enable area map */ 1038 RK_U8 abs_qp_en; /**< absolute qp enable flag*/ 1039 } MppEncROIRegion; 1040 1041 /** 1042 * @brief MPP encoder's ROI configuration 1043 */ 1044 typedef struct MppEncROICfg_t { 1045 RK_U32 number; /**< ROI rectangle number */ 1046 MppEncROIRegion *regions; /**< ROI parameters */ 1047 } MppEncROICfg; 1048 1049 typedef struct MppEncROICfg0_t { 1050 RK_U32 change; /**< change flag */ 1051 RK_U32 number; /**< ROI rectangle number */ 1052 MppEncROIRegion regions[8]; /**< ROI parameters */ 1053 } MppEncROICfgLegacy; 1054 1055 /** 1056 * @brief Mpp ROI parameter for vepu54x / vepu58x 1057 * @note These encoders have more complex roi configure structure. 1058 * User need to generate roi structure data for different soc. 1059 * And send buffers to encoder through metadata. 1060 */ 1061 typedef struct MppEncROICfg2_t { 1062 MppBuffer base_cfg_buf; 1063 MppBuffer qp_cfg_buf; 1064 MppBuffer amv_cfg_buf; 1065 MppBuffer mv_cfg_buf; 1066 1067 RK_U32 roi_qp_en : 1; 1068 RK_U32 roi_amv_en : 1; 1069 RK_U32 roi_mv_en : 1; 1070 RK_U32 reserve_bits : 29; 1071 RK_U32 reserve[3]; 1072 } MppEncROICfg2; 1073 1074 typedef struct MppJpegROIRegion_t { 1075 RK_U16 x; /* horizontal position of top left corner */ 1076 RK_U16 y; /* vertical position of top left corner */ 1077 RK_U16 w; /* width of ROI rectangle */ 1078 RK_U16 h; /* height of ROI rectangle */ 1079 RK_U8 level; /* the strength of erasing residuals for roi */ 1080 RK_U8 roi_en; /* enable roi */ 1081 } MppJpegROIRegion; 1082 1083 typedef struct MppJpegROICfg_t { 1084 RK_U32 change; 1085 RK_U16 non_roi_level; /* the strength of erasing residuals for non-roi */ 1086 RK_U16 non_roi_en; /* enable non-roi */ 1087 MppJpegROIRegion regions[16]; 1088 } MppJpegROICfg; 1089 1090 /* 1091 * Mpp OSD parameter 1092 * 1093 * Mpp OSD support total 8 regions 1094 * Mpp OSD support 256-color palette two mode palette: 1095 * 1. Configurable OSD palette 1096 * When palette is set. 1097 * 2. fixed OSD palette 1098 * When palette is NULL. 1099 * 1100 * if MppEncOSDPlt.buf != NULL , palette includes maximun 256 levels, 1101 * every level composed of 32 bits defined below: 1102 * Y : 8 bits 1103 * U : 8 bits 1104 * V : 8 bits 1105 * alpha : 8 bits 1106 */ 1107 #define MPP_ENC_OSD_PLT_WHITE ((255<<24)|(128<<16)|(128<<8)|235) 1108 #define MPP_ENC_OSD_PLT_YELLOW ((255<<24)|(146<<16)|( 16<<8)|210) 1109 #define MPP_ENC_OSD_PLT_CYAN ((255<<24)|( 16<<16)|(166<<8)|170) 1110 #define MPP_ENC_OSD_PLT_GREEN ((255<<24)|( 34<<16)|( 54<<8)|145) 1111 #define MPP_ENC_OSD_PLT_TRANS (( 0<<24)|(222<<16)|(202<<8)|106) 1112 #define MPP_ENC_OSD_PLT_RED ((255<<24)|(240<<16)|( 90<<8)| 81) 1113 #define MPP_ENC_OSD_PLT_BLUE ((255<<24)|(110<<16)|(240<<8)| 41) 1114 #define MPP_ENC_OSD_PLT_BLACK ((255<<24)|(128<<16)|(128<<8)| 16) 1115 1116 typedef enum MppEncOSDPltType_e { 1117 MPP_ENC_OSD_PLT_TYPE_DEFAULT, 1118 MPP_ENC_OSD_PLT_TYPE_USERDEF, 1119 MPP_ENC_OSD_PLT_TYPE_BUTT, 1120 } MppEncOSDPltType; 1121 1122 /* OSD palette value define */ 1123 typedef union MppEncOSDPltVal_u { 1124 struct { 1125 RK_U32 v : 8; 1126 RK_U32 u : 8; 1127 RK_U32 y : 8; 1128 RK_U32 alpha : 8; 1129 }; 1130 RK_U32 val; 1131 } MppEncOSDPltVal; 1132 1133 typedef struct MppEncOSDPlt_t { 1134 MppEncOSDPltVal data[256]; 1135 } MppEncOSDPlt; 1136 1137 typedef enum MppEncOSDPltCfgChange_e { 1138 MPP_ENC_OSD_PLT_CFG_CHANGE_MODE = (1 << 0), /* change osd plt type */ 1139 MPP_ENC_OSD_PLT_CFG_CHANGE_PLT_VAL = (1 << 1), /* change osd plt table value */ 1140 MPP_ENC_OSD_PLT_CFG_CHANGE_ALL = (0xFFFFFFFF), 1141 } MppEncOSDPltCfgChange; 1142 1143 typedef struct MppEncOSDPltCfg_t { 1144 RK_U32 change; 1145 MppEncOSDPltType type; 1146 MppEncOSDPlt *plt; 1147 } MppEncOSDPltCfg; 1148 1149 /* position info is unit in 16 pixels(one MB), and 1150 * x-directon range in pixels = (rd_pos_x - lt_pos_x + 1) * 16; 1151 * y-directon range in pixels = (rd_pos_y - lt_pos_y + 1) * 16; 1152 */ 1153 typedef struct MppEncOSDRegion_t { 1154 RK_U32 enable; 1155 RK_U32 inverse; 1156 RK_U32 start_mb_x; 1157 RK_U32 start_mb_y; 1158 RK_U32 num_mb_x; 1159 RK_U32 num_mb_y; 1160 RK_U32 buf_offset; 1161 } MppEncOSDRegion; 1162 1163 /* if num_region > 0 && region==NULL 1164 * use old osd data 1165 */ 1166 typedef struct MppEncOSDData_t { 1167 MppBuffer buf; 1168 RK_U32 num_region; 1169 MppEncOSDRegion region[8]; 1170 } MppEncOSDData; 1171 1172 typedef struct MppEncOSDRegion2_t { 1173 RK_U32 enable; 1174 RK_U32 inverse; 1175 RK_U32 start_mb_x; 1176 RK_U32 start_mb_y; 1177 RK_U32 num_mb_x; 1178 RK_U32 num_mb_y; 1179 RK_U32 buf_offset; 1180 MppBuffer buf; 1181 } MppEncOSDRegion2; 1182 1183 typedef struct MppEncOSDData2_t { 1184 RK_U32 num_region; 1185 MppEncOSDRegion2 region[8]; 1186 } MppEncOSDData2; 1187 1188 /* kmpp osd configure */ 1189 typedef struct EncOSDInvCfg_t { 1190 RK_U32 yg_inv_en; 1191 RK_U32 uvrb_inv_en; 1192 RK_U32 alpha_inv_en; 1193 RK_U32 inv_sel; 1194 RK_U32 uv_sw_inv_en; 1195 RK_U32 inv_size; 1196 RK_U32 inv_stride; 1197 KmppShmPtr inv_buf; 1198 } EncOSDInvCfg; 1199 1200 typedef struct EncOSDAlphaCfg_t { 1201 RK_U32 alpha_swap; 1202 RK_U32 bg_alpha; 1203 RK_U32 fg_alpha; 1204 RK_U32 fg_alpha_sel; 1205 } EncOSDAlphaCfg; 1206 1207 typedef struct EncOSDQpCfg_t { 1208 RK_U32 qp_adj_en; 1209 RK_U32 qp_adj_sel; 1210 RK_S32 qp; 1211 RK_U32 qp_max; 1212 RK_U32 qp_min; 1213 RK_U32 qp_prj; 1214 } EncOSDQpCfg; 1215 1216 typedef struct MppEncOSDRegion3_t { 1217 RK_U32 enable; 1218 RK_U32 range_trns_en; 1219 RK_U32 range_trns_sel; 1220 RK_U32 fmt; 1221 RK_U32 rbuv_swap; 1222 RK_U32 lt_x; 1223 RK_U32 lt_y; 1224 RK_U32 rb_x; 1225 RK_U32 rb_y; 1226 RK_U32 stride; 1227 RK_U32 ch_ds_mode; 1228 RK_U32 osd_endn; 1229 EncOSDInvCfg inv_cfg; 1230 EncOSDAlphaCfg alpha_cfg; 1231 EncOSDQpCfg qp_cfg; 1232 KmppShmPtr osd_buf; 1233 RK_U8 lut[8]; //vuy vuy alpha 1234 } MppEncOSDRegion3; 1235 1236 typedef struct MppEncOSDData3_t { 1237 RK_U32 change; 1238 RK_U32 num_region; 1239 MppEncOSDRegion3 region[8]; 1240 } MppEncOSDData3; 1241 /* kmpp osd configure end */ 1242 1243 typedef struct MppEncUserData_t { 1244 RK_U32 len; 1245 void *pdata; 1246 } MppEncUserData; 1247 1248 typedef struct MppEncUserDataFull_t { 1249 RK_U32 len; 1250 RK_U8 *uuid; 1251 void *pdata; 1252 } MppEncUserDataFull; 1253 1254 typedef struct MppEncUserDataSet_t { 1255 RK_U32 count; 1256 MppEncUserDataFull *datas; 1257 } MppEncUserDataSet; 1258 1259 typedef enum MppEncSceneMode_e { 1260 MPP_ENC_SCENE_MODE_DEFAULT, 1261 MPP_ENC_SCENE_MODE_IPC, 1262 MPP_ENC_SCENE_MODE_IPC_PTZ, 1263 MPP_ENC_SCENE_MODE_BUTT, 1264 } MppEncSceneMode; 1265 1266 typedef struct MppEncFineTuneCfg_t { 1267 MppEncSceneMode scene_mode; 1268 MppEncSeMode se_mode; 1269 RK_S32 deblur_en; /* qpmap_en */ 1270 RK_S32 deblur_str; /* deblur strength */ 1271 RK_S32 anti_flicker_str; 1272 RK_S32 lambda_idx_i; 1273 RK_S32 lambda_idx_p; 1274 RK_S32 atr_str_i; /* line_en */ 1275 RK_S32 atr_str_p; /* line_en */ 1276 RK_S32 atl_str; /* anti_stripe */ 1277 RK_S32 sao_str_i; /* anti blur */ 1278 RK_S32 sao_str_p; /* anti blur */ 1279 RK_S32 rc_container; 1280 RK_S32 vmaf_opt; 1281 1282 RK_S32 motion_static_switch_enable; 1283 RK_S32 atf_str; 1284 /* vepu500 only */ 1285 RK_S32 lgt_chg_lvl; /* light change level, [0, 3] */ 1286 RK_S32 static_frm_num; /* static frame number, [0, 7] */ 1287 RK_S32 madp16_th; /* madp threshold for static block detection, [0, 63] */ 1288 RK_S32 skip16_wgt; /* weight for skip16, 0 or [3, 8] */ 1289 RK_S32 skip32_wgt; /* weight for skip32, 0 or [3, 8] */ 1290 RK_S32 qpmap_en; 1291 RK_S32 speed; /* encoder speed [0..3], 0:normal; 1:fast; 2:faster; 3:fastest */ 1292 1293 /* smart v3 only */ 1294 RK_S32 bg_delta_qp_i; /* background delta qp for i frame */ 1295 RK_S32 bg_delta_qp_p; /* background delta qp for p frame */ 1296 RK_S32 fg_delta_qp_i; /* foreground delta qp for i frame */ 1297 RK_S32 fg_delta_qp_p; /* foreground delta qp for p frame */ 1298 RK_S32 bmap_qpmin_i; /* min qp for i frame in bmap */ 1299 RK_S32 bmap_qpmin_p; /* min qp for p frame in bmap */ 1300 RK_S32 bmap_qpmax_i; /* max qp for i frame in bmap */ 1301 RK_S32 bmap_qpmax_p; /* max qp for p frame in bmap */ 1302 RK_S32 min_bg_fqp; /* min frame qp for background region */ 1303 RK_S32 max_bg_fqp; /* max frame qp for background region */ 1304 RK_S32 min_fg_fqp; /* min frame qp for foreground region */ 1305 RK_S32 max_fg_fqp; /* max frame qp for foreground region */ 1306 RK_S32 fg_area; /* foreground area, [-1, 100] */ 1307 } MppEncFineTuneCfg; 1308 1309 #endif /*__RK_VENC_CMD_H__*/ 1310