1*437bfbebSnyanmisaka /* SPDX-License-Identifier: Apache-2.0 OR MIT */ 2*437bfbebSnyanmisaka /* 3*437bfbebSnyanmisaka * Copyright (c) 2024 Rockchip Electronics Co., Ltd. 4*437bfbebSnyanmisaka */ 5*437bfbebSnyanmisaka 6*437bfbebSnyanmisaka #ifndef __MPP_SYS_CFG_H__ 7*437bfbebSnyanmisaka #define __MPP_SYS_CFG_H__ 8*437bfbebSnyanmisaka 9*437bfbebSnyanmisaka #include "mpp_frame.h" 10*437bfbebSnyanmisaka #include "mpp_list.h" 11*437bfbebSnyanmisaka 12*437bfbebSnyanmisaka typedef enum MppSysDecBufCkhCfgChange_e { 13*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_ENABLE = (1 << 0), 14*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_TYPE = (1 << 1), 15*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_FMT_CODEC = (1 << 2), 16*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_FMT_FBC = (1 << 3), 17*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_FMT_HDR = (1 << 4), 18*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_WIDTH = (1 << 5), 19*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_HEIGHT = (1 << 6), 20*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_CROP_TOP = (1 << 7), 21*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_CROP_BOTTOM = (1 << 8), 22*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_CROP_LEFT = (1 << 9), 23*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_CROP_RIGHT = (1 << 10), 24*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_FLAG_METADATA = (1 << 11), 25*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_FLAG_THUMBNAIL = (1 << 12), 26*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_H_STRIDE_BYTE = (1 << 13), 27*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_V_STRIDE = (1 << 14), 28*437bfbebSnyanmisaka 29*437bfbebSnyanmisaka MPP_SYS_DEC_BUF_CHK_CFG_CHANGE_ALL = (0xFFFFFFFF), 30*437bfbebSnyanmisaka } MppSysDecBufCkhChange; 31*437bfbebSnyanmisaka 32*437bfbebSnyanmisaka typedef struct MppSysBaseCfg_t { 33*437bfbebSnyanmisaka RK_U64 change; 34*437bfbebSnyanmisaka 35*437bfbebSnyanmisaka RK_U32 enable; 36*437bfbebSnyanmisaka 37*437bfbebSnyanmisaka /* input args start */ 38*437bfbebSnyanmisaka MppCodingType type; 39*437bfbebSnyanmisaka MppFrameFormat fmt_codec; 40*437bfbebSnyanmisaka RK_U32 fmt_fbc; 41*437bfbebSnyanmisaka RK_U32 fmt_hdr; 42*437bfbebSnyanmisaka 43*437bfbebSnyanmisaka /* video codec width and height */ 44*437bfbebSnyanmisaka RK_U32 width; 45*437bfbebSnyanmisaka RK_U32 height; 46*437bfbebSnyanmisaka 47*437bfbebSnyanmisaka /* display crop info */ 48*437bfbebSnyanmisaka RK_U32 crop_top; 49*437bfbebSnyanmisaka RK_U32 crop_bottom; 50*437bfbebSnyanmisaka RK_U32 crop_left; 51*437bfbebSnyanmisaka RK_U32 crop_right; 52*437bfbebSnyanmisaka 53*437bfbebSnyanmisaka /* bit mask for metadata and thumbnail config */ 54*437bfbebSnyanmisaka RK_U32 has_metadata; 55*437bfbebSnyanmisaka RK_U32 has_thumbnail; 56*437bfbebSnyanmisaka 57*437bfbebSnyanmisaka /* extra protocol config */ 58*437bfbebSnyanmisaka /* H.265 ctu size, VP9/Av1 super block size */ 59*437bfbebSnyanmisaka RK_U32 unit_size; 60*437bfbebSnyanmisaka 61*437bfbebSnyanmisaka /* output args start */ 62*437bfbebSnyanmisaka /* system support capability */ 63*437bfbebSnyanmisaka RK_U32 cap_fbc; 64*437bfbebSnyanmisaka RK_U32 cap_tile; 65*437bfbebSnyanmisaka 66*437bfbebSnyanmisaka /* 2 horizontal stride for 2 planes like Y/UV */ 67*437bfbebSnyanmisaka RK_U32 h_stride_by_pixel; 68*437bfbebSnyanmisaka RK_U32 h_stride_by_byte; 69*437bfbebSnyanmisaka RK_U32 v_stride; 70*437bfbebSnyanmisaka RK_U32 buf_total_size; 71*437bfbebSnyanmisaka 72*437bfbebSnyanmisaka /* fbc display offset config for some fbc version */ 73*437bfbebSnyanmisaka RK_U32 offset_y; 74*437bfbebSnyanmisaka RK_U32 size_total; 75*437bfbebSnyanmisaka RK_U32 size_fbc_hdr; 76*437bfbebSnyanmisaka RK_U32 size_fbc_bdy; 77*437bfbebSnyanmisaka 78*437bfbebSnyanmisaka /* extra buffer size */ 79*437bfbebSnyanmisaka RK_U32 size_metadata; 80*437bfbebSnyanmisaka RK_U32 size_thumbnail; 81*437bfbebSnyanmisaka } MppSysDecBufChkCfg; 82*437bfbebSnyanmisaka 83*437bfbebSnyanmisaka typedef struct MppSysCfgSet_t { 84*437bfbebSnyanmisaka RK_U32 change; 85*437bfbebSnyanmisaka MppSysDecBufChkCfg dec_buf_chk; 86*437bfbebSnyanmisaka } MppSysCfgSet; 87*437bfbebSnyanmisaka 88*437bfbebSnyanmisaka #ifdef __cplusplus 89*437bfbebSnyanmisaka extern "C" { 90*437bfbebSnyanmisaka #endif 91*437bfbebSnyanmisaka 92*437bfbebSnyanmisaka MPP_RET mpp_sys_dec_buf_chk_proc(MppSysDecBufChkCfg *cfg); 93*437bfbebSnyanmisaka 94*437bfbebSnyanmisaka #ifdef __cplusplus 95*437bfbebSnyanmisaka } 96*437bfbebSnyanmisaka #endif 97*437bfbebSnyanmisaka 98*437bfbebSnyanmisaka #endif /* __MPP_SYS_CFG_H__ */ 99