1function 1: modify ddr.bin file from ddrbin_param.txt. 2 1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want. 3 If want to keep items default, please keep these items blank. 4 2) run 'ddrbin_tool' with argument 1: ddrbin_param.txt, argument 2: ddr bin file. 5 like: ./ddrbin_tool ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 6 7function 2: get ddr.bin file config to gen_param.txt file 8 If want to get ddrbin file config, please run like that: 9 ./ddrbin_tool -g gen_param.txt px30_ddr_333MHz_v1.15.bin 10 The config will show in gen_param.txt. 11 12The detail information as following: 13 14* support ddrbin version 15 The 'X' means not support change those parameters by tool. 16 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 17 | platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT | 18 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 19 | RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X | 20 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 21 | PX30/RK3326 | V1.11 | X | V1.16 | V1.12 | V1.15 | X | X | X | 22 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 23 | RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | 24 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 25 | RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | 26 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 27 | RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | 28 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 29 | RK3288 | V1.11 | X | X | V1.11 | X | X | X | X | 30 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 31 | RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X | 32 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 33 | RK3308S | V2.05 | V2.05 | V2.05 | V2.05 | V2.05 | X | X | X | 34 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 35 | RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | 36 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 37 | RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | 38 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 39 | RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | 40 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 41 | RK3399PRO NPU | V1.03 | V1.03 | X | V1.03 | X | X | X | X | 42 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 43 | RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | 44 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 45 | RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | 46 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 47 | RK3588 | V1.00 | V1.00 | X | V1.00 | V1.00 | V1.00 | X | X | 48 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 49 50| function | platform and ddrbin version | 51| ------------------------------- | -------------------------------------- | 52| first scan channel/channel mask | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 53| stride type | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 54| ext_temp_ref_en | Null | 55| link_ecc_en | Null | 56| per_bank_ref_en | RK3588 V1.09 | 57| derate_en | RK3588 V1.09 | 58| auto_precharge_en | Null | 59| res_space_remap_portion | RK3588 V1.09 | 60| res_space_remap_all | RK3588 V1.09 | 61| rd_vref_scan_en | RK3588 V1.08 | 62| wr_vref_scan_en | RK3588 V1.08 | 63| eye_2d_scan_en | RK3588 V1.08 | 64| ch/bank/rank_mask | RK3588 V1.00 | 65| pstore base_addr/buf_size | RK3588 V1.09 | 66| uboot/atf/optee/spl/tpl log en | RK3588 V1.09 | 67| boot_fsp | RK3588 V1.09 | 68 69* UART info 70 71uart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 72uart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 73or 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 74uart baudrate: uart baudrate should be 115200 or 1500000. 75 76* disable print training information 77 78dis_train_print: 1: will disabled print training information; 0: will enable print training information. 79 80* recycle registers space(remap register space to DDR) 81 82res_space_remap_portion 831: will remap the part of registers to DDR memory space(will not larger than 4GB). 84It is PCIE and some reserved space in RK3588, and the PCIE can not be used when set to 1. 85 86res_space_remap_all 871: will wrap all registers space(include res_space_remap_portion enable space) to DDR memory space. This space would be place in larger than 4GB. 88The PCIE can be used when set to 1 in RK3588. 89 90* DDR eye scanning 911) eye_2d_scan_en: 1: will enable 2D eye scanning for debug purpose, vref and skew eye scanning. 922) wr_vref_scan_en: 1: enable vref scan and use scanning result for write. 933) rd_vref_scan_en: 1: enable vref scan and use scanning result for read. 94 95* DDR auto precharge 96 97auto_precharge_en: 1: will enable the DDR auto precharge. 98 99* DDR refresh derate 100 101derate_en: 1: will enable derate function of the LP2/LP3/LP4/LP4X/LP5. 102The high temperature will issue more refresh command and the low temperature will less. 103 104* DDR per bank refresh 105 106per_bank_ref_en: 1: will enable per bank refresh 107 108* link ECC enable 109 110link_ecc_en: 1: read/write link ecc enable. 111 112* Extended temperature refresh 113 114ext_temp_ref_en: 1: will enable the extended temperature refresh which is 0.5x refresh operation in all time. 115 116* pstore_base_addr pstore_buf_size 117The pstore buffer base address: pstore_base_addr << 16, 64kB align. 118The pstore buffer size: pstore_buf_size * 4KB. 119It is define the addr and size to save ddrbin log for last log. 120 121* uboot_log_en 1221: enable uboot log. 1230: disable uboot log. 124 125* atf_log_en 1261: enable atf log. 1270: disable atf log. 128 129* optee_log_en 1301: enable optee log. 1310: disable optee log. 132 133* spl_log_en 1341: enable spl log. 1350: disable spl log. 136 137* tpl_log_en 1381: enable tpl log. 1390: disable tpl log. 140 141* boot_fsp 142To choose the which DDR freq to boot system. 0 means fsp0_freq, 1 means fsp1_freq, 2 means fsp2_freq, 3 means fsp3_freq, the default is 0. 143 144* DDR (final) freq(also called ddrx_f0_freq_mhz/fsp0_freq) 145 146For RK3588, the boot_fsp used to choose which ddrx_fx_freq_mhz/fspx_freq to boot system, default is ddrx_f0_freq_mhz/fsp0_freq. 147For the others platform, it is the final freq to boot system. 148 149ddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz. 150lp2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz. 151ddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz. 152lp3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz. 153ddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz. 154lp4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz. 155lp4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz. 156lp5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz. 157 158* support ddr frequency: 159The 'X' as follows means not support change frequencies by tool. 160+---------------+-----------------------------------------------------------------+ 161| platform | support frequencies(MHZ) | 162+---------------+-----------------------------------------------------------------+ 163| RK1108 | DDR2: 400; LP2: <= 533; DDR3: <= 800 | 164+---------------+-----------------------------------------------------------------+ 165| PX30/RK3326 | X | 166+---------------+-----------------------------------------------------------------+ 167| RK1808 | 333,400,533,666,786,933 | 168+---------------+-----------------------------------------------------------------+ 169| RK322x | DDR2/LP2: <= 533; others: <= 800 | 170+---------------+-----------------------------------------------------------------+ 171| RK322xh | X | 172+---------------+-----------------------------------------------------------------+ 173| RK3288 | X | 174+---------------+-----------------------------------------------------------------+ 175| RK3308/RK3308S| DDR2/LP2: 393,451; DDR3: 393,451,589 | 176+---------------+-----------------------------------------------------------------+ 177| RK3368 | DDR3: <= 800; LP3: <= 666 | 178+---------------+-----------------------------------------------------------------+ 179| RK3328 | X | 180+---------------+-----------------------------------------------------------------+ 181| RK3399 | X | 182+---------------+-----------------------------------------------------------------+ 183| RK3399PRO NPU | 333,400,533,666,786,933 | 184+---------------+-----------------------------------------------------------------+ 185| RV1126/RV1109 | 328,396,528,664,784,924,1056 | 186+---------------+-----------------------------------------------------------------+ 187| RK3566 | 324,396,528,630,780,920,1056 | 188+---------------+-----------------------------------------------------------------+ 189| RK3568 | DDR3/LP3: 324,396,528,630,780,920,1056 | 190| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184,1332,1560 | 191+---------------+-----------------------------------------------------------------+ 192| RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] | 193+---------------+-----------------------------------------------------------------+ 194| RK3528 | DDR3/LP3: 324,396,528,630,780,920,1056 | 195| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184 | 196+---------------+-----------------------------------------------------------------+ 197 198* DDR frequencies(add more) 199 200ddr2_f1_freq_mhz: ddr2 frequency fsp 1, unit:MHz. 201ddr2_f2_freq_mhz: ddr2 frequency fsp 2, unit:MHz. 202ddr2_f3_freq_mhz: ddr2 frequency fsp 3, unit:MHz. 203ddr2_f4_freq_mhz: ddr2 frequency fsp 4, unit:MHz. 204ddr2_f5_freq_mhz: ddr2 frequency fsp 5, unit:MHz. 205... 206The ddrx_f0_freq_mhz(the fsp0 frequency) is named ddrx_freq. 207 208ddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used. 209The program will initialize dram by following order. 210for example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq. 211And the final frequency is ddr4_freq to boot system. 212The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 213So it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'. 214Such as: ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq) 215For example: 216 ... 217 ddr4_freq=1560 218 ... 219 ddr4_f1_freq_mhz=324 220 ddr4_f2_freq_mhz=528 221 ddr4_f3_freq_mhz=780 222 ... 223 224Note: The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 225 226* SR PD idle 227 228sr_idle: auto self-refresh mode delay time. 229pd_idle: auto power-down mode delay time. 230 231* DDR 2T 232 233ddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 234 235* PLL ssmod 236 237These parameters are about Spread Spectrum Modulator(ssmod) for PLL. 238ssmod_downspread: ssmod work mode. 1: down spread, 0: center spread. 239ssmod_div: Divider required to set the modulation frequency. RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5. 240ssmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f. 241 242* driver strength 243 244phy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm. 245phy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm. 246phy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm. 247ddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm. 248phy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm. 249phy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm. 250phy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm. 251ddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm. 252 253The phy side driver strength support value as follows: 254+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 255| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 256+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 257| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | | 258| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | | 259| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | X | 260| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | | 261| | 20 | 21 | | 25,24,23,22 | | | | 262+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 263| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | | 264| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | | 265| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 266| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 267| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 268| | | | | | 28 | 23 | | 269+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 270| RK3588 | X | X | X | 240,120,80,60, | follow LP4 | follow LP4 | follow LP4 | 271| | | | | 48,40,34,30 | | | | 272+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 273| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 585,297,202, | 585,297,202, | | 274| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 150,122,103,90,| | 275| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43,| follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 276| | 38,36,34,33,31,30,| 39,37,35,34,32,31,| | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 277| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 278| | | | | | 30 | 30 | | 279+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 280 281The DRAM side driver strength support value as follows: 282+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 283| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | LP5 | 284+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 285| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | follow LP4 | 286+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 287 288* ODT 289phy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm. 290ddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm. 291phy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable 292phy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable 293phy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz. 294ddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz. 295 296The phy side ODT support value as follows: 297The ODT "0" means disabled ODT. 298+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 299| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 300+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 301| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | | 302| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | | 303| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | X | 304| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | | 305| | 28,27,25 | 27 | | 29,27 | | | | 306+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 307| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | | 308| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | | 309| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 310| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 311| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 312| | | | | | 28 | 23 | | 313+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 314| RK3588 | X | X | X | 0,240,120,80, | follow LP4 | follow LP4 | follow LP4 | 315| | | | | 60,48,40,34,30 | | | | 316+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 317| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 585,297,202, | 585,297,202, | | 318| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 150,122,103,90,| | 319| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43, | follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 320| | 38,36,34,33,31,30,| 39,37,35,34,32,31, | | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 321| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 322| | | | | | 30 | 30 | | 323+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 324The DRAM side ODT support value as follows: 325+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 326| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | LP5 | 327+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 328| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | follow LP4 | 329+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 330 331* slew rate 332 333phy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on. 334phy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on. 335phy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on. 336phy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off. 337phy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off. 338phy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off. 339 340The max value is 0x1f, the min is 0x0. 341 342* byte map 343 344ddr*_bytes_map: The bytes remap in PHY. 345 346* dq remap 347 348lp*_dq*_*_map: The dq remap in PHY. 349ddr*_cs*_dq*_dq*_map: The dq remap in PHY. 350 351* lp4/lp4x more information 352 353lp4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz. 354phy_lp4*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand. 355lp4*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand. 356lp4*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand. 357phy_lp4_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand. 358lp4_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand. 359lp4_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand. 360 361* hash info 362ch/bank/rank_mask*: is used to DDR address hash mask. 363