186251429SZhihuan Hefunction 1: modify ddr.bin file from ddrbin_param.txt. 2612e733eSZhihuan He 1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want. 386251429SZhihuan He If want to keep items default, please keep these items blank. 4612e733eSZhihuan He 2) run 'ddrbin_tool' with argument 1: ddrbin_param.txt, argument 2: ddr bin file. 554a17cb1STang Yun ping like: ./ddrbin_tool ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 6612e733eSZhihuan He 786251429SZhihuan Hefunction 2: get ddr.bin file config to gen_param.txt file 886251429SZhihuan He If want to get ddrbin file config, please run like that: 986251429SZhihuan He ./ddrbin_tool -g gen_param.txt px30_ddr_333MHz_v1.15.bin 1086251429SZhihuan He The config will show in gen_param.txt. 1154a17cb1STang Yun ping 1286251429SZhihuan HeThe detail information as following: 1354a17cb1STang Yun ping 1486251429SZhihuan He* support ddrbin version 156f34a9d1SZhihuan He The 'X' means not support change those parameters by tool. 166f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 176f34a9d1SZhihuan He | platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT | 186f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 196f34a9d1SZhihuan He | RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X | 206f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 216f34a9d1SZhihuan He | PX30/RK3326 | V1.11 | X | V1.16 | V1.12 | V1.15 | X | X | X | 226f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 236f34a9d1SZhihuan He | RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | 246f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 256f34a9d1SZhihuan He | RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | 266f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 276f34a9d1SZhihuan He | RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | 286f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 296f34a9d1SZhihuan He | RK3288 | V1.11 | X | X | V1.11 | X | X | X | X | 306f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 316f34a9d1SZhihuan He | RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X | 326f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 336f34a9d1SZhihuan He | RK3308S | V2.05 | V2.05 | V2.05 | V2.05 | V2.05 | X | X | X | 346f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 356f34a9d1SZhihuan He | RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | 366f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 376f34a9d1SZhihuan He | RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | 386f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 396f34a9d1SZhihuan He | RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | 406f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 416f34a9d1SZhihuan He | RK3399PRO NPU | V1.03 | V1.03 | X | V1.03 | X | X | X | X | 426f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 436f34a9d1SZhihuan He | RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | 446f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 456f34a9d1SZhihuan He | RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | 466f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 476f34a9d1SZhihuan He | RK3588 | V1.00 | V1.00 | X | V1.00 | V1.00 | V1.00 | X | X | 486f34a9d1SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 496f34a9d1SZhihuan He 506f34a9d1SZhihuan He| function | platform and ddrbin version | 516f34a9d1SZhihuan He| ------------------------------- | -------------------------------------- | 526f34a9d1SZhihuan He| first scan channel/channel mask | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 536f34a9d1SZhihuan He| stride type | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 54*1c9962b9SYouMin Chen| ext_temp_ref | Null | 556f34a9d1SZhihuan He| link_ecc_en | Null | 566f34a9d1SZhihuan He| per_bank_ref_en | RK3588 V1.09 | 576f34a9d1SZhihuan He| derate_en | RK3588 V1.09 | 586f34a9d1SZhihuan He| auto_precharge_en | Null | 596f34a9d1SZhihuan He| res_space_remap_portion | RK3588 V1.09 | 606f34a9d1SZhihuan He| res_space_remap_all | RK3588 V1.09 | 616f34a9d1SZhihuan He| rd_vref_scan_en | RK3588 V1.08 | 626f34a9d1SZhihuan He| wr_vref_scan_en | RK3588 V1.08 | 636f34a9d1SZhihuan He| eye_2d_scan_en | RK3588 V1.08 | 646f34a9d1SZhihuan He| ch/bank/rank_mask | RK3588 V1.00 | 656f34a9d1SZhihuan He| pstore base_addr/buf_size | RK3588 V1.09 | 666f34a9d1SZhihuan He| uboot/atf/optee/spl/tpl log en | RK3588 V1.09 | 676f34a9d1SZhihuan He| boot_fsp | RK3588 V1.09 | 689c25957fSYouMin Chen| pageclose | RK3588 V1.10 | 6986251429SZhihuan He 7086251429SZhihuan He* UART info 7186251429SZhihuan He 7286251429SZhihuan Heuart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 7386251429SZhihuan Heuart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 7486251429SZhihuan Heor 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 7586251429SZhihuan Heuart baudrate: uart baudrate should be 115200 or 1500000. 7686251429SZhihuan He 7786251429SZhihuan He* disable print training information 7886251429SZhihuan He 796f34a9d1SZhihuan Hedis_train_print: 1: will disabled print training information; 0: will enable print training information. 8086251429SZhihuan He 816f34a9d1SZhihuan He* recycle registers space(remap register space to DDR) 8286251429SZhihuan He 836f34a9d1SZhihuan Heres_space_remap_portion 846f34a9d1SZhihuan He1: will remap the part of registers to DDR memory space(will not larger than 4GB). 856f34a9d1SZhihuan HeIt is PCIE and some reserved space in RK3588, and the PCIE can not be used when set to 1. 866f34a9d1SZhihuan He 876f34a9d1SZhihuan Heres_space_remap_all 886f34a9d1SZhihuan He1: will wrap all registers space(include res_space_remap_portion enable space) to DDR memory space. This space would be place in larger than 4GB. 896f34a9d1SZhihuan HeThe PCIE can be used when set to 1 in RK3588. 90612e733eSZhihuan He 91612e733eSZhihuan He* DDR eye scanning 92612e733eSZhihuan He1) eye_2d_scan_en: 1: will enable 2D eye scanning for debug purpose, vref and skew eye scanning. 93612e733eSZhihuan He2) wr_vref_scan_en: 1: enable vref scan and use scanning result for write. 94612e733eSZhihuan He3) rd_vref_scan_en: 1: enable vref scan and use scanning result for read. 9586251429SZhihuan He 966f34a9d1SZhihuan He* DDR auto precharge 976f34a9d1SZhihuan He 986f34a9d1SZhihuan Heauto_precharge_en: 1: will enable the DDR auto precharge. 996f34a9d1SZhihuan He 1006f34a9d1SZhihuan He* DDR refresh derate 1016f34a9d1SZhihuan He 1026f34a9d1SZhihuan Hederate_en: 1: will enable derate function of the LP2/LP3/LP4/LP4X/LP5. 1036f34a9d1SZhihuan HeThe high temperature will issue more refresh command and the low temperature will less. 1046f34a9d1SZhihuan He 1056f34a9d1SZhihuan He* DDR per bank refresh 1066f34a9d1SZhihuan He 1076f34a9d1SZhihuan Heper_bank_ref_en: 1: will enable per bank refresh 1086f34a9d1SZhihuan He 1096f34a9d1SZhihuan He* link ECC enable 1106f34a9d1SZhihuan He 1116f34a9d1SZhihuan Helink_ecc_en: 1: read/write link ecc enable. 1126f34a9d1SZhihuan He 1136f34a9d1SZhihuan He* Extended temperature refresh 1146f34a9d1SZhihuan He 115*1c9962b9SYouMin Chenext_temp_ref: 116*1c9962b9SYouMin Chen 0: ref1x for normal chip, 2x for 3568M/3568J 117*1c9962b9SYouMin Chen 1: fix 2x ref for all chip 118*1c9962b9SYouMin Chen 2: fix 4x ref for all chip 119*1c9962b9SYouMin Chen 3: fix 1x ref for all chip 120*1c9962b9SYouMin ChenNote: If derate-enabled DDR are configured with derate_en=1, the ext_temp_ref configuration does not take effect. 1216f34a9d1SZhihuan He 1226f34a9d1SZhihuan He* pstore_base_addr pstore_buf_size 1236f34a9d1SZhihuan HeThe pstore buffer base address: pstore_base_addr << 16, 64kB align. 1246f34a9d1SZhihuan HeThe pstore buffer size: pstore_buf_size * 4KB. 1256f34a9d1SZhihuan HeIt is define the addr and size to save ddrbin log for last log. 1266f34a9d1SZhihuan He 1276f34a9d1SZhihuan He* uboot_log_en 1286f34a9d1SZhihuan He1: enable uboot log. 1296f34a9d1SZhihuan He0: disable uboot log. 1306f34a9d1SZhihuan He 1316f34a9d1SZhihuan He* atf_log_en 1326f34a9d1SZhihuan He1: enable atf log. 1336f34a9d1SZhihuan He0: disable atf log. 1346f34a9d1SZhihuan He 1356f34a9d1SZhihuan He* optee_log_en 1366f34a9d1SZhihuan He1: enable optee log. 1376f34a9d1SZhihuan He0: disable optee log. 1386f34a9d1SZhihuan He 1396f34a9d1SZhihuan He* spl_log_en 1406f34a9d1SZhihuan He1: enable spl log. 1416f34a9d1SZhihuan He0: disable spl log. 1426f34a9d1SZhihuan He 1436f34a9d1SZhihuan He* tpl_log_en 1446f34a9d1SZhihuan He1: enable tpl log. 1456f34a9d1SZhihuan He0: disable tpl log. 1466f34a9d1SZhihuan He 1479c25957fSYouMin Chen* pageclose 1489c25957fSYouMin Chen1: enable pageclose. 1499c25957fSYouMin Chen0: disable pageclose. 1509c25957fSYouMin Chen 1516f34a9d1SZhihuan He* boot_fsp 1526f34a9d1SZhihuan HeTo choose the which DDR freq to boot system. 0 means fsp0_freq, 1 means fsp1_freq, 2 means fsp2_freq, 3 means fsp3_freq, the default is 0. 1536f34a9d1SZhihuan He 1546f34a9d1SZhihuan He* DDR (final) freq(also called ddrx_f0_freq_mhz/fsp0_freq) 1556f34a9d1SZhihuan He 1566f34a9d1SZhihuan HeFor RK3588, the boot_fsp used to choose which ddrx_fx_freq_mhz/fspx_freq to boot system, default is ddrx_f0_freq_mhz/fsp0_freq. 1576f34a9d1SZhihuan HeFor the others platform, it is the final freq to boot system. 15886251429SZhihuan He 159d42b646fSZhihuan Heddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz. 160d42b646fSZhihuan Help2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz. 161d42b646fSZhihuan Heddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz. 162d42b646fSZhihuan Help3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz. 163d42b646fSZhihuan Heddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz. 164d42b646fSZhihuan Help4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz. 165d42b646fSZhihuan Help4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz. 166d42b646fSZhihuan Help5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz. 16754a17cb1STang Yun ping 1686f34a9d1SZhihuan He* support ddr frequency: 1696f34a9d1SZhihuan HeThe 'X' as follows means not support change frequencies by tool. 1706f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 1716f34a9d1SZhihuan He| platform | support frequencies(MHZ) | 1726f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 1736f34a9d1SZhihuan He| RK1108 | DDR2: 400; LP2: <= 533; DDR3: <= 800 | 1746f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 17586251429SZhihuan He| PX30/RK3326 | X | 1766f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 17786251429SZhihuan He| RK1808 | 333,400,533,666,786,933 | 1786f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 1796f34a9d1SZhihuan He| RK322x | DDR2/LP2: <= 533; others: <= 800 | 1806f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 18186251429SZhihuan He| RK322xh | X | 1826f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 18386251429SZhihuan He| RK3288 | X | 1846f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 1856f34a9d1SZhihuan He| RK3308/RK3308S| DDR2/LP2: 393,451; DDR3: 393,451,589 | 1866f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 1876f34a9d1SZhihuan He| RK3368 | DDR3: <= 800; LP3: <= 666 | 1886f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 18986251429SZhihuan He| RK3328 | X | 1906f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 19186251429SZhihuan He| RK3399 | X | 1926f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 19386251429SZhihuan He| RK3399PRO NPU | 333,400,533,666,786,933 | 1946f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 19586251429SZhihuan He| RV1126/RV1109 | 328,396,528,664,784,924,1056 | 1966f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 1976f34a9d1SZhihuan He| RK3566 | 324,396,528,630,780,920,1056 | 1986f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 1996f34a9d1SZhihuan He| RK3568 | DDR3/LP3: 324,396,528,630,780,920,1056 | 2006f34a9d1SZhihuan He| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184,1332,1560 | 2016f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 2028edfcbeaSZhihuan He| RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] | 2036f34a9d1SZhihuan He+---------------+-----------------------------------------------------------------+ 204f90d99fcSZhihuan He| RK3528 | DDR3/LP3: 324,396,528,630,780,920,1056 | 205f90d99fcSZhihuan He| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184 | 206f90d99fcSZhihuan He+---------------+-----------------------------------------------------------------+ 207558a25b2STang Yun ping 20886251429SZhihuan He* DDR frequencies(add more) 209eea48410SZhihuan He 2106f34a9d1SZhihuan Heddr2_f1_freq_mhz: ddr2 frequency fsp 1, unit:MHz. 2116f34a9d1SZhihuan Heddr2_f2_freq_mhz: ddr2 frequency fsp 2, unit:MHz. 2126f34a9d1SZhihuan Heddr2_f3_freq_mhz: ddr2 frequency fsp 3, unit:MHz. 2136f34a9d1SZhihuan Heddr2_f4_freq_mhz: ddr2 frequency fsp 4, unit:MHz. 2146f34a9d1SZhihuan Heddr2_f5_freq_mhz: ddr2 frequency fsp 5, unit:MHz. 21572640b4bSZhihuan He... 2166f34a9d1SZhihuan HeThe ddrx_f0_freq_mhz(the fsp0 frequency) is named ddrx_freq. 21786251429SZhihuan He 218612e733eSZhihuan Heddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used. 2198edfcbeaSZhihuan HeThe program will initialize dram by following order. 22086251429SZhihuan Hefor example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq. 221612e733eSZhihuan HeAnd the final frequency is ddr4_freq to boot system. 222612e733eSZhihuan HeThe ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 22386251429SZhihuan HeSo it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'. 224612e733eSZhihuan HeSuch as: ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq) 22586251429SZhihuan HeFor example: 22686251429SZhihuan He ... 22786251429SZhihuan He ddr4_freq=1560 22886251429SZhihuan He ... 22986251429SZhihuan He ddr4_f1_freq_mhz=324 23086251429SZhihuan He ddr4_f2_freq_mhz=528 23186251429SZhihuan He ddr4_f3_freq_mhz=780 23286251429SZhihuan He ... 23386251429SZhihuan He 2346f34a9d1SZhihuan HeNote: The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 2356f34a9d1SZhihuan He 23686251429SZhihuan He* SR PD idle 23786251429SZhihuan He 23886251429SZhihuan Hesr_idle: auto self-refresh mode delay time. 23986251429SZhihuan Hepd_idle: auto power-down mode delay time. 24086251429SZhihuan He 24186251429SZhihuan He* DDR 2T 24286251429SZhihuan He 24386251429SZhihuan Heddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 24486251429SZhihuan He 24586251429SZhihuan He* PLL ssmod 24686251429SZhihuan He 2473e8d76b8SZhihuan HeThese parameters are about Spread Spectrum Modulator(ssmod) for PLL. 248f90d99fcSZhihuan Hessmod_downspread: ssmod work mode. 1: down spread, 0: center spread. 249612e733eSZhihuan Hessmod_div: Divider required to set the modulation frequency. RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5. 2503e8d76b8SZhihuan Hessmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f. 25186251429SZhihuan He 25286251429SZhihuan He* driver strength 25386251429SZhihuan He 25486251429SZhihuan Hephy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm. 25586251429SZhihuan Hephy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm. 25686251429SZhihuan Hephy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm. 25786251429SZhihuan Heddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm. 25886251429SZhihuan Hephy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm. 25986251429SZhihuan Hephy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm. 26086251429SZhihuan Hephy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm. 26186251429SZhihuan Heddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm. 26286251429SZhihuan He 26386251429SZhihuan HeThe phy side driver strength support value as follows: 264612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 265612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 266612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 267612e733eSZhihuan He| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | | 268612e733eSZhihuan He| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | | 269612e733eSZhihuan He| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | X | 270612e733eSZhihuan He| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | | 271612e733eSZhihuan He| | 20 | 21 | | 25,24,23,22 | | | | 272612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 273612e733eSZhihuan He| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | | 274612e733eSZhihuan He| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | | 275612e733eSZhihuan He| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 276612e733eSZhihuan He| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 277612e733eSZhihuan He| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 278612e733eSZhihuan He| | | | | | 28 | 23 | | 279612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 280612e733eSZhihuan He| RK3588 | X | X | X | 240,120,80,60, | follow LP4 | follow LP4 | follow LP4 | 281612e733eSZhihuan He| | | | | 48,40,34,30 | | | | 282612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 283f90d99fcSZhihuan He| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 585,297,202, | 585,297,202, | | 284f90d99fcSZhihuan He| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 150,122,103,90,| | 285f90d99fcSZhihuan He| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43,| follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 286f90d99fcSZhihuan He| | 38,36,34,33,31,30,| 39,37,35,34,32,31,| | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 287f90d99fcSZhihuan He| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 288f90d99fcSZhihuan He| | | | | | 30 | 30 | | 289f90d99fcSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 29086251429SZhihuan He 29186251429SZhihuan HeThe DRAM side driver strength support value as follows: 292612e733eSZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 293612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | LP5 | 294612e733eSZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 295612e733eSZhihuan He| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | follow LP4 | 296612e733eSZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 29786251429SZhihuan He 29886251429SZhihuan He* ODT 29986251429SZhihuan Hephy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm. 30086251429SZhihuan Heddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm. 30186251429SZhihuan Hephy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable 30286251429SZhihuan Hephy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable 30386251429SZhihuan Hephy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz. 30486251429SZhihuan Heddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz. 30586251429SZhihuan He 30686251429SZhihuan HeThe phy side ODT support value as follows: 30786251429SZhihuan HeThe ODT "0" means disabled ODT. 308612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 309612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 310612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 311612e733eSZhihuan He| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | | 312612e733eSZhihuan He| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | | 313612e733eSZhihuan He| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | X | 314612e733eSZhihuan He| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | | 315612e733eSZhihuan He| | 28,27,25 | 27 | | 29,27 | | | | 316612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 317612e733eSZhihuan He| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | | 318612e733eSZhihuan He| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | | 319612e733eSZhihuan He| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 320612e733eSZhihuan He| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 321612e733eSZhihuan He| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 322612e733eSZhihuan He| | | | | | 28 | 23 | | 323612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 324612e733eSZhihuan He| RK3588 | X | X | X | 0,240,120,80, | follow LP4 | follow LP4 | follow LP4 | 325612e733eSZhihuan He| | | | | 60,48,40,34,30 | | | | 326612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 327f90d99fcSZhihuan He| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 585,297,202, | 585,297,202, | | 328f90d99fcSZhihuan He| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 150,122,103,90,| | 329f90d99fcSZhihuan He| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43, | follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 330f90d99fcSZhihuan He| | 38,36,34,33,31,30,| 39,37,35,34,32,31, | | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 331f90d99fcSZhihuan He| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 332f90d99fcSZhihuan He| | | | | | 30 | 30 | | 333f90d99fcSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 33486251429SZhihuan HeThe DRAM side ODT support value as follows: 335612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 336612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | LP5 | 337612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 338612e733eSZhihuan He| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | follow LP4 | 339612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 34086251429SZhihuan He 34186251429SZhihuan He* slew rate 34286251429SZhihuan He 34386251429SZhihuan Hephy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on. 34486251429SZhihuan Hephy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on. 34586251429SZhihuan Hephy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on. 34686251429SZhihuan Hephy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off. 34786251429SZhihuan Hephy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off. 34886251429SZhihuan Hephy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off. 34986251429SZhihuan He 350612e733eSZhihuan HeThe max value is 0x1f, the min is 0x0. 351612e733eSZhihuan He 35286251429SZhihuan He* byte map 35386251429SZhihuan He 354612e733eSZhihuan Heddr*_bytes_map: The bytes remap in PHY. 35586251429SZhihuan He 35686251429SZhihuan He* dq remap 35786251429SZhihuan He 358612e733eSZhihuan Help*_dq*_*_map: The dq remap in PHY. 359612e733eSZhihuan Heddr*_cs*_dq*_dq*_map: The dq remap in PHY. 36086251429SZhihuan He 36186251429SZhihuan He* lp4/lp4x more information 36286251429SZhihuan He 36386251429SZhihuan Help4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz. 36486251429SZhihuan Hephy_lp4*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand. 36586251429SZhihuan Help4*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand. 36686251429SZhihuan Help4*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand. 36786251429SZhihuan Hephy_lp4_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand. 36886251429SZhihuan Help4_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand. 36986251429SZhihuan Help4_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand. 3708edfcbeaSZhihuan He 3718edfcbeaSZhihuan He* hash info 3728edfcbeaSZhihuan Hech/bank/rank_mask*: is used to DDR address hash mask. 373