xref: /rkbin/tools/ddrbin_tool.py (revision fc577f4fbf4840abd121fccc2c1b968402bca641) 
1#!/usr/bin/env python3
2# -*-coding=utf-8-*-
3#
4# Copyright (C) 2024, Rockchip Electronics Co., Ltd.
5#
6
7import os
8import re
9import sys
10import copy
11import getopt
12import platform
13import struct
14from datetime import datetime
15
16version_max = 5
17update_key_list = []
18
19chip_info = 'null'
20chip_list = ['px30', 'px30s', 'px3se', 'px5', 'rk1808', 'rk2118', 'rk312x', 'rk3126', 'rk3128',
21    'rk3128h', 'rk322x', 'rk3228a', 'rk3228b', 'rk3228h', 'rk322xh', 'rk3229', 'rk3308', 'rk3288',
22    'rk3326', 'rk3326s', 'rk3328', 'rk3368', 'rk3399', 'rk3506', 'rk3528', 'rk356x', 'rk3562',
23    'rk3566', 'rk3568', 'rk3576', 'rk3588', 'rv1103', 'rv1103b', 'rv1106', 'rv1108', 'rv1109',
24    'rv1126']
25
26version_old_list = ['rk322xh', 'rk3328', 'rk3318']
27
28# struct rk3528_ca_skew
29rk3528_ca_skew = {
30    'skew_freq': 0,
31    'ca_skew_0': 0,
32    'ca_skew_1': 0,
33    'ca_skew_2': 0,
34    'ca_skew_3': 0,
35    'ca_skew_4': 0,
36    'ca_skew_5': 0,
37    'ca_skew_6': 0,
38    'ca_skew_7': 0,
39}
40
41# struct rk3528_skew_info
42rk3528_skew_info = {
43    'skew_sub_version': 0,
44    'ddr3' : rk3528_ca_skew.copy(),
45    'ddr4' : rk3528_ca_skew.copy(),
46    'lp3' : rk3528_ca_skew.copy(),
47}
48
49# struct index_info, u8
50index_info = {
51    'offset' : 0,
52    'size' : 0
53}
54
55# struct sdram_head_info_index_v2
56sdram_head_info_index_v2 = {
57    'cpu_gen_index' : index_info.copy(),
58    'global_index' : index_info.copy(),
59    'ddr2_index' : index_info.copy(),
60    'ddr3_index' : index_info.copy(),
61    'ddr4_index' : index_info.copy(),
62    'ddr5_index' : index_info.copy(),
63    'lp2_index' : index_info.copy(),
64    'lp3_index' : index_info.copy(),
65    'lp4_index' : index_info.copy(),
66    'lp5_index' : index_info.copy(),
67    'skew_index' : index_info.copy(),
68    'dq_map_index' : index_info.copy(),
69}
70
71sdram_head_info_index_v2_3 = {
72    'lp4x_index' : index_info.copy(),
73    'lp4_4x_hash_index' : index_info.copy()
74}
75
76sdram_head_info_index_v3_4 = {
77    'lp5_hash_index' : index_info.copy(),
78    'ddr4_hash_index' : index_info.copy(),
79    'lp3_hash_index' : index_info.copy(),
80    'ddr3_hash_index' : index_info.copy(),
81    'lp2_hash_index' : index_info.copy(),
82    'ddr2_hash_index' : index_info.copy(),
83    'ddr5_hash_index' : index_info.copy(),
84}
85
86# struct global_info
87global_info = {
88    'uart_info' : 0,
89    'sr_pd_info' : 0,
90    'ch_info' : 0,
91    'info_2t' : 0,
92    'reserved_0' : 0,
93    'reserved_1' : 0,
94    'reserved_2' : 0,
95    'reserved_3' : 0,
96}
97
98# struct ddr2_3_4_lp2_3_info
99ddr2_3_4_lp2_3_info = {
100    'ddr_freq0_1' : 0,
101    'ddr_freq2_3' : 0,
102    'ddr_freq4_5' : 0,
103    'drv_when_odten' : 0,
104    'drv_when_odtoff' : 0,
105    'odt_info' : 0,
106    'odten_freq' : 0,
107    'sr_when_odten' : 0,
108    'sr_when_odtoff' : 0,
109}
110
111# struct ddr2_3_4_lp2_3_info_v5
112ddr2_3_4_lp2_3_info_v5 = {
113    'ddr_freq0_1' : 0,
114    'ddr_freq2_3' : 0,
115    'ddr_freq4_5' : 0,
116    'drv_when_odten' : 0,
117    'drv_when_odtoff' : 0,
118    'odt_info' : 0,
119    'odten_freq' : 0,
120    'sr_when_odten' : 0,
121    'sr_when_odtoff' : 0,
122    'vref_when_odten' : 0,
123    'vref_when_odtoff' : 0,
124}
125
126# struct lp4_info
127lp4_info = {
128    'ddr_freq0_1' : 0,
129    'ddr_freq2_3' : 0,
130    'ddr_freq4_5' : 0,
131    'drv_when_odten' : 0,
132    'drv_when_odtoff' : 0,
133    'odt_info' : 0,
134    'dq_odten_freq' : 0,
135    'sr_when_odten' : 0,
136    'sr_when_odtoff' : 0,
137    'ca_odten_freq' : 0,
138    'cs_drv_ca_odt_info' : 0,
139    'vref_when_odten' : 0,
140    'vref_when_odtoff' : 0,
141}
142
143# struct dq_map_info
144dq_map_info = {
145    'byte_map_0' : 0,
146    'byte_map_1' : 0,
147    'lp3_dq0_7_map' : 0,
148    'lp2_dq0_7_map' : 0,
149    'ddr4_dq_map_0' : 0,
150    'ddr4_dq_map_1' : 0,
151    'ddr4_dq_map_2' : 0,
152    'ddr4_dq_map_3' : 0,
153}
154
155# struct hash_info
156hash_info = {
157    'ch_mask_0' : 0,
158    'ch_mask_1' : 0,
159    'bank_mask_0' : 0,
160    'bank_mask_1' : 0,
161    'bank_mask_2' : 0,
162    'bank_mask_3' : 0,
163    'rank_mask0' : 0,
164    'rank_mask1' : 0,
165}
166
167# struct sdram_head_info_v2
168sdram_head_info_v2 = {
169    'global_info' : global_info.copy(),
170    'ddr2_info' : ddr2_3_4_lp2_3_info.copy(),
171    'ddr3_info' : ddr2_3_4_lp2_3_info.copy(),
172    'ddr4_info' : ddr2_3_4_lp2_3_info.copy(),
173    'ddr5_info' : ddr2_3_4_lp2_3_info.copy(),
174    'lp2_info' : ddr2_3_4_lp2_3_info.copy(),
175    'lp3_info' : ddr2_3_4_lp2_3_info.copy(),
176    'lp4_info' : lp4_info.copy(),
177    'dq_map_info' : dq_map_info.copy(),
178    'lp4x_info' : lp4_info.copy(),
179    'lp5_info' : lp4_info.copy(),
180    'lp4_4x_hash_info' : hash_info.copy(),
181    'lp5_hash_info' : hash_info.copy(),
182    'ddr4_hash_info' : hash_info.copy(),
183    'lp3_hash_info' : hash_info.copy(),
184    'ddr3_hash_info' : hash_info.copy(),
185    'lp2_hash_info' : hash_info.copy(),
186    'ddr2_hash_info' : hash_info.copy(),
187    'ddr5_hash_info' : hash_info.copy(),
188}
189
190# struct sdram_head_info_v5
191sdram_head_info_v5 = {
192    'global_info' : global_info.copy(),
193    'ddr2_info' : ddr2_3_4_lp2_3_info_v5.copy(),
194    'ddr3_info' : ddr2_3_4_lp2_3_info_v5.copy(),
195    'ddr4_info' : ddr2_3_4_lp2_3_info_v5.copy(),
196    'ddr5_info' : ddr2_3_4_lp2_3_info_v5.copy(),
197    'lp2_info' : ddr2_3_4_lp2_3_info_v5.copy(),
198    'lp3_info' : ddr2_3_4_lp2_3_info_v5.copy(),
199    'lp4_info' : lp4_info.copy(),
200    'dq_map_info' : dq_map_info.copy(),
201    'lp4x_info' : lp4_info.copy(),
202    'lp5_info' : lp4_info.copy(),
203    'lp4_4x_hash_info' : hash_info.copy(),
204    'lp5_hash_info' : hash_info.copy(),
205    'ddr4_hash_info' : hash_info.copy(),
206    'lp3_hash_info' : hash_info.copy(),
207    'ddr3_hash_info' : hash_info.copy(),
208    'lp2_hash_info' : hash_info.copy(),
209    'ddr2_hash_info' : hash_info.copy(),
210    'ddr5_hash_info' : hash_info.copy(),
211}
212
213sdram_head_info_v0 = [[0xc, 0], [0x10, 0], [0x14, 0], [0x18, 0], [0x1c, 0], [0x20, 0], [0x24, 0]]
214
215# struct base_info_full
216base_info_full = {
217    'start tag': {'value': 0, 'num_base': 'hex', 'index': 'null', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 0, 'v0_info': [0x0, 0, 0xffffffff]},
218
219    'ddr2_freq': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'ddr_freq0_1', 'shift': 0, 'mask': 0xfff, 'version': 0, 'v0_info': [0xc, 16, 0xffff]},
220    'lp2_freq': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'ddr_freq0_1', 'shift': 0, 'mask': 0xfff, 'version': 0, 'v0_info': [0xc, 0, 0xffff]},
221    'ddr3_freq': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'ddr_freq0_1', 'shift': 0, 'mask': 0xfff, 'version': 0, 'v0_info': [0x10, 16, 0xffff]},
222    'lp3_freq': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'ddr_freq0_1', 'shift': 0, 'mask': 0xfff, 'version': 0, 'v0_info': [0x10, 0, 0xffff]},
223    'ddr4_freq': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'ddr_freq0_1', 'shift': 0, 'mask': 0xfff, 'version': 0, 'v0_info': [0x14, 16, 0xffff]},
224    'lp4_freq': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ddr_freq0_1', 'shift': 0, 'mask': 0xfff, 'version': 0, 'v0_info': [0x14, 0, 0xffff]},
225    'lp4x_freq': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ddr_freq0_1', 'shift': 0, 'mask': 0xfff, 'version': 2},
226    'lp5_freq': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ddr_freq0_1', 'shift': 0, 'mask': 0xfff, 'version': 2},
227    'uart id': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'uart_info', 'shift': 28, 'mask': 0xf, 'version': 0, 'v0_info': [0x18, 28, 0xf]},
228    'uart iomux': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'uart_info', 'shift': 24, 'mask': 0xf, 'version': 0, 'v0_info': [0x18, 24, 0xf]},
229    'uart baudrate': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'uart_info', 'shift': 0, 'mask': 0xffffff, 'version': 0, 'v0_info': [0x18, 0, 0xffffff]},
230    'sr_idle': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'sr_pd_info', 'shift': 16, 'mask': 0xffff, 'version': 0, 'v0_info': [0x1c, 16, 0xffff]},
231    'pd_idle': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'sr_pd_info', 'shift': 0, 'mask': 0xffff, 'version': 0, 'v0_info': [0x1c, 0, 0xffff]},
232    'first scan channel': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'ch_info', 'shift': 28, 'mask': 0xf, 'version': 0, 'v0_info': [0x20, 28, 0xf]},
233    'channel mask': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'ch_info', 'shift': 24, 'mask': 0xf, 'version': 0, 'v0_info': [0x20, 24, 0xf]},
234    'stride type': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'ch_info', 'shift': 16, 'mask': 0xff, 'version': 0, 'v0_info': [0x20, 16, 0xff]},
235    'standby_idle': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'ch_info', 'shift': 0, 'mask': 0xffff, 'version': 0, 'v0_info': [0x20, 0, 0xffff]},
236    'ext_temp_ref': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 29, 'mask': 0x3, 'version': 0, 'v0_info': [0x24, 29, 0x3]},
237    'link_ecc_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 28, 'mask': 0x1, 'version': 2},
238    'per_bank_ref_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 27, 'mask': 0x1, 'version': 2},
239    'derate_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 26, 'mask': 0x1, 'version': 0, 'v0_info': [0x24, 26, 0x1]},
240    'auto_precharge_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 25, 'mask': 0x1, 'version': 2},
241    'res_space_remap_all': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 24, 'mask': 0x1, 'version': 2},
242    'res_space_remap_portion': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 20, 'mask': 0x1, 'version': 2},
243    'rd_vref_scan_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 21, 'mask': 0x1, 'version': 2},
244    'wr_vref_scan_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 22, 'mask': 0x1, 'version': 2},
245    'eye_2d_scan_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 23, 'mask': 0x1, 'version': 2},
246    'dis_train_print': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 19, 'mask': 0x1, 'version': 2},
247    'ssmod_downspread': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 17, 'mask': 0x3, 'version': 0, 'v0_info': [0x24, 17, 0x3]},
248    'ssmod_div': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 9, 'mask': 0xff, 'version': 0, 'v0_info': [0x24, 9, 0xff]},
249    'ssmod_spread': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 1, 'mask': 0xff, 'version': 0, 'v0_info': [0x24, 1, 0xff]},
250    'ddr_2t': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 0, 'mask': 0x1, 'version': 0, 'v0_info': [0x24, 0, 0x1]},
251    'reserved_global_info_2t_bit31': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'info_2t', 'shift': 31, 'mask': 0x1, 'version': 2},
252    'pstore_base_addr': {'value': 0, 'num_base': 'hex', 'index': 'global_index', 'position': 'reserved_0', 'shift': 16, 'mask': 0xffff, 'version': 2},
253    'pstore_buf_size': {'value': 0, 'num_base': 'hex', 'index': 'global_index', 'position': 'reserved_0', 'shift': 12, 'mask': 0xf, 'version': 2},
254    'uboot_log_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_0', 'shift': 4, 'mask': 0x1, 'version': 2},
255    'atf_log_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_0', 'shift': 3, 'mask': 0x1, 'version': 2},
256    'optee_log_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_0', 'shift': 2, 'mask': 0x1, 'version': 2},
257    'spl_log_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_0', 'shift': 1, 'mask': 0x1, 'version': 2},
258    'tpl_log_en': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_0', 'shift': 0, 'mask': 0x1, 'version': 2},
259    'reserved_global_reserved_0_bit5_11': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_0', 'shift': 5, 'mask': 0x7f, 'version': 2},
260    'first_init_dram_type': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_1', 'shift': 5, 'mask': 0xf, 'version': 2},
261    'dfs_disable': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_1', 'shift': 4, 'mask': 0x1, 'version': 2},
262    'pageclose': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_1', 'shift': 3, 'mask': 0x1, 'version': 2},
263    'boot_fsp': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_1', 'shift': 0, 'mask': 0x7, 'version': 2},
264    'reserved_global_reserved_1_bit9_31': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_1', 'shift': 9, 'mask': 0x7fffff, 'version': 2},
265    'reserved_global_reserved_2_bit0_31': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_2', 'shift': 0, 'mask': 0xffffffff, 'version': 2},
266    'reserved_global_reserved_3_bit0_31': {'value': 0, 'num_base': 'dec', 'index': 'global_index', 'position': 'reserved_3', 'shift': 0, 'mask': 0xffffffff, 'version': 2},
267
268    'ddr2_f1_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'ddr_freq0_1', 'shift': 12, 'mask': 0xfff, 'version': 2},
269    'reserved_ddr2_ddr_freq0_1_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'ddr_freq0_1', 'shift': 24, 'mask': 0xff, 'version': 2},
270    'ddr2_f2_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'ddr_freq2_3', 'shift': 0, 'mask': 0xfff, 'version': 2},
271    'ddr2_f3_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'ddr_freq2_3', 'shift': 12, 'mask': 0xfff, 'version': 2},
272    'reserved_ddr2_ddr_freq2_3_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'ddr_freq2_3', 'shift': 24, 'mask': 0xff, 'version': 2},
273    'ddr2_f4_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'ddr_freq4_5', 'shift': 0, 'mask': 0xfff, 'version': 2},
274    'ddr2_f5_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'ddr_freq4_5', 'shift': 12, 'mask': 0xfff, 'version': 2},
275    'reserved_ddr2_ddr_freq4_5_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'ddr_freq4_5', 'shift': 24, 'mask': 0xff, 'version': 2},
276    'phy_ddr2_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'drv_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
277    'phy_ddr2_ca_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'drv_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
278    'phy_ddr2_clk_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'drv_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
279    'ddr2_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'drv_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
280    'phy_ddr2_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'drv_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
281    'phy_ddr2_ca_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'drv_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
282    'phy_ddr2_clk_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'drv_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
283    'ddr2_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'drv_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
284    'phy_ddr2_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'odt_info', 'shift': 8, 'mask': 0x3ff, 'version': 2},
285    'ddr2_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
286    'phy_ddr2_odt_pull_up_en': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'odt_info', 'shift': 18, 'mask': 0x1, 'version': 2},
287    'phy_ddr2_odt_pull_dn_en': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'odt_info', 'shift': 19, 'mask': 0x1, 'version': 2},
288    'reserved_ddr2_odt_info_bit20_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'odt_info', 'shift': 20, 'mask': 0xfff, 'version': 2},
289    'phy_ddr2_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'odten_freq', 'shift': 12, 'mask': 0xfff, 'version': 2},
290    'ddr2_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
291    'reserved_ddr2_odten_freq_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'odten_freq', 'shift': 24, 'mask': 0xff, 'version': 2},
292    'phy_ddr2_dq_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'sr_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
293    'phy_ddr2_ca_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'sr_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
294    'phy_ddr2_clk_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'sr_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
295    'reserved_ddr2_sr_when_odten_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'sr_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
296    'phy_ddr2_dq_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'sr_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
297    'phy_ddr2_ca_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'sr_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
298    'phy_ddr2_clk_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'sr_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
299    'reserved_ddr2_sr_when_odtoff_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'sr_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
300    'phy_ddr2_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'vref_when_odten', 'shift': 0, 'mask': 0x3ff, 'version': 5},
301    'ddr2_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'vref_when_odten', 'shift': 10, 'mask': 0x3ff, 'version': 5},
302    'ddr2_ca_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'vref_when_odten', 'shift': 20, 'mask': 0x3ff, 'version': 5},
303    'reserved_ddr2_vref_when_odten_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'vref_when_odten', 'shift': 30, 'mask': 0x3, 'version': 5},
304    'phy_ddr2_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'vref_when_odtoff', 'shift': 0, 'mask': 0x3ff, 'version': 5},
305    'ddr2_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'vref_when_odtoff', 'shift': 10, 'mask': 0x3ff, 'version': 5},
306    'ddr2_ca_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'vref_when_odtoff', 'shift': 20, 'mask': 0x3ff, 'version': 5},
307    'reserved_ddr2_vref_when_odtoff_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr2_index', 'position': 'vref_when_odtoff', 'shift': 30, 'mask': 0x3, 'version': 5},
308
309    'ddr3_f1_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'ddr_freq0_1', 'shift': 12, 'mask': 0xfff, 'version': 2},
310    'reserved_ddr3_ddr_freq0_1_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'ddr_freq0_1', 'shift': 24, 'mask': 0xff, 'version': 2},
311    'ddr3_f2_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'ddr_freq2_3', 'shift': 0, 'mask': 0xfff, 'version': 2},
312    'ddr3_f3_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'ddr_freq2_3', 'shift': 12, 'mask': 0xfff, 'version': 2},
313    'reserved_ddr3_ddr_freq2_3_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'ddr_freq2_3', 'shift': 24, 'mask': 0xff, 'version': 2},
314    'ddr3_f4_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'ddr_freq4_5', 'shift': 0, 'mask': 0xfff, 'version': 2},
315    'ddr3_f5_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'ddr_freq4_5', 'shift': 12, 'mask': 0xfff, 'version': 2},
316    'reserved_ddr3_ddr_freq4_5_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'ddr_freq4_5', 'shift': 24, 'mask': 0xff, 'version': 2},
317    'phy_ddr3_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'drv_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
318    'phy_ddr3_ca_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'drv_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
319    'phy_ddr3_clk_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'drv_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
320    'ddr3_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'drv_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
321    'phy_ddr3_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'drv_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
322    'phy_ddr3_ca_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'drv_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
323    'phy_ddr3_clk_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'drv_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
324    'ddr3_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'drv_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
325    'phy_ddr3_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'odt_info', 'shift': 8, 'mask': 0x3ff, 'version': 2},
326    'ddr3_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
327    'phy_ddr3_odt_pull_up_en': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'odt_info', 'shift': 18, 'mask': 0x1, 'version': 2},
328    'phy_ddr3_odt_pull_dn_en': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'odt_info', 'shift': 19, 'mask': 0x1, 'version': 2},
329    'reserved_ddr3_odt_info_bit20_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'odt_info', 'shift': 20, 'mask': 0xfff, 'version': 2},
330    'phy_ddr3_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'odten_freq', 'shift': 12, 'mask': 0xfff, 'version': 2},
331    'ddr3_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
332    'reserved_ddr3_odten_freq_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'odten_freq', 'shift': 24, 'mask': 0xff, 'version': 2},
333    'phy_ddr3_dq_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'sr_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
334    'phy_ddr3_ca_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'sr_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
335    'phy_ddr3_clk_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'sr_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
336    'reserved_ddr3_sr_when_odten_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'sr_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
337    'phy_ddr3_dq_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'sr_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
338    'phy_ddr3_ca_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'sr_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
339    'phy_ddr3_clk_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'sr_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
340    'reserved_ddr3_sr_when_odtoff_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'sr_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
341    'phy_ddr3_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'vref_when_odten', 'shift': 0, 'mask': 0x3ff, 'version': 5},
342    'ddr3_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'vref_when_odten', 'shift': 10, 'mask': 0x3ff, 'version': 5},
343    'ddr3_ca_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'vref_when_odten', 'shift': 20, 'mask': 0x3ff, 'version': 5},
344    'reserved_ddr3_vref_when_odten_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'vref_when_odten', 'shift': 30, 'mask': 0x3, 'version': 5},
345    'phy_ddr3_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'vref_when_odtoff', 'shift': 0, 'mask': 0x3ff, 'version': 5},
346    'ddr3_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'vref_when_odtoff', 'shift': 10, 'mask': 0x3ff, 'version': 5},
347    'ddr3_ca_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'vref_when_odtoff', 'shift': 20, 'mask': 0x3ff, 'version': 5},
348    'reserved_ddr3_vref_when_odtoff_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr3_index', 'position': 'vref_when_odtoff', 'shift': 30, 'mask': 0x3, 'version': 5},
349
350    'ddr4_f1_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'ddr_freq0_1', 'shift': 12, 'mask': 0xfff, 'version': 2},
351    'reserved_ddr4_ddr_freq0_1_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'ddr_freq0_1', 'shift': 24, 'mask': 0xff, 'version': 2},
352    'ddr4_f2_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'ddr_freq2_3', 'shift': 0, 'mask': 0xfff, 'version': 2},
353    'ddr4_f3_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'ddr_freq2_3', 'shift': 12, 'mask': 0xfff, 'version': 2},
354    'reserved_ddr4_ddr_freq2_3_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'ddr_freq2_3', 'shift': 24, 'mask': 0xff, 'version': 2},
355    'ddr4_f4_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'ddr_freq4_5', 'shift': 0, 'mask': 0xfff, 'version': 2},
356    'ddr4_f5_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'ddr_freq4_5', 'shift': 12, 'mask': 0xfff, 'version': 2},
357    'reserved_ddr4_ddr_freq4_5_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'ddr_freq4_5', 'shift': 24, 'mask': 0xff, 'version': 2},
358    'phy_ddr4_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'drv_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
359    'phy_ddr4_ca_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'drv_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
360    'phy_ddr4_clk_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'drv_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
361    'ddr4_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'drv_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
362    'phy_ddr4_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'drv_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
363    'phy_ddr4_ca_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'drv_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
364    'phy_ddr4_clk_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'drv_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
365    'ddr4_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'drv_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
366    'phy_ddr4_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'odt_info', 'shift': 8, 'mask': 0x3ff, 'version': 2},
367    'ddr4_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
368    'phy_ddr4_odt_pull_up_en': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'odt_info', 'shift': 18, 'mask': 0x1, 'version': 2},
369    'phy_ddr4_odt_pull_dn_en': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'odt_info', 'shift': 19, 'mask': 0x1, 'version': 2},
370    'reserved_ddr4_odt_info_bit20_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'odt_info', 'shift': 20, 'mask': 0xfff, 'version': 2},
371    'phy_ddr4_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'odten_freq', 'shift': 12, 'mask': 0xfff, 'version': 2},
372    'ddr4_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
373    'reserved_ddr4_odten_freq_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'odten_freq', 'shift': 24, 'mask': 0xff, 'version': 2},
374    'phy_ddr4_dq_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'sr_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
375    'phy_ddr4_ca_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'sr_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
376    'phy_ddr4_clk_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'sr_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
377    'reserved_ddr4_sr_when_odten_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'sr_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
378    'phy_ddr4_dq_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'sr_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
379    'phy_ddr4_ca_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'sr_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
380    'phy_ddr4_clk_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'sr_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
381    'reserved_ddr4_sr_when_odtoff_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'sr_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
382    'phy_ddr4_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'vref_when_odten', 'shift': 0, 'mask': 0x3ff, 'version': 5},
383    'ddr4_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'vref_when_odten', 'shift': 10, 'mask': 0x3ff, 'version': 5},
384    'ddr4_ca_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'vref_when_odten', 'shift': 20, 'mask': 0x3ff, 'version': 5},
385    'reserved_ddr4_vref_when_odten_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'vref_when_odten', 'shift': 30, 'mask': 0x3, 'version': 5},
386    'phy_ddr4_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'vref_when_odtoff', 'shift': 0, 'mask': 0x3ff, 'version': 5},
387    'ddr4_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'vref_when_odtoff', 'shift': 10, 'mask': 0x3ff, 'version': 5},
388    'ddr4_ca_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'vref_when_odtoff', 'shift': 20, 'mask': 0x3ff, 'version': 5},
389    'reserved_ddr4_vref_when_odtoff_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'ddr4_index', 'position': 'vref_when_odtoff', 'shift': 30, 'mask': 0x3, 'version': 5},
390
391    'lp2_f1_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'ddr_freq0_1', 'shift': 12, 'mask': 0xfff, 'version': 2},
392    'reserved_lp2_ddr_freq0_1_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'ddr_freq0_1', 'shift': 24, 'mask': 0xff, 'version': 2},
393    'lp2_f2_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'ddr_freq2_3', 'shift': 0, 'mask': 0xfff, 'version': 2},
394    'lp2_f3_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'ddr_freq2_3', 'shift': 12, 'mask': 0xfff, 'version': 2},
395    'reserved_lp2_ddr_freq2_3_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'ddr_freq2_3', 'shift': 24, 'mask': 0xff, 'version': 2},
396    'lp2_f4_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'ddr_freq4_5', 'shift': 0, 'mask': 0xfff, 'version': 2},
397    'lp2_f5_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'ddr_freq4_5', 'shift': 12, 'mask': 0xfff, 'version': 2},
398    'reserved_lp2_ddr_freq4_5_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'ddr_freq4_5', 'shift': 24, 'mask': 0xff, 'version': 2},
399    'phy_lp2_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'drv_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
400    'phy_lp2_ca_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'drv_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
401    'phy_lp2_clk_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'drv_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
402    'lp2_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'drv_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
403    'phy_lp2_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'drv_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
404    'phy_lp2_ca_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'drv_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
405    'phy_lp2_clk_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'drv_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
406    'lp2_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'drv_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
407    'phy_lp2_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'odt_info', 'shift': 8, 'mask': 0x3ff, 'version': 2},
408    'lp2_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
409    'phy_lp2_odt_pull_up_en': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'odt_info', 'shift': 18, 'mask': 0x1, 'version': 2},
410    'phy_lp2_odt_pull_dn_en': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'odt_info', 'shift': 19, 'mask': 0x1, 'version': 2},
411    'reserved_lp2_odt_info_bit20_31': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'odt_info', 'shift': 20, 'mask': 0xfff, 'version': 2},
412    'phy_lp2_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'odten_freq', 'shift': 12, 'mask': 0xfff, 'version': 2},
413    'lp2_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
414    'reserved_lp2_odten_freq_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'odten_freq', 'shift': 24, 'mask': 0xff, 'version': 2},
415    'phy_lp2_dq_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'sr_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
416    'phy_lp2_ca_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'sr_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
417    'phy_lp2_clk_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'sr_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
418    'reserved_lp2_sr_when_odten_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'sr_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
419    'phy_lp2_dq_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'sr_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
420    'phy_lp2_ca_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'sr_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
421    'phy_lp2_clk_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'sr_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
422    'reserved_lp2_sr_when_odtoff_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'sr_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
423    'phy_lp2_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'vref_when_odten', 'shift': 0, 'mask': 0x3ff, 'version': 5},
424    'lp2_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'vref_when_odten', 'shift': 10, 'mask': 0x3ff, 'version': 5},
425    'lp2_ca_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'vref_when_odten', 'shift': 20, 'mask': 0x3ff, 'version': 5},
426    'reserved_lp2_vref_when_odten_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'vref_when_odten', 'shift': 30, 'mask': 0x3, 'version': 5},
427    'phy_lp2_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'vref_when_odtoff', 'shift': 0, 'mask': 0x3ff, 'version': 5},
428    'lp2_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'vref_when_odtoff', 'shift': 10, 'mask': 0x3ff, 'version': 5},
429    'lp2_ca_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'vref_when_odtoff', 'shift': 20, 'mask': 0x3ff, 'version': 5},
430    'reserved_lp2_vref_when_odtoff_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'lp2_index', 'position': 'vref_when_odtoff', 'shift': 30, 'mask': 0x3, 'version': 5},
431
432    'lp3_f1_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'ddr_freq0_1', 'shift': 12, 'mask': 0xfff, 'version': 2},
433    'reserved_lp3_ddr_freq0_1_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'ddr_freq0_1', 'shift': 24, 'mask': 0xff, 'version': 2},
434    'lp3_f2_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'ddr_freq2_3', 'shift': 0, 'mask': 0xfff, 'version': 2},
435    'lp3_f3_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'ddr_freq2_3', 'shift': 12, 'mask': 0xfff, 'version': 2},
436    'reserved_lp3_ddr_freq2_3_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'ddr_freq2_3', 'shift': 24, 'mask': 0xff, 'version': 2},
437    'lp3_f4_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'ddr_freq4_5', 'shift': 0, 'mask': 0xfff, 'version': 2},
438    'lp3_f5_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'ddr_freq4_5', 'shift': 12, 'mask': 0xfff, 'version': 2},
439    'reserved_lp3_ddr_freq4_5_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'ddr_freq4_5', 'shift': 24, 'mask': 0xff, 'version': 2},
440    'phy_lp3_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'drv_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
441    'phy_lp3_ca_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'drv_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
442    'phy_lp3_clk_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'drv_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
443    'lp3_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'drv_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
444    'phy_lp3_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'drv_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
445    'phy_lp3_ca_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'drv_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
446    'phy_lp3_clk_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'drv_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
447    'lp3_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'drv_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
448    'phy_lp3_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'odt_info', 'shift': 8, 'mask': 0x3ff, 'version': 2},
449    'lp3_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
450    'phy_lp3_odt_pull_up_en': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'odt_info', 'shift': 18, 'mask': 0x1, 'version': 2},
451    'phy_lp3_odt_pull_dn_en': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'odt_info', 'shift': 19, 'mask': 0x1, 'version': 2},
452    'reserved_lp3_odt_info_bit20_31': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'odt_info', 'shift': 20, 'mask': 0xfff, 'version': 2},
453    'phy_lp3_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'odten_freq', 'shift': 12, 'mask': 0xfff, 'version': 2},
454    'lp3_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
455    'reserved_lp3_odten_freq_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'odten_freq', 'shift': 24, 'mask': 0xff, 'version': 2},
456    'phy_lp3_dq_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'sr_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
457    'phy_lp3_ca_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'sr_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
458    'phy_lp3_clk_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'sr_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
459    'reserved_lp3_sr_when_odten_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'sr_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
460    'phy_lp3_dq_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'sr_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
461    'phy_lp3_ca_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'sr_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
462    'phy_lp3_clk_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'sr_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
463    'reserved_lp3_sr_when_odtoff_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'sr_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
464    'phy_lp3_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'vref_when_odten', 'shift': 0, 'mask': 0x3ff, 'version': 5},
465    'lp3_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'vref_when_odten', 'shift': 10, 'mask': 0x3ff, 'version': 5},
466    'lp3_ca_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'vref_when_odten', 'shift': 20, 'mask': 0x3ff, 'version': 5},
467    'reserved_lp3_vref_when_odten_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'vref_when_odten', 'shift': 30, 'mask': 0x3, 'version': 5},
468    'phy_lp3_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'vref_when_odtoff', 'shift': 0, 'mask': 0x3ff, 'version': 5},
469    'lp3_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'vref_when_odtoff', 'shift': 10, 'mask': 0x3ff, 'version': 5},
470    'lp3_ca_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'vref_when_odtoff', 'shift': 20, 'mask': 0x3ff, 'version': 5},
471    'reserved_lp3_vref_when_odtoff_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'lp3_index', 'position': 'vref_when_odtoff', 'shift': 30, 'mask': 0x3, 'version': 5},
472
473    'lp4_f1_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ddr_freq0_1', 'shift': 12, 'mask': 0xfff, 'version': 2},
474    'reserved_lp4_ddr_freq0_1_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ddr_freq0_1', 'shift': 24, 'mask': 0xff, 'version': 2},
475    'lp4_f2_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ddr_freq2_3', 'shift': 0, 'mask': 0xfff, 'version': 2},
476    'lp4_f3_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ddr_freq2_3', 'shift': 12, 'mask': 0xfff, 'version': 2},
477    'reserved_lp4_ddr_freq2_3_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ddr_freq2_3', 'shift': 24, 'mask': 0xff, 'version': 2},
478    'lp4_f4_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ddr_freq4_5', 'shift': 0, 'mask': 0xfff, 'version': 2},
479    'lp4_f5_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ddr_freq4_5', 'shift': 12, 'mask': 0xfff, 'version': 2},
480    'reserved_lp4_ddr_freq4_5_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ddr_freq4_5', 'shift': 24, 'mask': 0xff, 'version': 2},
481    'phy_lp4_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'drv_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
482    'phy_lp4_ca_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'drv_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
483    'phy_lp4_clk_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'drv_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
484    'lp4_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'drv_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
485    'phy_lp4_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'drv_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
486    'phy_lp4_ca_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'drv_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
487    'phy_lp4_clk_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'drv_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
488    'lp4_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'drv_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
489    'phy_lp4_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'odt_info', 'shift': 8, 'mask': 0x3ff, 'version': 2},
490    'lp4_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
491    'lp4_ca_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'odt_info', 'shift': 18, 'mask': 0xff, 'version': 2},
492    'lp4_drv_pu_cal_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'odt_info', 'shift': 26, 'mask': 0x1, 'version': 2},
493    'lp4_drv_pu_cal_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'odt_info', 'shift': 27, 'mask': 0x1, 'version': 2},
494    'phy_lp4_drv_pull_dn_en_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'odt_info', 'shift': 28, 'mask': 0x1, 'version': 2},
495    'phy_lp4_drv_pull_dn_en_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'odt_info', 'shift': 29, 'mask': 0x1, 'version': 2},
496    'reserved_lp4_odt_info_bit31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'odt_info', 'shift': 31, 'mask': 0x1, 'version': 2},
497    'phy_lp4_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'dq_odten_freq', 'shift': 12, 'mask': 0xfff, 'version': 2},
498    'lp4_dq_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'dq_odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
499    'reserved_lp4_dq_odten_freq_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'dq_odten_freq', 'shift': 24, 'mask': 0xff, 'version': 2},
500    'phy_lp4_dq_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'sr_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
501    'phy_lp4_ca_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'sr_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
502    'phy_lp4_clk_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'sr_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
503    'reserved_lp4_sr_when_odten_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'sr_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
504    'phy_lp4_dq_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'sr_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
505    'phy_lp4_ca_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'sr_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
506    'phy_lp4_clk_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'sr_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
507    'reserved_lp4_sr_when_odtoff_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'sr_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
508    'lp4_ca_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ca_odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
509    'reserved_lp4_ca_odten_freq_bit12_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'ca_odten_freq', 'shift': 12, 'mask': 0xfffff, 'version': 2},
510    'phy_lp4_cs_drv_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'cs_drv_ca_odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
511    'phy_lp4_cs_drv_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'cs_drv_ca_odt_info', 'shift': 8, 'mask': 0xff, 'version': 2},
512    'lp4_odte_ck': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'cs_drv_ca_odt_info', 'shift': 16, 'mask': 0x1, 'version': 2},
513    'lp4_odte_cs_en': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'cs_drv_ca_odt_info', 'shift': 17, 'mask': 0x1, 'version': 2},
514    'lp4_odtd_ca_en': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'cs_drv_ca_odt_info', 'shift': 18, 'mask': 0x1, 'version': 2},
515    'reserved_lp4cs_drv_ca_odt_info_bit19_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'cs_drv_ca_odt_info', 'shift': 19, 'mask': 0x1fff, 'version': 2},
516    'phy_lp4_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'vref_when_odten', 'shift': 0, 'mask': 0x3ff, 'version': 2},
517    'lp4_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'vref_when_odten', 'shift': 10, 'mask': 0x3ff, 'version': 2},
518    'lp4_ca_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'vref_when_odten', 'shift': 20, 'mask': 0x3ff, 'version': 2},
519    'reserved_lp4_vref_when_odten_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'vref_when_odten', 'shift': 30, 'mask': 0x3, 'version': 2},
520    'phy_lp4_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'vref_when_odtoff', 'shift': 0, 'mask': 0x3ff, 'version': 2},
521    'lp4_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'vref_when_odtoff', 'shift': 10, 'mask': 0x3ff, 'version': 2},
522    'lp4_ca_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'vref_when_odtoff', 'shift': 20, 'mask': 0x3ff, 'version': 2},
523    'reserved_lp4_vref_when_odtoff_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4_index', 'position': 'vref_when_odtoff', 'shift': 30, 'mask': 0x3, 'version': 2},
524
525    'ddr2_bytes_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'byte_map_0', 'shift': 16, 'mask': 0xff, 'version': 2},
526    'ddr3_bytes_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'byte_map_0', 'shift': 24, 'mask': 0xff, 'version': 2},
527    'ddr4_bytes_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'byte_map_0', 'shift': 0, 'mask': 0xff, 'version': 2},
528    'reservedbyte_map_0_bit8_15': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'byte_map_0', 'shift': 8, 'mask': 0xff, 'version': 2},
529    'lp2_bytes_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'byte_map_1', 'shift': 8, 'mask': 0xff, 'version': 2},
530    'lp3_bytes_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'byte_map_1', 'shift': 16, 'mask': 0xff, 'version': 2},
531    'lp4_bytes_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'byte_map_1', 'shift': 24, 'mask': 0xff, 'version': 2},
532    'reserved_byte_map_1_bit0_7': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'byte_map_1', 'shift': 0, 'mask': 0xff, 'version': 2},
533    'lp3_dq0_7_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'lp3_dq0_7_map', 'shift': 0, 'mask': 0xffffffff, 'version': 2},
534    'lp2_dq0_7_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'lp2_dq0_7_map', 'shift': 0, 'mask': 0xffffffff, 'version': 2},
535    'ddr4_cs0_dq0_dq15_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'ddr4_dq_map_0', 'shift': 0, 'mask': 0xffffffff, 'version': 2},
536    'ddr4_cs0_dq16_dq31_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'ddr4_dq_map_1', 'shift': 0, 'mask': 0xffffffff, 'version': 2},
537    'ddr4_cs1_dq0_dq15_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'ddr4_dq_map_2', 'shift': 0, 'mask': 0xffffffff, 'version': 2},
538    'ddr4_cs1_dq16_dq31_map': {'value': 0, 'num_base': 'hex', 'index': 'dq_map_index', 'position': 'ddr4_dq_map_3', 'shift': 0, 'mask': 0xffffffff, 'version': 2},
539
540    'lp4x_f1_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ddr_freq0_1', 'shift': 12, 'mask': 0xfff, 'version': 2},
541    'reserved_lp4x_ddr_freq0_1_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ddr_freq0_1', 'shift': 24, 'mask': 0xff, 'version': 2},
542    'lp4x_f2_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ddr_freq2_3', 'shift': 0, 'mask': 0xfff, 'version': 2},
543    'lp4x_f3_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ddr_freq2_3', 'shift': 12, 'mask': 0xfff, 'version': 2},
544    'reserved_lp4x_ddr_freq2_3_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ddr_freq2_3', 'shift': 24, 'mask': 0xff, 'version': 2},
545    'lp4x_f4_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ddr_freq4_5', 'shift': 0, 'mask': 0xfff, 'version': 2},
546    'lp4x_f5_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ddr_freq4_5', 'shift': 12, 'mask': 0xfff, 'version': 2},
547    'reserved_lp4x_ddr_freq4_5_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ddr_freq4_5', 'shift': 24, 'mask': 0xff, 'version': 2},
548    'phy_lp4x_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'drv_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
549    'phy_lp4x_ca_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'drv_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
550    'phy_lp4x_clk_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'drv_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
551    'lp4x_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'drv_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
552    'phy_lp4x_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'drv_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
553    'phy_lp4x_ca_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'drv_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
554    'phy_lp4x_clk_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'drv_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
555    'lp4x_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'drv_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
556    'phy_lp4x_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'odt_info', 'shift': 8, 'mask': 0x3ff, 'version': 2},
557    'lp4x_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
558    'lp4x_ca_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'odt_info', 'shift': 18, 'mask': 0xff, 'version': 2},
559    'lp4x_drv_pu_cal_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'odt_info', 'shift': 26, 'mask': 0x1, 'version': 2},
560    'lp4x_drv_pu_cal_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'odt_info', 'shift': 27, 'mask': 0x1, 'version': 2},
561    'phy_lp4x_drv_pull_dn_en_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'odt_info', 'shift': 28, 'mask': 0x1, 'version': 2},
562    'phy_lp4x_drv_pull_dn_en_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'odt_info', 'shift': 29, 'mask': 0x1, 'version': 2},
563    'reserved_lp4x_odt_info_bit31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'odt_info', 'shift': 31, 'mask': 0x1, 'version': 2},
564    'phy_lp4x_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'dq_odten_freq', 'shift': 12, 'mask': 0xfff, 'version': 2},
565    'lp4x_dq_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'dq_odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
566    'reserved_lp4x_dq_odten_freq_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'dq_odten_freq', 'shift': 24, 'mask': 0xff, 'version': 2},
567    'phy_lp4x_dq_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'sr_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
568    'phy_lp4x_ca_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'sr_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
569    'phy_lp4x_clk_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'sr_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
570    'reserved_lp4x_sr_when_odten_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'sr_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
571    'phy_lp4x_dq_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'sr_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
572    'phy_lp4x_ca_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'sr_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
573    'phy_lp4x_clk_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'sr_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
574    'reserved_lp4x_sr_when_odtoff_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'sr_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
575    'lp4x_ca_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ca_odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
576    'reserved_lp4x_ca_odten_freq_bit12_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'ca_odten_freq', 'shift': 12, 'mask': 0xfffff, 'version': 2},
577    'phy_lp4x_cs_drv_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'cs_drv_ca_odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
578    'phy_lp4x_cs_drv_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'cs_drv_ca_odt_info', 'shift': 8, 'mask': 0xff, 'version': 2},
579    'lp4x_odte_ck': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'cs_drv_ca_odt_info', 'shift': 16, 'mask': 0x1, 'version': 2},
580    'lp4x_odte_cs_en': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'cs_drv_ca_odt_info', 'shift': 17, 'mask': 0x1, 'version': 2},
581    'lp4x_odtd_ca_en': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'cs_drv_ca_odt_info', 'shift': 18, 'mask': 0x1, 'version': 2},
582    'reserved_lp4xcs_drv_ca_odt_info_bit19_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'cs_drv_ca_odt_info', 'shift': 19, 'mask': 0x1fff, 'version': 2},
583    'phy_lp4x_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'vref_when_odten', 'shift': 0, 'mask': 0x3ff, 'version': 2},
584    'lp4x_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'vref_when_odten', 'shift': 10, 'mask': 0x3ff, 'version': 2},
585    'lp4x_ca_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'vref_when_odten', 'shift': 20, 'mask': 0x3ff, 'version': 2},
586    'reserved_lp4x_vref_when_odten_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'vref_when_odten', 'shift': 30, 'mask': 0x3, 'version': 2},
587    'phy_lp4x_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'vref_when_odtoff', 'shift': 0, 'mask': 0x3ff, 'version': 2},
588    'lp4x_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'vref_when_odtoff', 'shift': 10, 'mask': 0x3ff, 'version': 2},
589    'lp4x_ca_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'vref_when_odtoff', 'shift': 20, 'mask': 0x3ff, 'version': 2},
590    'reserved_lp4x_vref_when_odtoff_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'lp4x_index', 'position': 'vref_when_odtoff', 'shift': 30, 'mask': 0x3, 'version': 2},
591
592    'lp5_f1_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ddr_freq0_1', 'shift': 12, 'mask': 0xfff, 'version': 2},
593    'reserved_lp5_ddr_freq0_1_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ddr_freq0_1', 'shift': 24, 'mask': 0xff, 'version': 2},
594    'lp5_f2_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ddr_freq2_3', 'shift': 0, 'mask': 0xfff, 'version': 2},
595    'lp5_f3_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ddr_freq2_3', 'shift': 12, 'mask': 0xfff, 'version': 2},
596    'reserved_lp5_ddr_freq2_3_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ddr_freq2_3', 'shift': 24, 'mask': 0xff, 'version': 2},
597    'lp5_f4_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ddr_freq4_5', 'shift': 0, 'mask': 0xfff, 'version': 2},
598    'lp5_f5_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ddr_freq4_5', 'shift': 12, 'mask': 0xfff, 'version': 2},
599    'reserved_lp5_ddr_freq4_5_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ddr_freq4_5', 'shift': 24, 'mask': 0xff, 'version': 2},
600    'phy_lp5_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'drv_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
601    'phy_lp5_ca_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'drv_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
602    'phy_lp5_clk_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'drv_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
603    'lp5_dq_drv_when_odten_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'drv_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
604    'phy_lp5_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'drv_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
605    'phy_lp5_ca_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'drv_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
606    'phy_lp5_clk_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'drv_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
607    'lp5_dq_drv_when_odtoff_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'drv_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
608    'phy_lp5_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'odt_info', 'shift': 8, 'mask': 0x3ff, 'version': 2},
609    'lp5_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
610    'lp5_ca_odt_ohm': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'odt_info', 'shift': 18, 'mask': 0xff, 'version': 2},
611    'lp5_drv_pu_cal_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'odt_info', 'shift': 26, 'mask': 0x1, 'version': 2},
612    'lp5_drv_pu_cal_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'odt_info', 'shift': 27, 'mask': 0x1, 'version': 2},
613    'phy_lp5_drv_pull_dn_en_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'odt_info', 'shift': 28, 'mask': 0x1, 'version': 2},
614    'phy_lp5_drv_pull_dn_en_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'odt_info', 'shift': 29, 'mask': 0x1, 'version': 2},
615    'reserved_lp5_odt_info_bit31': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'odt_info', 'shift': 31, 'mask': 0x1, 'version': 2},
616    'phy_lp5_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'dq_odten_freq', 'shift': 12, 'mask': 0xfff, 'version': 2},
617    'lp5_dq_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'dq_odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
618    'reserved_lp5_dq_odten_freq_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'dq_odten_freq', 'shift': 24, 'mask': 0xff, 'version': 2},
619    'phy_lp5_dq_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'sr_when_odten', 'shift': 0, 'mask': 0xff, 'version': 2},
620    'phy_lp5_ca_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'sr_when_odten', 'shift': 8, 'mask': 0xff, 'version': 2},
621    'phy_lp5_clk_sr_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'sr_when_odten', 'shift': 16, 'mask': 0xff, 'version': 2},
622    'reserved_lp5_sr_when_odten_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'sr_when_odten', 'shift': 24, 'mask': 0xff, 'version': 2},
623    'phy_lp5_dq_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'sr_when_odtoff', 'shift': 0, 'mask': 0xff, 'version': 2},
624    'phy_lp5_ca_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'sr_when_odtoff', 'shift': 8, 'mask': 0xff, 'version': 2},
625    'phy_lp5_clk_sr_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'sr_when_odtoff', 'shift': 16, 'mask': 0xff, 'version': 2},
626    'reserved_lp5_sr_when_odtoff_bit24_31': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'sr_when_odtoff', 'shift': 24, 'mask': 0xff, 'version': 2},
627    'lp5_ca_odten_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ca_odten_freq', 'shift': 0, 'mask': 0xfff, 'version': 2},
628    'lp5_wck_odt_en_freq': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ca_odten_freq', 'shift': 12, 'mask': 0xfff, 'version': 2},
629    'lp5_wck_odt': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'ca_odten_freq', 'shift': 24, 'mask': 0xff, 'version': 2},
630    'phy_lp5_cs_drv_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'cs_drv_ca_odt_info', 'shift': 0, 'mask': 0xff, 'version': 2},
631    'phy_lp5_cs_drv_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'cs_drv_ca_odt_info', 'shift': 8, 'mask': 0xff, 'version': 2},
632    'lp5_odte_ck': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'cs_drv_ca_odt_info', 'shift': 16, 'mask': 0x1, 'version': 2},
633    'lp5_odte_cs_en': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'cs_drv_ca_odt_info', 'shift': 17, 'mask': 0x1, 'version': 2},
634    'lp5_odtd_ca_en': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'cs_drv_ca_odt_info', 'shift': 18, 'mask': 0x1, 'version': 2},
635    'lp5_nt_odt': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'cs_drv_ca_odt_info', 'shift': 24, 'mask': 0xff, 'version': 2},
636    'reserved_lp5_cs_drv_ca_odt_info_bit19_23': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'cs_drv_ca_odt_info', 'shift': 19, 'mask': 0x1f, 'version': 2},
637    'phy_lp5_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'vref_when_odten', 'shift': 0, 'mask': 0x3ff, 'version': 2},
638    'lp5_dq_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'vref_when_odten', 'shift': 10, 'mask': 0x3ff, 'version': 2},
639    'lp5_ca_vref_when_odten': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'vref_when_odten', 'shift': 20, 'mask': 0x3ff, 'version': 2},
640    'reserved_lp5_vref_when_odten_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'vref_when_odten', 'shift': 30, 'mask': 0x3, 'version': 2},
641    'phy_lp5_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'vref_when_odtoff', 'shift': 0, 'mask': 0x3ff, 'version': 2},
642    'lp5_dq_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'vref_when_odtoff', 'shift': 10, 'mask': 0x3ff, 'version': 2},
643    'lp5_ca_vref_when_odtoff': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'vref_when_odtoff', 'shift': 20, 'mask': 0x3ff, 'version': 2},
644    'reserved_lp5_vref_when_odtoff_bit30_31': {'value': 0, 'num_base': 'dec', 'index': 'lp5_index', 'position': 'vref_when_odtoff', 'shift': 30, 'mask': 0x3, 'version': 2},
645
646    'lp4_4x_ch_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp4_4x_hash_index', 'position': 'ch_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 3},
647    'lp4_4x_ch_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp4_4x_hash_index', 'position': 'ch_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 3},
648    'lp4_4x_bank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp4_4x_hash_index', 'position': 'bank_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 3},
649    'lp4_4x_bank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp4_4x_hash_index', 'position': 'bank_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 3},
650    'lp4_4x_bank_mask2': {'value': 0, 'num_base': 'hex', 'index': 'lp4_4x_hash_index', 'position': 'bank_mask_2', 'shift': 0, 'mask': 0xffffffff, 'version': 3},
651    'lp4_4x_bank_mask3': {'value': 0, 'num_base': 'hex', 'index': 'lp4_4x_hash_index', 'position': 'bank_mask_3', 'shift': 0, 'mask': 0xffffffff, 'version': 3},
652    'lp4_4x_rank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp4_4x_hash_index', 'position': 'rank_mask0', 'shift': 0, 'mask': 0xffffffff, 'version': 3},
653    'lp4_4x_rank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp4_4x_hash_index', 'position': 'rank_mask1', 'shift': 0, 'mask': 0xffffffff, 'version': 3},
654
655    'lp5_ch_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp5_hash_index', 'position': 'ch_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
656    'lp5_ch_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp5_hash_index', 'position': 'ch_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
657    'lp5_bank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp5_hash_index', 'position': 'bank_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
658    'lp5_bank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp5_hash_index', 'position': 'bank_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
659    'lp5_bank_mask2': {'value': 0, 'num_base': 'hex', 'index': 'lp5_hash_index', 'position': 'bank_mask_2', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
660    'lp5_bank_mask3': {'value': 0, 'num_base': 'hex', 'index': 'lp5_hash_index', 'position': 'bank_mask_3', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
661    'lp5_rank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp5_hash_index', 'position': 'rank_mask0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
662    'lp5_rank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp5_hash_index', 'position': 'rank_mask1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
663
664    'ddr4_ch_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr4_hash_index', 'position': 'ch_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
665    'ddr4_ch_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr4_hash_index', 'position': 'ch_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
666    'ddr4_bank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr4_hash_index', 'position': 'bank_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
667    'ddr4_bank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr4_hash_index', 'position': 'bank_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
668    'ddr4_bank_mask2': {'value': 0, 'num_base': 'hex', 'index': 'ddr4_hash_index', 'position': 'bank_mask_2', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
669    'ddr4_bank_mask3': {'value': 0, 'num_base': 'hex', 'index': 'ddr4_hash_index', 'position': 'bank_mask_3', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
670    'ddr4_rank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr4_hash_index', 'position': 'rank_mask0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
671    'ddr4_rank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr4_hash_index', 'position': 'rank_mask1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
672
673    'lp3_ch_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp3_hash_index', 'position': 'ch_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
674    'lp3_ch_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp3_hash_index', 'position': 'ch_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
675    'lp3_bank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp3_hash_index', 'position': 'bank_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
676    'lp3_bank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp3_hash_index', 'position': 'bank_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
677    'lp3_bank_mask2': {'value': 0, 'num_base': 'hex', 'index': 'lp3_hash_index', 'position': 'bank_mask_2', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
678    'lp3_bank_mask3': {'value': 0, 'num_base': 'hex', 'index': 'lp3_hash_index', 'position': 'bank_mask_3', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
679    'lp3_rank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp3_hash_index', 'position': 'rank_mask0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
680    'lp3_rank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp3_hash_index', 'position': 'rank_mask1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
681
682    'ddr3_ch_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr3_hash_index', 'position': 'ch_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
683    'ddr3_ch_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr3_hash_index', 'position': 'ch_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
684    'ddr3_bank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr3_hash_index', 'position': 'bank_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
685    'ddr3_bank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr3_hash_index', 'position': 'bank_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
686    'ddr3_bank_mask2': {'value': 0, 'num_base': 'hex', 'index': 'ddr3_hash_index', 'position': 'bank_mask_2', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
687    'ddr3_bank_mask3': {'value': 0, 'num_base': 'hex', 'index': 'ddr3_hash_index', 'position': 'bank_mask_3', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
688    'ddr3_rank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr3_hash_index', 'position': 'rank_mask0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
689    'ddr3_rank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr3_hash_index', 'position': 'rank_mask1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
690
691    'lp2_ch_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp2_hash_index', 'position': 'ch_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
692    'lp2_ch_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp2_hash_index', 'position': 'ch_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
693    'lp2_bank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp2_hash_index', 'position': 'bank_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
694    'lp2_bank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp2_hash_index', 'position': 'bank_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
695    'lp2_bank_mask2': {'value': 0, 'num_base': 'hex', 'index': 'lp2_hash_index', 'position': 'bank_mask_2', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
696    'lp2_bank_mask3': {'value': 0, 'num_base': 'hex', 'index': 'lp2_hash_index', 'position': 'bank_mask_3', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
697    'lp2_rank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'lp2_hash_index', 'position': 'rank_mask0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
698    'lp2_rank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'lp2_hash_index', 'position': 'rank_mask1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
699
700    'ddr2_ch_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr2_hash_index', 'position': 'ch_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
701    'ddr2_ch_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr2_hash_index', 'position': 'ch_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
702    'ddr2_bank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr2_hash_index', 'position': 'bank_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
703    'ddr2_bank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr2_hash_index', 'position': 'bank_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
704    'ddr2_bank_mask2': {'value': 0, 'num_base': 'hex', 'index': 'ddr2_hash_index', 'position': 'bank_mask_2', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
705    'ddr2_bank_mask3': {'value': 0, 'num_base': 'hex', 'index': 'ddr2_hash_index', 'position': 'bank_mask_3', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
706    'ddr2_rank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr2_hash_index', 'position': 'rank_mask0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
707    'ddr2_rank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr2_hash_index', 'position': 'rank_mask1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
708
709    'ddr5_ch_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr5_hash_index', 'position': 'ch_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
710    'ddr5_ch_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr5_hash_index', 'position': 'ch_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
711    'ddr5_bank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr5_hash_index', 'position': 'bank_mask_0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
712    'ddr5_bank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr5_hash_index', 'position': 'bank_mask_1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
713    'ddr5_bank_mask2': {'value': 0, 'num_base': 'hex', 'index': 'ddr5_hash_index', 'position': 'bank_mask_2', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
714    'ddr5_bank_mask3': {'value': 0, 'num_base': 'hex', 'index': 'ddr5_hash_index', 'position': 'bank_mask_3', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
715    'ddr5_rank_mask0': {'value': 0, 'num_base': 'hex', 'index': 'ddr5_hash_index', 'position': 'rank_mask0', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
716    'ddr5_rank_mask1': {'value': 0, 'num_base': 'hex', 'index': 'ddr5_hash_index', 'position': 'rank_mask1', 'shift': 0, 'mask': 0xffffffff, 'version': 4},
717
718    'reserved_skew_ddr3_skew_freq_bit12_31': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_skew_freq', 'shift': 12, 'mask': 0xfffff, 'version': 4},
719    'ddr3_skew_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'skew_index', 'position': 'ddr3_skew_freq', 'shift': 0, 'mask': 0xfff, 'version': 4},
720    'ddr3_ca0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_2', 'shift': 8, 'mask': 0xff, 'version': 4},
721    'ddr3_ca1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_0', 'shift': 0, 'mask': 0xff, 'version': 4},
722    'ddr3_ca2_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_1', 'shift': 24, 'mask': 0xff, 'version': 4},
723    'ddr3_ca3_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_1', 'shift': 8, 'mask': 0xff, 'version': 4},
724    'ddr3_ca4_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_1', 'shift': 16, 'mask': 0xff, 'version': 4},
725    'ddr3_ca5_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_2', 'shift': 24, 'mask': 0xff, 'version': 4},
726    'ddr3_ca6_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_1', 'shift': 0, 'mask': 0xff, 'version': 4},
727    'ddr3_ca7_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_2', 'shift': 0, 'mask': 0xff, 'version': 4},
728    'ddr3_ca8_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_3', 'shift': 16, 'mask': 0xff, 'version': 4},
729    'ddr3_ca9_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_0', 'shift': 24, 'mask': 0xff, 'version': 4},
730    'ddr3_ca10_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_3', 'shift': 24, 'mask': 0xff, 'version': 4},
731    'ddr3_ca11_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_2', 'shift': 16, 'mask': 0xff, 'version': 4},
732    'ddr3_ca12_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_4', 'shift': 0, 'mask': 0xff, 'version': 4},
733    'ddr3_ca13_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_0', 'shift': 8, 'mask': 0xff, 'version': 4},
734    'ddr3_ca14_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_0', 'shift': 16, 'mask': 0xff, 'version': 4},
735    'ddr3_ca15_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_5', 'shift': 16, 'mask': 0xff, 'version': 4},
736    'ddr3_ras_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_5', 'shift': 8, 'mask': 0xff, 'version': 4},
737    'ddr3_cas_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_7', 'shift': 24, 'mask': 0xff, 'version': 4},
738    'ddr3_ba0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_5', 'shift': 24, 'mask': 0xff, 'version': 4},
739    'ddr3_ba1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_3', 'shift': 0, 'mask': 0xff, 'version': 4},
740    'ddr3_ba2_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_4', 'shift': 8, 'mask': 0xff, 'version': 4},
741    'ddr3_we_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_6', 'shift': 8, 'mask': 0xff, 'version': 4},
742    'ddr3_cke0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_4', 'shift': 24, 'mask': 0xff, 'version': 4},
743    'ddr3_cke1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_5', 'shift': 0, 'mask': 0xff, 'version': 4},
744    'ddr3_ckn_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_6', 'shift': 24, 'mask': 0xff, 'version': 4},
745    'ddr3_ckp_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_6', 'shift': 16, 'mask': 0xff, 'version': 4},
746    'ddr3_odt0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_3', 'shift': 8, 'mask': 0xff, 'version': 4},
747    'ddr3_odt1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_6', 'shift': 0, 'mask': 0xff, 'version': 4},
748    'ddr3_cs0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_7', 'shift': 0, 'mask': 0xff, 'version': 4},
749    'ddr3_cs1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_7', 'shift': 16, 'mask': 0xff, 'version': 4},
750    'ddr3_resetn_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr3_ca_skew_7', 'shift': 8, 'mask': 0xff, 'version': 4},
751
752    'reserved_skew_ddr4_skew_freq_bit12_31': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_skew_freq', 'shift': 12, 'mask': 0xfffff, 'version': 4},
753    'ddr4_skew_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'skew_index', 'position': 'ddr4_skew_freq', 'shift': 0, 'mask': 0xfff, 'version': 4},
754    'ddr4_ca0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_0', 'shift': 24, 'mask': 0xff, 'version': 4},
755    'ddr4_ca1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_0', 'shift': 16, 'mask': 0xff, 'version': 4},
756    'ddr4_ca2_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_0', 'shift': 8, 'mask': 0xff, 'version': 4},
757    'ddr4_ca3_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_0', 'shift': 0, 'mask': 0xff, 'version': 4},
758    'ddr4_ca4_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_1', 'shift': 24, 'mask': 0xff, 'version': 4},
759    'ddr4_ca5_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_1', 'shift': 16, 'mask': 0xff, 'version': 4},
760    'ddr4_ca6_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_1', 'shift': 8, 'mask': 0xff, 'version': 4},
761    'ddr4_ca7_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_1', 'shift': 0, 'mask': 0xff, 'version': 4},
762    'ddr4_ca8_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_2', 'shift': 24, 'mask': 0xff, 'version': 4},
763    'ddr4_ca9_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_2', 'shift': 16, 'mask': 0xff, 'version': 4},
764    'ddr4_ca10_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_2', 'shift': 8, 'mask': 0xff, 'version': 4},
765    'ddr4_ca11_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_2', 'shift': 0, 'mask': 0xff, 'version': 4},
766    'ddr4_ca12_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_3', 'shift': 24, 'mask': 0xff, 'version': 4},
767    'ddr4_ca13_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_3', 'shift': 16, 'mask': 0xff, 'version': 4},
768    'ddr4_ca14_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_3', 'shift': 8, 'mask': 0xff, 'version': 4},
769    'ddr4_ca15_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_3', 'shift': 0, 'mask': 0xff, 'version': 4},
770    'ddr4_ca16_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_4', 'shift': 24, 'mask': 0xff, 'version': 4},
771    'ddr4_ca17_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_4', 'shift': 16, 'mask': 0xff, 'version': 4},
772    'ddr4_ba0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_4', 'shift': 8, 'mask': 0xff, 'version': 4},
773    'ddr4_ba1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_4', 'shift': 0, 'mask': 0xff, 'version': 4},
774    'ddr4_bg0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_5', 'shift': 24, 'mask': 0xff, 'version': 4},
775    'ddr4_bg1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_5', 'shift': 16, 'mask': 0xff, 'version': 4},
776    'ddr4_cke0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_5', 'shift': 8, 'mask': 0xff, 'version': 4},
777    'ddr4_cke1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_5', 'shift': 0, 'mask': 0xff, 'version': 4},
778    'ddr4_ckn_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_6', 'shift': 24, 'mask': 0xff, 'version': 4},
779    'ddr4_ckp_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_6', 'shift': 16, 'mask': 0xff, 'version': 4},
780    'ddr4_odt0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_6', 'shift': 8, 'mask': 0xff, 'version': 4},
781    'ddr4_odt1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_6', 'shift': 0, 'mask': 0xff, 'version': 4},
782    'ddr4_cs0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_7', 'shift': 24, 'mask': 0xff, 'version': 4},
783    'ddr4_cs1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_7', 'shift': 16, 'mask': 0xff, 'version': 4},
784    'ddr4_resetn_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_7', 'shift': 8, 'mask': 0xff, 'version': 4},
785    'ddr4_actn_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'ddr4_ca_skew_7', 'shift': 0, 'mask': 0xff, 'version': 4},
786
787    'reserved_skew_lp3_skew_freq_bit12_31': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_skew_freq', 'shift': 12, 'mask': 0xfffff, 'version': 4},
788    'lp3_skew_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'skew_index', 'position': 'lp3_skew_freq', 'shift': 0, 'mask': 0xfff, 'version': 4},
789    'lp3_ca0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_3', 'shift': 0, 'mask': 0xff, 'version': 4},
790    'lp3_ca1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_4', 'shift': 0, 'mask': 0xff, 'version': 4},
791    'lp3_ca2_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_2', 'shift': 16, 'mask': 0xff, 'version': 4},
792    'lp3_ca3_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_3', 'shift': 16, 'mask': 0xff, 'version': 4},
793    'lp3_ca4_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_3', 'shift': 24, 'mask': 0xff, 'version': 4},
794    'lp3_ca5_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_1', 'shift': 24, 'mask': 0xff, 'version': 4},
795    'lp3_ca6_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_2', 'shift': 24, 'mask': 0xff, 'version': 4},
796    'lp3_ca7_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_2', 'shift': 0, 'mask': 0xff, 'version': 4},
797    'lp3_ca8_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_5', 'shift': 24, 'mask': 0xff, 'version': 4},
798    'lp3_ca9_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_7', 'shift': 0, 'mask': 0xff, 'version': 4},
799    'lp3_cke0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_4', 'shift': 8, 'mask': 0xff, 'version': 4},
800    'lp3_cke1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_5', 'shift': 0, 'mask': 0xff, 'version': 4},
801    'lp3_ckn_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_6', 'shift': 24, 'mask': 0xff, 'version': 4},
802    'lp3_ckp_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_6', 'shift': 16, 'mask': 0xff, 'version': 4},
803    'lp3_odt0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_6', 'shift': 8, 'mask': 0xff, 'version': 4},
804    'lp3_odt1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_6', 'shift': 0, 'mask': 0xff, 'version': 4},
805    'lp3_odt2_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_0', 'shift': 24, 'mask': 0xff, 'version': 4},
806    'lp3_odt3_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_0', 'shift': 8, 'mask': 0xff, 'version': 4},
807    'lp3_cs0_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_7', 'shift': 16, 'mask': 0xff, 'version': 4},
808    'lp3_cs1_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_7', 'shift': 24, 'mask': 0xff, 'version': 4},
809    'lp3_cs2_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_1', 'shift': 8, 'mask': 0xff, 'version': 4},
810    'lp3_cs3_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'lp3_ca_skew_3', 'shift': 8, 'mask': 0xff, 'version': 4},
811
812    'reserved_skew_lp4_skew_freq_bit12_31': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
813    'lp4_skew_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
814    'lp4_ca0_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
815    'lp4_ca1_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
816    'lp4_ca2_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
817    'lp4_ca3_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
818    'lp4_ca4_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
819    'lp4_ca5_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
820    'lp4_odt0_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
821    'lp4_odt1_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
822    'lp4_cke0_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
823    'lp4_cke1_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
824    'lp4_ckn_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
825    'lp4_ckp_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
826    'lp4_cs0_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
827    'lp4_cs1_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
828    'lp4_ca0_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
829    'lp4_ca1_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
830    'lp4_ca2_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
831    'lp4_ca3_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
832    'lp4_ca4_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
833    'lp4_ca5_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
834    'lp4_odt0_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
835    'lp4_odt1_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
836    'lp4_cke0_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
837    'lp4_cke1_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
838    'lp4_ckn_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
839    'lp4_ckp_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
840    'lp4_cs0_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
841    'lp4_cs1_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
842    'lp4_resetn_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
843
844    'reserved_skew_lp5_skew_freq_bit12_31': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
845    'lp5_skew_freq_mhz': {'value': 0, 'num_base': 'dec', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
846    'lp5_ca0_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
847    'lp5_ca1_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
848    'lp5_ca2_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
849    'lp5_ca3_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
850    'lp5_ca4_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
851    'lp5_ca5_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
852    'lp5_ca6_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
853    'lp5_ckn_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
854    'lp5_ckp_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
855    'lp5_cs0_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
856    'lp5_cs1_a_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
857    'lp5_ca0_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
858    'lp5_ca1_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
859    'lp5_ca2_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
860    'lp5_ca3_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
861    'lp5_ca4_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
862    'lp5_ca5_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
863    'lp5_ca6_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
864    'lp5_ckn_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
865    'lp5_ckp_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
866    'lp5_cs0_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
867    'lp5_cs1_b_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
868    'lp5_resetn_skew': {'value': 0, 'num_base': 'hex', 'index': 'skew_index', 'position': 'null', 'shift': 0, 'mask': 0, 'version': 4},
869}
870
871
872def bin_data_2_info(info_from_bin, read_out, ddrbin_index, version, info_from_txt):
873    info_from_bin['start tag']['value'] = 0x12345678
874
875    if version < 2:
876        for key, value in info_from_bin.items():
877            if value['version'] <= version:
878                for i in range(len(read_out)):
879                    # read_out is sdram_head_info_v0 = [[offset, value], ...]
880                    # info_from_bin v0_info = [offset, shift, mask]
881                    if value['v0_info'][0] == read_out[i][0]:
882                        temp_value = (read_out[i][1] >> value['v0_info'][1]) & value['v0_info'][2]
883                        info_from_bin[key]['value'] = temp_value
884                        #print(f"D: {key} = {value} {hex(value['v0_info'][0])}={read_out[i][1]}")
885    elif version <= version_max:
886        for index_name in ddrbin_index:
887            head_info_name = index_name[:-6]+'_info'
888            if ddrbin_index[index_name]['offset'] != 0 and 'skew' not in index_name:
889                for key, value in info_from_bin.items():
890                    if value['index'] == index_name and value['version'] <= version:
891                        temp_value = read_out[head_info_name][value['position']]
892                        temp_value = (temp_value >> value['shift']) & value['mask']
893                        info_from_bin[key]['value'] = temp_value
894                        #print(f"D: {key} = {value} {value['position']}={temp_value}")
895            elif ddrbin_index[index_name]['offset'] != 0 and 'skew' in index_name:
896                if chip_info == 'rk3528':
897                    for key, value in info_from_bin.items():
898                        if value['index'] == index_name and value['version'] <= version:
899                            position_1 = value['position'][ : value['position'].find('_')]
900                            position_2 = value['position'][value['position'].find('_') + 1 : ]
901                            # read_out is sdram_head_info_v2 or sdram_head_info_v5
902                            if position_1 in list(read_out[head_info_name].keys()):
903                                temp_value = read_out[head_info_name][position_1][position_2]
904                                temp_value = (temp_value >> value['shift']) & value['mask']
905                                info_from_bin[key]['value'] = temp_value
906                                #print(f"D: {key} = {value} {value['position']}={temp_value}")
907
908    return 0
909
910
911def modefy_2_bin_data(info_from_txt, write_in, ddrbin_index, version):
912    global rk3528_skew_info
913
914    if version < 2:
915        for key, value in info_from_txt.items():
916            if value['version'] <= version:
917                for i in range(len(write_in)):
918                    if value['v0_info'][0] == write_in[i][0]:
919                        write_in[i][1] |= (value['value'] << value['v0_info'][1])
920    elif version <= version_max:
921        for index_name in ddrbin_index:
922            head_info_name = index_name[:-6]+'_info'
923            if ddrbin_index[index_name]['offset'] != 0 and 'skew' not in index_name:
924                position_name = 'null'
925                for key, value in info_from_txt.items():
926                    if value['index'] == index_name and value['version'] <= version:
927                        if position_name != value['position']:
928                            position_name = value['position']
929                            position_value = 0
930                        position_value |= (value['value'] << value['shift'])
931                        write_in[head_info_name][value['position']] = position_value
932                        #print(f"D: {key} = {value}, {value['position']}={position_value}")
933            elif ddrbin_index[index_name]['offset'] != 0 and 'skew' in index_name:
934                if chip_info == 'rk3528':
935                    write_in.update({'skew_info' : rk3528_skew_info})
936                    if rk3528_skew_info['skew_sub_version'] == 0x1:
937                        for key, value in info_from_txt.items():
938                            if value['index'] == index_name and value['version'] <= version:
939                                position_1 = value['position'][ : value['position'].find('_')]
940                                position_2 = value['position'][value['position'].find('_') + 1 : ]
941                                if position_1 in list(write_in[head_info_name].keys()):
942                                    temp_value =  write_in[head_info_name][position_1][position_2]
943                                    temp_value &= ~(value['mask'] << value['shift'])
944                                    temp_value |= value['value'] << value['shift']
945                                    write_in[head_info_name][position_1][position_2] = temp_value
946                                    #print(f"D: {key} = {value}, {temp_value}")
947
948    #print(f"D: write_in = {write_in}")
949    return 0
950
951
952def write_in_bin_data_v2(filebin, bin_skew_offset, write_in, ddrbin_index, info_from_txt, version):
953    for index_name in ddrbin_index:
954        head_info_name = index_name[:-6]+'_info'
955        if ddrbin_index[index_name]['offset'] != 0 and 'skew' not in index_name:
956            filebin.seek(bin_skew_offset + (ddrbin_index[index_name]['offset'] - 1) * 4)
957            index_size = ddrbin_index[index_name]['size']
958            for key in write_in[head_info_name]:
959                if index_size > 0:
960                    try:
961                        filebin.write(write_in[head_info_name][key].to_bytes(4,byteorder='little'))
962                        #print(f"D: {head_info_name} {key} = {write_in[head_info_name][key]}")
963                        index_size -= 1
964                    except:
965                        print("write bin {} to file fail".format(head_info_name))
966                        return -1
967        elif ddrbin_index[index_name]['offset'] != 0 and 'skew' in index_name:
968            if chip_info == 'rk3528' and write_in[head_info_name]["skew_sub_version"] == 1:
969                filebin.seek(bin_skew_offset + (ddrbin_index[index_name]['offset'] - 1) * 4)
970                index_size = ddrbin_index[index_name]['size']
971                for key in write_in[head_info_name]:
972                    if key == 'skew_sub_version':
973                        temp_value = write_in[head_info_name]["skew_sub_version"]
974                        filebin.write(temp_value.to_bytes(4,byteorder='little'))
975                        continue
976                    for key_1 in write_in[head_info_name][key]:
977                        if index_size > 0:
978                            try:
979                                temp_value = write_in[head_info_name][key][key_1]
980                                #print(f"D: {head_info_name} {key}.{key_1} = {temp_value}")
981                                filebin.write(temp_value.to_bytes(4,byteorder='little'))
982                                index_size -= 1
983                            except:
984                                print("write bin {} to file fail".format(head_info_name))
985                                return -1
986
987    return 0
988
989
990#info from bin + info from txt generate to loader parameters
991def txt_data_2_bin_data(info_from_txt, info_from_bin, ddrbin_index, write_in, version):
992    print("\nnew bin config:")
993
994    for key, value in info_from_txt.items():
995        if key == 'start tag':
996            continue
997        if (info_from_txt[key]['value'] == 0) and (key not in update_key_list):
998            info_from_txt[key]['value'] = info_from_bin[key]['value']
999        else:
1000            if info_from_txt[key]['num_base'] == 'hex':
1001                print("{}: {}".format(key, hex(info_from_txt[key]['value'])))
1002            else:
1003                print("{}: {}".format(key, info_from_txt[key]['value']))
1004    #print(info_from_txt)
1005
1006    modefy_2_bin_data(info_from_txt, write_in, ddrbin_index, version)
1007
1008    return 0
1009
1010
1011def bin_data_readout(filebin, ddrbin_index, read_out, bin_skew_offset, version, info_from_txt):
1012    global rk3528_skew_info
1013
1014    if version < 2:
1015        for i in range(len(read_out)):
1016            try:
1017                read_out[i][1] = int.from_bytes(filebin.read(4), byteorder='little')
1018                #print(f"D: read_out {hex(read_out[i][0])} = {read_out[i][1]}")
1019            except:
1020                print("read bin file fail")
1021                return -1
1022    elif version <= version_max:
1023        for index_name in ddrbin_index:
1024            head_info_name = index_name[:-6]+'_info'
1025            if ddrbin_index[index_name]['offset'] != 0 and 'skew' not in index_name:
1026                filebin.seek(bin_skew_offset + (ddrbin_index[index_name]['offset'] - 1) * 4)
1027                index_size = ddrbin_index[index_name]['size']
1028                for key in read_out[head_info_name]:
1029                    if index_size > 0:
1030                        try:
1031                            temp_value = int.from_bytes(filebin.read(4), byteorder='little')
1032                            read_out[head_info_name][key] = temp_value
1033                            #print(f"D: {head_info_name} {key} = {read_out[head_info_name][key]}")
1034                            index_size -= 1
1035                        except:
1036                            print("read {} from bin file fail".format(head_info_name))
1037                            return -1
1038            elif ddrbin_index[index_name]['offset'] != 0 and 'skew' in index_name:
1039                try:
1040                    filebin.seek(bin_skew_offset + (ddrbin_index[index_name]['offset'] - 1) * 4)
1041                    skew_sub_ver = int.from_bytes(filebin.read(4), byteorder='little') & 0xff
1042                except:
1043                    print("read skew_sub_ver from bin file fail")
1044                    return -1
1045                if chip_info == 'rk3528' and skew_sub_ver == 0x1:
1046                    for i in rk3528_skew_info:
1047                        if i == 'skew_sub_version':
1048                            rk3528_skew_info[i] = skew_sub_ver
1049                            continue
1050                        for j in rk3528_skew_info[i]:
1051                            try:
1052                                temp_value = int.from_bytes(filebin.read(4), byteorder='little')
1053                                rk3528_skew_info[i][j] = temp_value
1054                                #print(f"D: {i}.{j}={rk3528_skew_info[i][j]}")
1055                            except:
1056                                print("read {} from bin file fail".format(head_info_name))
1057                                return -1
1058
1059                read_out.update({'skew_info' : rk3528_skew_info})
1060
1061    return 0
1062
1063
1064def gen_info_from_bin(filegen_path, info_from_bin, verinfo_full, version):
1065    with open(filegen_path, 'w+', encoding='utf-8') as file:
1066        file.write('/* ' + verinfo_full + ' */\n')
1067
1068    with open(filegen_path, 'a', encoding='utf-8') as file:
1069        for key, value in info_from_bin.items():
1070            if "reserved" in key:
1071                continue
1072
1073            if value['num_base'] == 'hex':
1074                value_str = str(hex(value['value']))
1075            else:
1076                value_str = str(value['value'])
1077
1078            write_buff = key + '=' + value_str
1079            #print(f"D: {write_buff}")
1080            file.write(write_buff + '\n')
1081
1082    with open(filegen_path, 'a', encoding='utf-8') as file:
1083        file.write('end' + '\n')
1084
1085    return 0
1086
1087
1088def print_help():
1089    print(
1090        "For more details, please refer to the ddrbin_tool_user_guide.txt\n"\
1091        "This tools support two functions\n"\
1092        "for example:\n"\
1093        "function 1: modify ddr.bin file from ddrbin_param.txt.\n"\
1094        "	1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want.\n"\
1095        "	If want to keep items default, please keep these items blank.\n"\
1096        "	The date & time in the version information will be updated by default.\n"\
1097        "	like: ./ddrbin_tool px30 ddrbin_param.txt px30_ddr_333MHz_v1.13.bin\n"\
1098        "\n"\
1099        "	OPTION: --verinfo_editable=TEXT		The TEXT(max 17 chars) will replace\n"\
1100        "						the date & time in the version information.\n"\
1101        "	like: ./ddrbin_tool px30 ddrbin_param.txt px30_ddr_333MHz_v1.13.bin [OPTION]\n"\
1102        "\n"\
1103        "function 2: get ddr.bin file config to gen_param.txt file\n"\
1104        "	If want to get ddrbin file config, please run like that:\n"\
1105        "	./ddrbin_tool px30 -g gen_param.txt px30_ddr_333MHz_v1.15.bin\n"\
1106        "	The config will show in gen_param.txt.\n"\
1107        "\n"\
1108        "Note:	The function 1 and function 2 are two separate functions\n"\
1109        "The gen_param.txt file which is generated by function 2 is no need used in function 1.\n"\
1110        "\n"\
1111        "For more details, please refer to the ddrbin_tool_user_guide.txt\n"\
1112    )
1113
1114
1115def ddrbin_tool(argc, argv):
1116    global updata_key_list
1117    global chip_info
1118
1119    info_from_txt = copy.deepcopy(base_info_full)
1120    info_from_bin = copy.deepcopy(base_info_full)
1121    ddrbin_index = copy.deepcopy(sdram_head_info_index_v2)
1122
1123    version_old_hit = 0
1124    gen_txt_from_bin = 0
1125
1126    verinfo_full = ''
1127    verinfo_full_offset = 0
1128    verinfo_full_length = 0
1129    verinfo_editable = ''
1130    verinfo_editable_offset = 0
1131    verinfo_editable_length = 17
1132
1133    print("version v1.21 20241211")
1134    print("python {}, {}, {}".format(sys.version.split(' ', 1)[0], platform.system(), platform.machine()))
1135    if sys.version_info < (3, 6):
1136        print("Warning: Please installed Python 3.6 or later.")
1137
1138    if argc == 1:
1139        print_help()
1140        return -1
1141
1142    chip_info = argv[1]
1143    if chip_info not in chip_list:
1144        chip_info = 'others chip'
1145    print("chip: {}".format(chip_info))
1146
1147    try:
1148        opts, args = getopt.gnu_getopt(argv, 'g:h', ['verinfo_editable='])
1149    except:
1150        print_help()
1151        return -1
1152
1153    for opt, arg in opts:
1154        if opt == '-g':
1155            gen_txt_from_bin = 1
1156            filegen_path = arg
1157        elif opt == '--verinfo_editable':
1158            verinfo_editable = arg
1159            if len(verinfo_editable) > verinfo_editable_length:
1160                print("The character count of 'verinfo_editable' exceeds the allowed limit of 17.")
1161                return -1
1162        elif opt == '-h':
1163            print_help()
1164            return -1
1165
1166    if gen_txt_from_bin == 1:
1167        # function: get ddr.bin file config to gen_param.txt file
1168        if argc < 5:
1169            print("The number of parameters error")
1170            print_help()
1171            return -1
1172
1173        filebin_path = argv[4]
1174        if os.path.exists(filebin_path) != True:
1175            print("The file {} not exist".format(filebin_path))
1176            return -1
1177
1178        #print(f"D: filegen_path={filegen_path}, {filebin_path}")
1179    else:
1180        # function: modify ddr.bin file from ddrbin_param.txt.
1181        if argc < 4:
1182            print("The number of parameters error")
1183            print_help()
1184            return -1
1185
1186        fileskew_path = argv[2]
1187        if os.path.exists(fileskew_path) != True:
1188            print("The file {} not exist".format(fileskew_path))
1189            return -1
1190
1191        filebin_path = argv[3]
1192        if os.path.exists(filebin_path) != True:
1193            print("The file {} not exist".format(filebin_path))
1194            return -1
1195
1196        for key in version_old_list:
1197            if key in argv[3]:
1198                version_old_hit = 1
1199        #print(f"D: fileskew_path={fileskew_path},{filebin_path},version_old_hit={version_old_hit}")
1200
1201    if gen_txt_from_bin != 1:
1202        # Read the parameters that need to be modified from the txt file.
1203        key_list = list(info_from_txt.keys())
1204        hot = 0
1205        try:
1206            with open(fileskew_path,'r', encoding='UTF-8') as file:
1207                for line in file:
1208                    if '/*' in line:
1209                        continue
1210
1211                    if '=' in line:
1212                        index_of_line = line.find('=')
1213                        if line[index_of_line : ].strip() != '=':
1214                            info_dict_key = line[ : index_of_line]
1215                            info_dict_value = line[index_of_line + 1 : -1]
1216
1217                            if '0x' in info_dict_value:
1218                                info_dict_value = int(info_dict_value[2:], 16)
1219                            else:
1220                                info_dict_value = int(info_dict_value)
1221
1222                            info_from_txt[info_dict_key]['value'] = info_dict_value
1223
1224                            # append info_dict_key to update_key_list, need updata value from txt
1225                            update_key_list.append(info_dict_key)
1226                            #print(f"D: update_key_list append, {info_dict_key}={info_dict_value}")
1227
1228                        hot = hot + 1
1229        except (KeyError, ValueError):
1230            print("KeyError or ValueError: {}={}".format(info_dict_key, info_dict_value))
1231            return -1
1232        except Exception:
1233            print("The file {} read failed".format(fileskew_path))
1234            return -1
1235
1236        if hot == 0:
1237            print("Failed to read DRAM parameters from the file")
1238            return -1
1239    else:
1240        info_from_txt['start tag']['value'] = 0x12345678
1241
1242    # get info from bin file
1243    with open(filebin_path, 'rb') as file:
1244        content = file.read()
1245    # convert the target byte sequence 'start tag' into bytes, byteorder little
1246    target_bytes = struct.pack('<I', info_from_txt['start tag']['value'])
1247    start_position = 0
1248    while True:
1249        position = content.find(target_bytes, start_position)
1250        if position == -1:
1251            break
1252
1253        version = int.from_bytes(content[position + 4: position + 8], byteorder='little')
1254        if version >= 0 and version <= version_max:
1255            break
1256        else:
1257            start_position = position + len(target_bytes)
1258
1259    if position == -1:
1260        if start_position == 0:
1261            print("Find the 'start tag' in the ddrbin file failed")
1262        else:
1263            print("version = {}, invalid.".format(version))
1264            if version > version_max and version < (version_max + 5):
1265                print("Please check if there is a new version of the tool available.")
1266        return -1
1267
1268    # get ddrbin parameters version
1269    try:
1270        bin_skew_offset = position + 4
1271        filebin = open(filebin_path, 'rb+')
1272        filebin.seek(bin_skew_offset)
1273        version = int.from_bytes(filebin.read(4), byteorder='little')
1274    except:
1275        print("get version fail")
1276        filebin.close()
1277        return -1
1278
1279    print("version {}".format(version))
1280
1281    # get ddrbin version information from bin file
1282    # eg: DDR 03ea844c5d typ 24/09/03-10:42:57,fwver: v1.23
1283    target_bytes = b'DDR '
1284    target_bytes_1 = b',fwver:'
1285    start_position = 0
1286    while True:
1287        position = content.find(target_bytes, start_position)
1288        position_1 = content.find(target_bytes_1, start_position)
1289        if position == -1 or position_1 == -1:
1290            break
1291        elif (position_1 - position) < 100:
1292            verinfo_full = content[position: position_1+30].decode('utf-8', errors='replace')
1293            verinfo_full = verinfo_full[:verinfo_full.find('\n')]
1294            if content[position_1 - verinfo_editable_length - 1].to_bytes(1, 'little') == b' ':
1295                verinfo_editable_offset = position_1 - verinfo_editable_length
1296                verinfo_full_offset = position
1297                verinfo_full_length = len(verinfo_full.encode('utf-8'))
1298                print("{}".format(verinfo_full))
1299                break
1300        else:
1301            start_position = position + len(target_bytes)
1302
1303    if version < 2:
1304        read_out = copy.deepcopy(sdram_head_info_v0)
1305        write_in = copy.deepcopy(sdram_head_info_v0)
1306
1307        # skip gcpu_gen_freq after version_info
1308        filebin.seek(bin_skew_offset + 8)
1309    elif version <= 5:
1310        if version >= 3:
1311            ddrbin_index.update(sdram_head_info_index_v2_3)
1312        if version >= 4:
1313            ddrbin_index.update(sdram_head_info_index_v3_4)
1314
1315        if version < 5:
1316            read_out = copy.deepcopy(sdram_head_info_v2)
1317            write_in = copy.deepcopy(sdram_head_info_v2)
1318        else:
1319            read_out = copy.deepcopy(sdram_head_info_v5)
1320            write_in = copy.deepcopy(sdram_head_info_v5)
1321
1322        #index_info read out
1323        for key in ddrbin_index:
1324            try:
1325                ddrbin_index[key]['offset'] = int.from_bytes(filebin.read(1), byteorder='little')
1326                ddrbin_index[key]['size'] = int.from_bytes(filebin.read(1), byteorder='little')
1327            except:
1328                filebin.close()
1329                print("readout ddrbin_index fail")
1330                return -1
1331            #print(f"D: {key} = {index[key]}",ddrbin_index[key]["offset"],ddrbin_index[key]["size"])
1332    else:
1333        filebin.close()
1334        print("version not support")
1335        return -1
1336
1337    if bin_data_readout(filebin, ddrbin_index, read_out, bin_skew_offset, version, info_from_txt) != 0:
1338        filebin.close()
1339        print("bin_data_readout failed")
1340        return -1
1341
1342    bin_data_2_info(info_from_bin, read_out, ddrbin_index, version, info_from_txt)
1343    if gen_txt_from_bin == 1:
1344        if gen_info_from_bin(filegen_path, info_from_bin, verinfo_full, version) == 0:
1345            print("generate info from bin file ok.")
1346            filebin.close()
1347            return 0
1348        else:
1349            print("generate info fail.")
1350            filebin.close()
1351            return -1
1352
1353    txt_data_2_bin_data(info_from_txt, info_from_bin, ddrbin_index, write_in, version)
1354
1355    if version < 2:
1356        if version_old_hit == 0:
1357            filebin.seek(bin_skew_offset + 8)
1358            for i in range(len(write_in)):
1359                try:
1360                    filebin.write(write_in[i][1].to_bytes(4,byteorder='little'))
1361                except:
1362                    print("write bin file fail")
1363        else:
1364            filebin.seek(bin_skew_offset + 20)
1365            for i in range(3, len(write_in)):
1366                try:
1367                    filebin.write(write_in[i][1].to_bytes(4,byteorder='little'))
1368                except:
1369                    print("write bin file fail")
1370    elif version <= version_max:
1371        write_in_bin_data_v2(filebin, bin_skew_offset, write_in, ddrbin_index, info_from_txt, version)
1372    print("modify end\n")
1373
1374    # update ddrbin version information to bin file
1375    if verinfo_editable_offset != 0:
1376        if verinfo_editable == '':
1377            #print(f"position_1={position_1}, position_2={position_2}, {old_verinfo_editable}")
1378            current_time = datetime.now()
1379            verinfo_editable = current_time.strftime("%y/%m/%d-%H:%M.%S")
1380        if len(verinfo_editable) < verinfo_editable_length:
1381            verinfo_editable = verinfo_editable.ljust(verinfo_editable_length)
1382
1383        verinfo_editable_bytes = verinfo_editable.encode('utf-8')[:verinfo_editable_length]
1384        try:
1385            filebin.seek(verinfo_editable_offset)
1386            filebin.write(verinfo_editable_bytes)
1387            filebin.seek(verinfo_full_offset)
1388            new_verinfo_full = filebin.read(verinfo_full_length).decode('utf-8', errors='replace')
1389            print("new ddrbin version information: {}".format(new_verinfo_full))
1390        except:
1391            print("change verinfo_editable error")
1392
1393    filebin.close()
1394
1395    return 0
1396
1397
1398if __name__ == '__main__':
1399    #print(f"D: argc = {len(sys.argv)}, argv = {sys.argv}")
1400    ddrbin_tool(len(sys.argv), sys.argv)
1401
1402