1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * (C) Copyright 2002 3a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4a47a12beSStefan Roese * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6a47a12beSStefan Roese */ 7a47a12beSStefan Roese 8a47a12beSStefan Roese #include <common.h> 9a47a12beSStefan Roese 10a47a12beSStefan Roese /* 11a47a12beSStefan Roese * CPU test 12a47a12beSStefan Roese * Binary instructions instr rD,rA 13a47a12beSStefan Roese * 14a47a12beSStefan Roese * Logic instructions: neg 15a47a12beSStefan Roese * Arithmetic instructions: addme, addze, subfme, subfze 16a47a12beSStefan Roese 17a47a12beSStefan Roese * The test contains a pre-built table of instructions, operands and 18a47a12beSStefan Roese * expected results. For each table entry, the test will cyclically use 19a47a12beSStefan Roese * different sets of operand registers and result registers. 20a47a12beSStefan Roese */ 21a47a12beSStefan Roese 22a47a12beSStefan Roese #include <post.h> 23a47a12beSStefan Roese #include "cpu_asm.h" 24a47a12beSStefan Roese 25a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 26a47a12beSStefan Roese 27a47a12beSStefan Roese extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); 28a47a12beSStefan Roese extern ulong cpu_post_makecr (long v); 29a47a12beSStefan Roese 30a47a12beSStefan Roese static struct cpu_post_two_s 31a47a12beSStefan Roese { 32a47a12beSStefan Roese ulong cmd; 33a47a12beSStefan Roese ulong op; 34a47a12beSStefan Roese ulong res; 35a47a12beSStefan Roese } cpu_post_two_table[] = 36a47a12beSStefan Roese { 37a47a12beSStefan Roese { 38a47a12beSStefan Roese OP_NEG, 39a47a12beSStefan Roese 3, 40a47a12beSStefan Roese -3 41a47a12beSStefan Roese }, 42a47a12beSStefan Roese { 43a47a12beSStefan Roese OP_NEG, 44a47a12beSStefan Roese 5, 45a47a12beSStefan Roese -5 46a47a12beSStefan Roese }, 47a47a12beSStefan Roese { 48a47a12beSStefan Roese OP_ADDME, 49a47a12beSStefan Roese 6, 50a47a12beSStefan Roese 5 51a47a12beSStefan Roese }, 52a47a12beSStefan Roese { 53a47a12beSStefan Roese OP_ADDZE, 54a47a12beSStefan Roese 5, 55a47a12beSStefan Roese 5 56a47a12beSStefan Roese }, 57a47a12beSStefan Roese { 58a47a12beSStefan Roese OP_SUBFME, 59a47a12beSStefan Roese 6, 60a47a12beSStefan Roese ~6 - 1 61a47a12beSStefan Roese }, 62a47a12beSStefan Roese { 63a47a12beSStefan Roese OP_SUBFZE, 64a47a12beSStefan Roese 5, 65a47a12beSStefan Roese ~5 66a47a12beSStefan Roese }, 67a47a12beSStefan Roese }; 68d2397817SMike Frysinger static unsigned int cpu_post_two_size = ARRAY_SIZE(cpu_post_two_table); 69a47a12beSStefan Roese 70a47a12beSStefan Roese int cpu_post_test_two (void) 71a47a12beSStefan Roese { 72a47a12beSStefan Roese int ret = 0; 73a47a12beSStefan Roese unsigned int i, reg; 74a47a12beSStefan Roese int flag = disable_interrupts(); 75a47a12beSStefan Roese 76a47a12beSStefan Roese for (i = 0; i < cpu_post_two_size && ret == 0; i++) 77a47a12beSStefan Roese { 78a47a12beSStefan Roese struct cpu_post_two_s *test = cpu_post_two_table + i; 79a47a12beSStefan Roese 80a47a12beSStefan Roese for (reg = 0; reg < 32 && ret == 0; reg++) 81a47a12beSStefan Roese { 82a47a12beSStefan Roese unsigned int reg0 = (reg + 0) % 32; 83a47a12beSStefan Roese unsigned int reg1 = (reg + 1) % 32; 84a47a12beSStefan Roese unsigned int stk = reg < 16 ? 31 : 15; 85a47a12beSStefan Roese unsigned long code[] = 86a47a12beSStefan Roese { 87a47a12beSStefan Roese ASM_STW(stk, 1, -4), 88a47a12beSStefan Roese ASM_ADDI(stk, 1, -16), 89a47a12beSStefan Roese ASM_STW(3, stk, 8), 90a47a12beSStefan Roese ASM_STW(reg0, stk, 4), 91a47a12beSStefan Roese ASM_STW(reg1, stk, 0), 92a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8), 93a47a12beSStefan Roese ASM_11(test->cmd, reg1, reg0), 94a47a12beSStefan Roese ASM_STW(reg1, stk, 8), 95a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0), 96a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4), 97a47a12beSStefan Roese ASM_LWZ(3, stk, 8), 98a47a12beSStefan Roese ASM_ADDI(1, stk, 16), 99a47a12beSStefan Roese ASM_LWZ(stk, 1, -4), 100a47a12beSStefan Roese ASM_BLR, 101a47a12beSStefan Roese }; 102a47a12beSStefan Roese unsigned long codecr[] = 103a47a12beSStefan Roese { 104a47a12beSStefan Roese ASM_STW(stk, 1, -4), 105a47a12beSStefan Roese ASM_ADDI(stk, 1, -16), 106a47a12beSStefan Roese ASM_STW(3, stk, 8), 107a47a12beSStefan Roese ASM_STW(reg0, stk, 4), 108a47a12beSStefan Roese ASM_STW(reg1, stk, 0), 109a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8), 110a47a12beSStefan Roese ASM_11(test->cmd, reg1, reg0) | BIT_C, 111a47a12beSStefan Roese ASM_STW(reg1, stk, 8), 112a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0), 113a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4), 114a47a12beSStefan Roese ASM_LWZ(3, stk, 8), 115a47a12beSStefan Roese ASM_ADDI(1, stk, 16), 116a47a12beSStefan Roese ASM_LWZ(stk, 1, -4), 117a47a12beSStefan Roese ASM_BLR, 118a47a12beSStefan Roese }; 119a47a12beSStefan Roese ulong res; 120a47a12beSStefan Roese ulong cr; 121a47a12beSStefan Roese 122a47a12beSStefan Roese if (ret == 0) 123a47a12beSStefan Roese { 124a47a12beSStefan Roese cr = 0; 125a47a12beSStefan Roese cpu_post_exec_21 (code, & cr, & res, test->op); 126a47a12beSStefan Roese 127a47a12beSStefan Roese ret = res == test->res && cr == 0 ? 0 : -1; 128a47a12beSStefan Roese 129a47a12beSStefan Roese if (ret != 0) 130a47a12beSStefan Roese { 131a47a12beSStefan Roese post_log ("Error at two test %d !\n", i); 132a47a12beSStefan Roese } 133a47a12beSStefan Roese } 134a47a12beSStefan Roese 135a47a12beSStefan Roese if (ret == 0) 136a47a12beSStefan Roese { 137a47a12beSStefan Roese cpu_post_exec_21 (codecr, & cr, & res, test->op); 138a47a12beSStefan Roese 139a47a12beSStefan Roese ret = res == test->res && 140a47a12beSStefan Roese (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; 141a47a12beSStefan Roese 142a47a12beSStefan Roese if (ret != 0) 143a47a12beSStefan Roese { 144a47a12beSStefan Roese post_log ("Error at two test %d !\n", i); 145a47a12beSStefan Roese } 146a47a12beSStefan Roese } 147a47a12beSStefan Roese } 148a47a12beSStefan Roese } 149a47a12beSStefan Roese 150a47a12beSStefan Roese if (flag) 151a47a12beSStefan Roese enable_interrupts(); 152a47a12beSStefan Roese 153a47a12beSStefan Roese return ret; 154a47a12beSStefan Roese } 155a47a12beSStefan Roese 156a47a12beSStefan Roese #endif 157