xref: /rk3399_rockchip-uboot/post/lib_powerpc/threex.c (revision 1a4596601fd395f3afb8f82f3f840c5e00bdd57a) 
1a47a12beSStefan Roese /*
2a47a12beSStefan Roese  * (C) Copyright 2002
3a47a12beSStefan Roese  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4a47a12beSStefan Roese  *
5*1a459660SWolfgang Denk  * SPDX-License-Identifier:	GPL-2.0+
6a47a12beSStefan Roese  */
7a47a12beSStefan Roese 
8a47a12beSStefan Roese #include <common.h>
9a47a12beSStefan Roese 
10a47a12beSStefan Roese /*
11a47a12beSStefan Roese  * CPU test
12a47a12beSStefan Roese  * Ternary instructions		instr rA,rS,rB
13a47a12beSStefan Roese  *
14a47a12beSStefan Roese  * Logic instructions:		or, orc, xor, nand, nor, eqv
15a47a12beSStefan Roese  * Shift instructions:		slw, srw, sraw
16a47a12beSStefan Roese  *
17a47a12beSStefan Roese  * The test contains a pre-built table of instructions, operands and
18a47a12beSStefan Roese  * expected results. For each table entry, the test will cyclically use
19a47a12beSStefan Roese  * different sets of operand registers and result registers.
20a47a12beSStefan Roese  */
21a47a12beSStefan Roese 
22a47a12beSStefan Roese #include <post.h>
23a47a12beSStefan Roese #include "cpu_asm.h"
24a47a12beSStefan Roese 
25a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU
26a47a12beSStefan Roese 
27a47a12beSStefan Roese extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
28a47a12beSStefan Roese     ulong op2);
29a47a12beSStefan Roese extern ulong cpu_post_makecr (long v);
30a47a12beSStefan Roese 
31a47a12beSStefan Roese static struct cpu_post_threex_s
32a47a12beSStefan Roese {
33a47a12beSStefan Roese     ulong cmd;
34a47a12beSStefan Roese     ulong op1;
35a47a12beSStefan Roese     ulong op2;
36a47a12beSStefan Roese     ulong res;
37a47a12beSStefan Roese } cpu_post_threex_table[] =
38a47a12beSStefan Roese {
39a47a12beSStefan Roese     {
40a47a12beSStefan Roese 	OP_OR,
41a47a12beSStefan Roese 	0x1234,
42a47a12beSStefan Roese 	0x5678,
43a47a12beSStefan Roese 	0x1234 | 0x5678
44a47a12beSStefan Roese     },
45a47a12beSStefan Roese     {
46a47a12beSStefan Roese 	OP_ORC,
47a47a12beSStefan Roese 	0x1234,
48a47a12beSStefan Roese 	0x5678,
49a47a12beSStefan Roese 	0x1234 | ~0x5678
50a47a12beSStefan Roese     },
51a47a12beSStefan Roese     {
52a47a12beSStefan Roese 	OP_XOR,
53a47a12beSStefan Roese 	0x1234,
54a47a12beSStefan Roese 	0x5678,
55a47a12beSStefan Roese 	0x1234 ^ 0x5678
56a47a12beSStefan Roese     },
57a47a12beSStefan Roese     {
58a47a12beSStefan Roese 	OP_NAND,
59a47a12beSStefan Roese 	0x1234,
60a47a12beSStefan Roese 	0x5678,
61a47a12beSStefan Roese 	~(0x1234 & 0x5678)
62a47a12beSStefan Roese     },
63a47a12beSStefan Roese     {
64a47a12beSStefan Roese 	OP_NOR,
65a47a12beSStefan Roese 	0x1234,
66a47a12beSStefan Roese 	0x5678,
67a47a12beSStefan Roese 	~(0x1234 | 0x5678)
68a47a12beSStefan Roese     },
69a47a12beSStefan Roese     {
70a47a12beSStefan Roese 	OP_EQV,
71a47a12beSStefan Roese 	0x1234,
72a47a12beSStefan Roese 	0x5678,
73a47a12beSStefan Roese 	~(0x1234 ^ 0x5678)
74a47a12beSStefan Roese     },
75a47a12beSStefan Roese     {
76a47a12beSStefan Roese 	OP_SLW,
77a47a12beSStefan Roese 	0x80,
78a47a12beSStefan Roese 	16,
79a47a12beSStefan Roese 	0x800000
80a47a12beSStefan Roese     },
81a47a12beSStefan Roese     {
82a47a12beSStefan Roese 	OP_SLW,
83a47a12beSStefan Roese 	0x80,
84a47a12beSStefan Roese 	32,
85a47a12beSStefan Roese 	0
86a47a12beSStefan Roese     },
87a47a12beSStefan Roese     {
88a47a12beSStefan Roese 	OP_SRW,
89a47a12beSStefan Roese 	0x800000,
90a47a12beSStefan Roese 	16,
91a47a12beSStefan Roese 	0x80
92a47a12beSStefan Roese     },
93a47a12beSStefan Roese     {
94a47a12beSStefan Roese 	OP_SRW,
95a47a12beSStefan Roese 	0x800000,
96a47a12beSStefan Roese 	32,
97a47a12beSStefan Roese 	0
98a47a12beSStefan Roese     },
99a47a12beSStefan Roese     {
100a47a12beSStefan Roese 	OP_SRAW,
101a47a12beSStefan Roese 	0x80000000,
102a47a12beSStefan Roese 	3,
103a47a12beSStefan Roese 	0xf0000000
104a47a12beSStefan Roese     },
105a47a12beSStefan Roese     {
106a47a12beSStefan Roese 	OP_SRAW,
107a47a12beSStefan Roese 	0x8000,
108a47a12beSStefan Roese 	3,
109a47a12beSStefan Roese 	0x1000
110a47a12beSStefan Roese     },
111a47a12beSStefan Roese };
112d2397817SMike Frysinger static unsigned int cpu_post_threex_size = ARRAY_SIZE(cpu_post_threex_table);
113a47a12beSStefan Roese 
114a47a12beSStefan Roese int cpu_post_test_threex (void)
115a47a12beSStefan Roese {
116a47a12beSStefan Roese     int ret = 0;
117a47a12beSStefan Roese     unsigned int i, reg;
118a47a12beSStefan Roese     int flag = disable_interrupts();
119a47a12beSStefan Roese 
120a47a12beSStefan Roese     for (i = 0; i < cpu_post_threex_size && ret == 0; i++)
121a47a12beSStefan Roese     {
122a47a12beSStefan Roese 	struct cpu_post_threex_s *test = cpu_post_threex_table + i;
123a47a12beSStefan Roese 
124a47a12beSStefan Roese 	for (reg = 0; reg < 32 && ret == 0; reg++)
125a47a12beSStefan Roese 	{
126a47a12beSStefan Roese 	    unsigned int reg0 = (reg + 0) % 32;
127a47a12beSStefan Roese 	    unsigned int reg1 = (reg + 1) % 32;
128a47a12beSStefan Roese 	    unsigned int reg2 = (reg + 2) % 32;
129a47a12beSStefan Roese 	    unsigned int stk = reg < 16 ? 31 : 15;
130a47a12beSStefan Roese 	    unsigned long code[] =
131a47a12beSStefan Roese 	    {
132a47a12beSStefan Roese 		ASM_STW(stk, 1, -4),
133a47a12beSStefan Roese 		ASM_ADDI(stk, 1, -24),
134a47a12beSStefan Roese 		ASM_STW(3, stk, 12),
135a47a12beSStefan Roese 		ASM_STW(4, stk, 16),
136a47a12beSStefan Roese 		ASM_STW(reg0, stk, 8),
137a47a12beSStefan Roese 		ASM_STW(reg1, stk, 4),
138a47a12beSStefan Roese 		ASM_STW(reg2, stk, 0),
139a47a12beSStefan Roese 		ASM_LWZ(reg1, stk, 12),
140a47a12beSStefan Roese 		ASM_LWZ(reg0, stk, 16),
141a47a12beSStefan Roese 		ASM_12X(test->cmd, reg2, reg1, reg0),
142a47a12beSStefan Roese 		ASM_STW(reg2, stk, 12),
143a47a12beSStefan Roese 		ASM_LWZ(reg2, stk, 0),
144a47a12beSStefan Roese 		ASM_LWZ(reg1, stk, 4),
145a47a12beSStefan Roese 		ASM_LWZ(reg0, stk, 8),
146a47a12beSStefan Roese 		ASM_LWZ(3, stk, 12),
147a47a12beSStefan Roese 		ASM_ADDI(1, stk, 24),
148a47a12beSStefan Roese 		ASM_LWZ(stk, 1, -4),
149a47a12beSStefan Roese 		ASM_BLR,
150a47a12beSStefan Roese 	    };
151a47a12beSStefan Roese 	    unsigned long codecr[] =
152a47a12beSStefan Roese 	    {
153a47a12beSStefan Roese 		ASM_STW(stk, 1, -4),
154a47a12beSStefan Roese 		ASM_ADDI(stk, 1, -24),
155a47a12beSStefan Roese 		ASM_STW(3, stk, 12),
156a47a12beSStefan Roese 		ASM_STW(4, stk, 16),
157a47a12beSStefan Roese 		ASM_STW(reg0, stk, 8),
158a47a12beSStefan Roese 		ASM_STW(reg1, stk, 4),
159a47a12beSStefan Roese 		ASM_STW(reg2, stk, 0),
160a47a12beSStefan Roese 		ASM_LWZ(reg1, stk, 12),
161a47a12beSStefan Roese 		ASM_LWZ(reg0, stk, 16),
162a47a12beSStefan Roese 		ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C,
163a47a12beSStefan Roese 		ASM_STW(reg2, stk, 12),
164a47a12beSStefan Roese 		ASM_LWZ(reg2, stk, 0),
165a47a12beSStefan Roese 		ASM_LWZ(reg1, stk, 4),
166a47a12beSStefan Roese 		ASM_LWZ(reg0, stk, 8),
167a47a12beSStefan Roese 		ASM_LWZ(3, stk, 12),
168a47a12beSStefan Roese 		ASM_ADDI(1, stk, 24),
169a47a12beSStefan Roese 		ASM_LWZ(stk, 1, -4),
170a47a12beSStefan Roese 		ASM_BLR,
171a47a12beSStefan Roese 	    };
172a47a12beSStefan Roese 	    ulong res;
173a47a12beSStefan Roese 	    ulong cr;
174a47a12beSStefan Roese 
175a47a12beSStefan Roese 	    if (ret == 0)
176a47a12beSStefan Roese 	    {
177a47a12beSStefan Roese 		cr = 0;
178a47a12beSStefan Roese 		cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
179a47a12beSStefan Roese 
180a47a12beSStefan Roese 		ret = res == test->res && cr == 0 ? 0 : -1;
181a47a12beSStefan Roese 
182a47a12beSStefan Roese 		if (ret != 0)
183a47a12beSStefan Roese 		{
184a47a12beSStefan Roese 	            post_log ("Error at threex test %d !\n", i);
185a47a12beSStefan Roese 		}
186a47a12beSStefan Roese 	    }
187a47a12beSStefan Roese 
188a47a12beSStefan Roese 	    if (ret == 0)
189a47a12beSStefan Roese 	    {
190a47a12beSStefan Roese 		cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
191a47a12beSStefan Roese 
192a47a12beSStefan Roese 		ret = res == test->res &&
193a47a12beSStefan Roese 		      (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
194a47a12beSStefan Roese 
195a47a12beSStefan Roese 		if (ret != 0)
196a47a12beSStefan Roese 		{
197a47a12beSStefan Roese 	            post_log ("Error at threex test %d !\n", i);
198a47a12beSStefan Roese 	        }
199a47a12beSStefan Roese 	    }
200a47a12beSStefan Roese 	}
201a47a12beSStefan Roese     }
202a47a12beSStefan Roese 
203a47a12beSStefan Roese     if (flag)
204a47a12beSStefan Roese 	enable_interrupts();
205a47a12beSStefan Roese 
206a47a12beSStefan Roese     return ret;
207a47a12beSStefan Roese }
208a47a12beSStefan Roese 
209a47a12beSStefan Roese #endif
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