1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * (C) Copyright 2002 3a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4a47a12beSStefan Roese * 5a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6a47a12beSStefan Roese * project. 7a47a12beSStefan Roese * 8a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11a47a12beSStefan Roese * the License, or (at your option) any later version. 12a47a12beSStefan Roese * 13a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16a47a12beSStefan Roese * GNU General Public License for more details. 17a47a12beSStefan Roese * 18a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21a47a12beSStefan Roese * MA 02111-1307 USA 22a47a12beSStefan Roese */ 23a47a12beSStefan Roese 24a47a12beSStefan Roese #include <common.h> 25a47a12beSStefan Roese 26a47a12beSStefan Roese /* 27a47a12beSStefan Roese * CPU test 28a47a12beSStefan Roese * Ternary instructions instr rA,rS,UIMM 29a47a12beSStefan Roese * 30a47a12beSStefan Roese * Logic instructions: ori, oris, xori, xoris 31a47a12beSStefan Roese * 32a47a12beSStefan Roese * The test contains a pre-built table of instructions, operands and 33a47a12beSStefan Roese * expected results. For each table entry, the test will cyclically use 34a47a12beSStefan Roese * different sets of operand registers and result registers. 35a47a12beSStefan Roese */ 36a47a12beSStefan Roese 37a47a12beSStefan Roese #include <post.h> 38a47a12beSStefan Roese #include "cpu_asm.h" 39a47a12beSStefan Roese 40a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 41a47a12beSStefan Roese 42a47a12beSStefan Roese extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); 43a47a12beSStefan Roese extern ulong cpu_post_makecr (long v); 44a47a12beSStefan Roese 45a47a12beSStefan Roese static struct cpu_post_threei_s 46a47a12beSStefan Roese { 47a47a12beSStefan Roese ulong cmd; 48a47a12beSStefan Roese ulong op1; 49a47a12beSStefan Roese ushort op2; 50a47a12beSStefan Roese ulong res; 51a47a12beSStefan Roese } cpu_post_threei_table[] = 52a47a12beSStefan Roese { 53a47a12beSStefan Roese { 54a47a12beSStefan Roese OP_ORI, 55a47a12beSStefan Roese 0x80000000, 56a47a12beSStefan Roese 0xffff, 57a47a12beSStefan Roese 0x8000ffff 58a47a12beSStefan Roese }, 59a47a12beSStefan Roese { 60a47a12beSStefan Roese OP_ORIS, 61a47a12beSStefan Roese 0x00008000, 62a47a12beSStefan Roese 0xffff, 63a47a12beSStefan Roese 0xffff8000 64a47a12beSStefan Roese }, 65a47a12beSStefan Roese { 66a47a12beSStefan Roese OP_XORI, 67a47a12beSStefan Roese 0x8000ffff, 68a47a12beSStefan Roese 0xffff, 69a47a12beSStefan Roese 0x80000000 70a47a12beSStefan Roese }, 71a47a12beSStefan Roese { 72a47a12beSStefan Roese OP_XORIS, 73a47a12beSStefan Roese 0x00008000, 74a47a12beSStefan Roese 0xffff, 75a47a12beSStefan Roese 0xffff8000 76a47a12beSStefan Roese }, 77a47a12beSStefan Roese }; 78*d2397817SMike Frysinger static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table); 79a47a12beSStefan Roese 80a47a12beSStefan Roese int cpu_post_test_threei (void) 81a47a12beSStefan Roese { 82a47a12beSStefan Roese int ret = 0; 83a47a12beSStefan Roese unsigned int i, reg; 84a47a12beSStefan Roese int flag = disable_interrupts(); 85a47a12beSStefan Roese 86a47a12beSStefan Roese for (i = 0; i < cpu_post_threei_size && ret == 0; i++) 87a47a12beSStefan Roese { 88a47a12beSStefan Roese struct cpu_post_threei_s *test = cpu_post_threei_table + i; 89a47a12beSStefan Roese 90a47a12beSStefan Roese for (reg = 0; reg < 32 && ret == 0; reg++) 91a47a12beSStefan Roese { 92a47a12beSStefan Roese unsigned int reg0 = (reg + 0) % 32; 93a47a12beSStefan Roese unsigned int reg1 = (reg + 1) % 32; 94a47a12beSStefan Roese unsigned int stk = reg < 16 ? 31 : 15; 95a47a12beSStefan Roese unsigned long code[] = 96a47a12beSStefan Roese { 97a47a12beSStefan Roese ASM_STW(stk, 1, -4), 98a47a12beSStefan Roese ASM_ADDI(stk, 1, -16), 99a47a12beSStefan Roese ASM_STW(3, stk, 8), 100a47a12beSStefan Roese ASM_STW(reg0, stk, 4), 101a47a12beSStefan Roese ASM_STW(reg1, stk, 0), 102a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8), 103a47a12beSStefan Roese ASM_11IX(test->cmd, reg1, reg0, test->op2), 104a47a12beSStefan Roese ASM_STW(reg1, stk, 8), 105a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0), 106a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4), 107a47a12beSStefan Roese ASM_LWZ(3, stk, 8), 108a47a12beSStefan Roese ASM_ADDI(1, stk, 16), 109a47a12beSStefan Roese ASM_LWZ(stk, 1, -4), 110a47a12beSStefan Roese ASM_BLR, 111a47a12beSStefan Roese }; 112a47a12beSStefan Roese ulong res; 113a47a12beSStefan Roese ulong cr; 114a47a12beSStefan Roese 115a47a12beSStefan Roese cr = 0; 116a47a12beSStefan Roese cpu_post_exec_21 (code, & cr, & res, test->op1); 117a47a12beSStefan Roese 118a47a12beSStefan Roese ret = res == test->res && cr == 0 ? 0 : -1; 119a47a12beSStefan Roese 120a47a12beSStefan Roese if (ret != 0) 121a47a12beSStefan Roese { 122a47a12beSStefan Roese post_log ("Error at threei test %d !\n", i); 123a47a12beSStefan Roese } 124a47a12beSStefan Roese } 125a47a12beSStefan Roese } 126a47a12beSStefan Roese 127a47a12beSStefan Roese if (flag) 128a47a12beSStefan Roese enable_interrupts(); 129a47a12beSStefan Roese 130a47a12beSStefan Roese return ret; 131a47a12beSStefan Roese } 132a47a12beSStefan Roese 133a47a12beSStefan Roese #endif 134