1*a47a12beSStefan Roese /* 2*a47a12beSStefan Roese * (C) Copyright 2002 3*a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4*a47a12beSStefan Roese * 5*a47a12beSStefan Roese * See file CREDITS for list of people who contributed to this 6*a47a12beSStefan Roese * project. 7*a47a12beSStefan Roese * 8*a47a12beSStefan Roese * This program is free software; you can redistribute it and/or 9*a47a12beSStefan Roese * modify it under the terms of the GNU General Public License as 10*a47a12beSStefan Roese * published by the Free Software Foundation; either version 2 of 11*a47a12beSStefan Roese * the License, or (at your option) any later version. 12*a47a12beSStefan Roese * 13*a47a12beSStefan Roese * This program is distributed in the hope that it will be useful, 14*a47a12beSStefan Roese * but WITHOUT ANY WARRANTY; without even the implied warranty of 15*a47a12beSStefan Roese * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16*a47a12beSStefan Roese * GNU General Public License for more details. 17*a47a12beSStefan Roese * 18*a47a12beSStefan Roese * You should have received a copy of the GNU General Public License 19*a47a12beSStefan Roese * along with this program; if not, write to the Free Software 20*a47a12beSStefan Roese * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21*a47a12beSStefan Roese * MA 02111-1307 USA 22*a47a12beSStefan Roese */ 23*a47a12beSStefan Roese 24*a47a12beSStefan Roese #include <common.h> 25*a47a12beSStefan Roese 26*a47a12beSStefan Roese /* 27*a47a12beSStefan Roese * CPU test 28*a47a12beSStefan Roese * Ternary instructions instr rA,rS,UIMM 29*a47a12beSStefan Roese * 30*a47a12beSStefan Roese * Logic instructions: ori, oris, xori, xoris 31*a47a12beSStefan Roese * 32*a47a12beSStefan Roese * The test contains a pre-built table of instructions, operands and 33*a47a12beSStefan Roese * expected results. For each table entry, the test will cyclically use 34*a47a12beSStefan Roese * different sets of operand registers and result registers. 35*a47a12beSStefan Roese */ 36*a47a12beSStefan Roese 37*a47a12beSStefan Roese #include <post.h> 38*a47a12beSStefan Roese #include "cpu_asm.h" 39*a47a12beSStefan Roese 40*a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 41*a47a12beSStefan Roese 42*a47a12beSStefan Roese extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); 43*a47a12beSStefan Roese extern ulong cpu_post_makecr (long v); 44*a47a12beSStefan Roese 45*a47a12beSStefan Roese static struct cpu_post_threei_s 46*a47a12beSStefan Roese { 47*a47a12beSStefan Roese ulong cmd; 48*a47a12beSStefan Roese ulong op1; 49*a47a12beSStefan Roese ushort op2; 50*a47a12beSStefan Roese ulong res; 51*a47a12beSStefan Roese } cpu_post_threei_table[] = 52*a47a12beSStefan Roese { 53*a47a12beSStefan Roese { 54*a47a12beSStefan Roese OP_ORI, 55*a47a12beSStefan Roese 0x80000000, 56*a47a12beSStefan Roese 0xffff, 57*a47a12beSStefan Roese 0x8000ffff 58*a47a12beSStefan Roese }, 59*a47a12beSStefan Roese { 60*a47a12beSStefan Roese OP_ORIS, 61*a47a12beSStefan Roese 0x00008000, 62*a47a12beSStefan Roese 0xffff, 63*a47a12beSStefan Roese 0xffff8000 64*a47a12beSStefan Roese }, 65*a47a12beSStefan Roese { 66*a47a12beSStefan Roese OP_XORI, 67*a47a12beSStefan Roese 0x8000ffff, 68*a47a12beSStefan Roese 0xffff, 69*a47a12beSStefan Roese 0x80000000 70*a47a12beSStefan Roese }, 71*a47a12beSStefan Roese { 72*a47a12beSStefan Roese OP_XORIS, 73*a47a12beSStefan Roese 0x00008000, 74*a47a12beSStefan Roese 0xffff, 75*a47a12beSStefan Roese 0xffff8000 76*a47a12beSStefan Roese }, 77*a47a12beSStefan Roese }; 78*a47a12beSStefan Roese static unsigned int cpu_post_threei_size = 79*a47a12beSStefan Roese sizeof (cpu_post_threei_table) / sizeof (struct cpu_post_threei_s); 80*a47a12beSStefan Roese 81*a47a12beSStefan Roese int cpu_post_test_threei (void) 82*a47a12beSStefan Roese { 83*a47a12beSStefan Roese int ret = 0; 84*a47a12beSStefan Roese unsigned int i, reg; 85*a47a12beSStefan Roese int flag = disable_interrupts(); 86*a47a12beSStefan Roese 87*a47a12beSStefan Roese for (i = 0; i < cpu_post_threei_size && ret == 0; i++) 88*a47a12beSStefan Roese { 89*a47a12beSStefan Roese struct cpu_post_threei_s *test = cpu_post_threei_table + i; 90*a47a12beSStefan Roese 91*a47a12beSStefan Roese for (reg = 0; reg < 32 && ret == 0; reg++) 92*a47a12beSStefan Roese { 93*a47a12beSStefan Roese unsigned int reg0 = (reg + 0) % 32; 94*a47a12beSStefan Roese unsigned int reg1 = (reg + 1) % 32; 95*a47a12beSStefan Roese unsigned int stk = reg < 16 ? 31 : 15; 96*a47a12beSStefan Roese unsigned long code[] = 97*a47a12beSStefan Roese { 98*a47a12beSStefan Roese ASM_STW(stk, 1, -4), 99*a47a12beSStefan Roese ASM_ADDI(stk, 1, -16), 100*a47a12beSStefan Roese ASM_STW(3, stk, 8), 101*a47a12beSStefan Roese ASM_STW(reg0, stk, 4), 102*a47a12beSStefan Roese ASM_STW(reg1, stk, 0), 103*a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8), 104*a47a12beSStefan Roese ASM_11IX(test->cmd, reg1, reg0, test->op2), 105*a47a12beSStefan Roese ASM_STW(reg1, stk, 8), 106*a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0), 107*a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4), 108*a47a12beSStefan Roese ASM_LWZ(3, stk, 8), 109*a47a12beSStefan Roese ASM_ADDI(1, stk, 16), 110*a47a12beSStefan Roese ASM_LWZ(stk, 1, -4), 111*a47a12beSStefan Roese ASM_BLR, 112*a47a12beSStefan Roese }; 113*a47a12beSStefan Roese ulong res; 114*a47a12beSStefan Roese ulong cr; 115*a47a12beSStefan Roese 116*a47a12beSStefan Roese cr = 0; 117*a47a12beSStefan Roese cpu_post_exec_21 (code, & cr, & res, test->op1); 118*a47a12beSStefan Roese 119*a47a12beSStefan Roese ret = res == test->res && cr == 0 ? 0 : -1; 120*a47a12beSStefan Roese 121*a47a12beSStefan Roese if (ret != 0) 122*a47a12beSStefan Roese { 123*a47a12beSStefan Roese post_log ("Error at threei test %d !\n", i); 124*a47a12beSStefan Roese } 125*a47a12beSStefan Roese } 126*a47a12beSStefan Roese } 127*a47a12beSStefan Roese 128*a47a12beSStefan Roese if (flag) 129*a47a12beSStefan Roese enable_interrupts(); 130*a47a12beSStefan Roese 131*a47a12beSStefan Roese return ret; 132*a47a12beSStefan Roese } 133*a47a12beSStefan Roese 134*a47a12beSStefan Roese #endif 135