1a47a12beSStefan Roese /* 2a47a12beSStefan Roese * (C) Copyright 2002 3a47a12beSStefan Roese * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4a47a12beSStefan Roese * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 6a47a12beSStefan Roese */ 7a47a12beSStefan Roese 8a47a12beSStefan Roese #include <common.h> 9a47a12beSStefan Roese 10a47a12beSStefan Roese /* 11a47a12beSStefan Roese * CPU test 12a47a12beSStefan Roese * Ternary instructions instr rA,rS,UIMM 13a47a12beSStefan Roese * 14a47a12beSStefan Roese * Logic instructions: ori, oris, xori, xoris 15a47a12beSStefan Roese * 16a47a12beSStefan Roese * The test contains a pre-built table of instructions, operands and 17a47a12beSStefan Roese * expected results. For each table entry, the test will cyclically use 18a47a12beSStefan Roese * different sets of operand registers and result registers. 19a47a12beSStefan Roese */ 20a47a12beSStefan Roese 21a47a12beSStefan Roese #include <post.h> 22a47a12beSStefan Roese #include "cpu_asm.h" 23a47a12beSStefan Roese 24a47a12beSStefan Roese #if CONFIG_POST & CONFIG_SYS_POST_CPU 25a47a12beSStefan Roese 26a47a12beSStefan Roese extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); 27a47a12beSStefan Roese extern ulong cpu_post_makecr (long v); 28a47a12beSStefan Roese 29a47a12beSStefan Roese static struct cpu_post_threei_s 30a47a12beSStefan Roese { 31a47a12beSStefan Roese ulong cmd; 32a47a12beSStefan Roese ulong op1; 33a47a12beSStefan Roese ushort op2; 34a47a12beSStefan Roese ulong res; 35a47a12beSStefan Roese } cpu_post_threei_table[] = 36a47a12beSStefan Roese { 37a47a12beSStefan Roese { 38a47a12beSStefan Roese OP_ORI, 39a47a12beSStefan Roese 0x80000000, 40a47a12beSStefan Roese 0xffff, 41a47a12beSStefan Roese 0x8000ffff 42a47a12beSStefan Roese }, 43a47a12beSStefan Roese { 44a47a12beSStefan Roese OP_ORIS, 45a47a12beSStefan Roese 0x00008000, 46a47a12beSStefan Roese 0xffff, 47a47a12beSStefan Roese 0xffff8000 48a47a12beSStefan Roese }, 49a47a12beSStefan Roese { 50a47a12beSStefan Roese OP_XORI, 51a47a12beSStefan Roese 0x8000ffff, 52a47a12beSStefan Roese 0xffff, 53a47a12beSStefan Roese 0x80000000 54a47a12beSStefan Roese }, 55a47a12beSStefan Roese { 56a47a12beSStefan Roese OP_XORIS, 57a47a12beSStefan Roese 0x00008000, 58a47a12beSStefan Roese 0xffff, 59a47a12beSStefan Roese 0xffff8000 60a47a12beSStefan Roese }, 61a47a12beSStefan Roese }; 62d2397817SMike Frysinger static unsigned int cpu_post_threei_size = ARRAY_SIZE(cpu_post_threei_table); 63a47a12beSStefan Roese 64a47a12beSStefan Roese int cpu_post_test_threei (void) 65a47a12beSStefan Roese { 66a47a12beSStefan Roese int ret = 0; 67a47a12beSStefan Roese unsigned int i, reg; 68a47a12beSStefan Roese int flag = disable_interrupts(); 69a47a12beSStefan Roese 70a47a12beSStefan Roese for (i = 0; i < cpu_post_threei_size && ret == 0; i++) 71a47a12beSStefan Roese { 72a47a12beSStefan Roese struct cpu_post_threei_s *test = cpu_post_threei_table + i; 73a47a12beSStefan Roese 74a47a12beSStefan Roese for (reg = 0; reg < 32 && ret == 0; reg++) 75a47a12beSStefan Roese { 76a47a12beSStefan Roese unsigned int reg0 = (reg + 0) % 32; 77a47a12beSStefan Roese unsigned int reg1 = (reg + 1) % 32; 78a47a12beSStefan Roese unsigned int stk = reg < 16 ? 31 : 15; 79a47a12beSStefan Roese unsigned long code[] = 80a47a12beSStefan Roese { 81a47a12beSStefan Roese ASM_STW(stk, 1, -4), 82a47a12beSStefan Roese ASM_ADDI(stk, 1, -16), 83a47a12beSStefan Roese ASM_STW(3, stk, 8), 84a47a12beSStefan Roese ASM_STW(reg0, stk, 4), 85a47a12beSStefan Roese ASM_STW(reg1, stk, 0), 86a47a12beSStefan Roese ASM_LWZ(reg0, stk, 8), 87a47a12beSStefan Roese ASM_11IX(test->cmd, reg1, reg0, test->op2), 88a47a12beSStefan Roese ASM_STW(reg1, stk, 8), 89a47a12beSStefan Roese ASM_LWZ(reg1, stk, 0), 90a47a12beSStefan Roese ASM_LWZ(reg0, stk, 4), 91a47a12beSStefan Roese ASM_LWZ(3, stk, 8), 92a47a12beSStefan Roese ASM_ADDI(1, stk, 16), 93a47a12beSStefan Roese ASM_LWZ(stk, 1, -4), 94a47a12beSStefan Roese ASM_BLR, 95a47a12beSStefan Roese }; 96a47a12beSStefan Roese ulong res; 97a47a12beSStefan Roese ulong cr; 98a47a12beSStefan Roese 99a47a12beSStefan Roese cr = 0; 100a47a12beSStefan Roese cpu_post_exec_21 (code, & cr, & res, test->op1); 101a47a12beSStefan Roese 102a47a12beSStefan Roese ret = res == test->res && cr == 0 ? 0 : -1; 103a47a12beSStefan Roese 104a47a12beSStefan Roese if (ret != 0) 105a47a12beSStefan Roese { 106a47a12beSStefan Roese post_log ("Error at threei test %d !\n", i); 107a47a12beSStefan Roese } 108a47a12beSStefan Roese } 109a47a12beSStefan Roese } 110a47a12beSStefan Roese 111a47a12beSStefan Roese if (flag) 112a47a12beSStefan Roese enable_interrupts(); 113a47a12beSStefan Roese 114a47a12beSStefan Roese return ret; 115a47a12beSStefan Roese } 116a47a12beSStefan Roese 117a47a12beSStefan Roese #endif 118